| commit | e4aa946c55a5769149f7e63d13e7ced505766966 | [log] [tgz] |
|---|---|---|
| author | Daniel Leung <daniel.leung@intel.com> | Fri Nov 02 13:24:28 2018 -0700 |
| committer | Anas Nashif <anas.nashif@intel.com> | Sat Nov 03 12:40:33 2018 -0400 |
| tree | e197d10a033aeb21433fd26e8fc054d95631ab72 | |
| parent | 5a47c60dbf4f24fa9ad2206502d5eab152587eac [diff] |
timer: xtensa_sys_timer: set compare register at init Since CCOMPARE* registers have undefined values after reset, set compare value first before enabling timer interrupt. Signed-off-by: Daniel Leung <daniel.leung@intel.com>