timer: xtensa_sys_timer: set compare register at init

Since CCOMPARE* registers have undefined values after reset,
set compare value first before enabling timer interrupt.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
diff --git a/drivers/timer/xtensa_sys_timer.c b/drivers/timer/xtensa_sys_timer.c
index 880b81f..072dd76 100644
--- a/drivers/timer/xtensa_sys_timer.c
+++ b/drivers/timer/xtensa_sys_timer.c
@@ -433,11 +433,16 @@
 	int val;
 
 	__asm__ volatile("rsr.intenable %0" : "=r"(val));
+
+	/*
+	 * Since CCOMPARE* registers have undefined values after reset,
+	 * set compare value first beforing enabling timer interrupt.
+	 */
+	SET_TIMER_FIRE_TIME(GET_TIMER_CURRENT_TIME() + _xt_tick_divisor);
+
 	val |= 1 << TIMER_IRQ;
 	__asm__ volatile("wsr.intenable %0" : : "r"(val));
 	__asm__ volatile("rsync");
-
-	SET_TIMER_FIRE_TIME(GET_TIMER_CURRENT_TIME() + _xt_tick_divisor);
 }
 #endif