| commit | e51b24b429bc603eb2fd12ea3c679cf3bf77abcc | [log] [tgz] |
|---|---|---|
| author | Eric Hay <EHay@sierrawireless.com> | Wed Oct 07 11:16:01 2020 -0700 |
| committer | Carles Cufí <carles.cufi@nordicsemi.no> | Fri Oct 09 11:49:39 2020 +0200 |
| tree | 6299ba293c38abaf3e21a3b9a6129034b9217344 | |
| parent | 31fca27d83f50bd5e99108148c79cca2b4179c8b [diff] |
drivers: clock_control: stm32g0: Enable the Q divisor on g0X1 variants The PLL Q divisor does not exist on stm32g0X0 variants. It should only be configured for g0X1 variants. Signed-off-by: Eric Hay <EHay@sierrawireless.com>