arm: relinquish one IRQ priority reserved by kernel
The Cortex-M3/4 kernel was reserving priorities 0 and 1 for itself, but
was not registering any exception on priority 0. Only reserve priority 0
and use it for SVC and fault exceptions instead of priority 1.
Change-Id: Iff2405e27fd4bed4e49ab90ec2ae984f2c0a83a6
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
diff --git a/arch/arm/include/cortex_m/exc.h b/arch/arm/include/cortex_m/exc.h
index 6157f61..601de64 100644
--- a/arch/arm/include/cortex_m/exc.h
+++ b/arch/arm/include/cortex_m/exc.h
@@ -72,16 +72,20 @@
static ALWAYS_INLINE void _ExcSetup(void)
{
_ScbExcPrioSet(_EXC_PENDSV, _EXC_PRIO(0xff));
-#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
- _ScbExcPrioSet(_EXC_SVC, _EXC_PRIO(0x01));
- _ScbExcPrioSet(_EXC_MPU_FAULT, _EXC_PRIO(0x01));
- _ScbExcPrioSet(_EXC_BUS_FAULT, _EXC_PRIO(0x01));
- _ScbExcPrioSet(_EXC_USAGE_FAULT, _EXC_PRIO(0x01));
+
+#ifdef CONFIG_CPU_CORTEX_M_HAS_BASEPRI
+ _ScbExcPrioSet(_EXC_SVC, _EXC_PRIO(_EXC_SVC_PRIO));
+#endif
+
+#ifdef CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
+ _ScbExcPrioSet(_EXC_MPU_FAULT, _EXC_PRIO(_EXC_FAULT_PRIO));
+ _ScbExcPrioSet(_EXC_BUS_FAULT, _EXC_PRIO(_EXC_FAULT_PRIO));
+ _ScbExcPrioSet(_EXC_USAGE_FAULT, _EXC_PRIO(_EXC_FAULT_PRIO));
_ScbUsageFaultEnable();
_ScbBusFaultEnable();
_ScbMemFaultEnable();
-#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */
+#endif
}
#endif /* _ASMLANGUAGE */
diff --git a/include/arch/arm/cortex_m/nvic.h b/include/arch/arm/cortex_m/nvic.h
index 4deaf8e..9705233 100644
--- a/include/arch/arm/cortex_m/nvic.h
+++ b/include/arch/arm/cortex_m/nvic.h
@@ -47,30 +47,27 @@
#define _EXC_PRIO(pri) (((pri) << (8 - CONFIG_NUM_IRQ_PRIO_BITS)) & 0xff)
#ifdef CONFIG_ZERO_LATENCY_IRQS
-#define ZERO_LATENCY_IRQS_RESERVED_PRIO 1
+#define _ZERO_LATENCY_IRQS_RESERVED_PRIO 1
#else
-#define ZERO_LATENCY_IRQS_RESERVED_PRIO 0
+#define _ZERO_LATENCY_IRQS_RESERVED_PRIO 0
#endif
-#ifdef CONFIG_CPU_CORTEX_M_HAS_BASEPRI
-#define HAS_BASEPRI_RESERVED_PRIO 1
+#if defined(CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS) || \
+ defined(CONFIG_CPU_CORTEX_M_HAS_BASEPRI)
+#define _EXCEPTION_RESERVED_PRIO 1
#else
-#define HAS_BASEPRI_RESERVED_PRIO 0
-#endif
-
-#ifdef CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
-#define HAS_PROGRAMMABLE_FAULT_PRIOS_RESERVED_PRIO 1
-#else
-#define HAS_PROGRAMMABLE_FAULT_PRIOS_RESERVED_PRIO 0
+#define _EXCEPTION_RESERVED_PRIO 0
#endif
#define _IRQ_PRIO_OFFSET \
- (ZERO_LATENCY_IRQS_RESERVED_PRIO + \
- HAS_BASEPRI_RESERVED_PRIO + \
- HAS_PROGRAMMABLE_FAULT_PRIOS_RESERVED_PRIO)
+ (_ZERO_LATENCY_IRQS_RESERVED_PRIO + \
+ _EXCEPTION_RESERVED_PRIO)
#define _EXC_IRQ_DEFAULT_PRIO _EXC_PRIO(_IRQ_PRIO_OFFSET)
+#define _EXC_SVC_PRIO 0
+#define _EXC_FAULT_PRIO 0
+
/* no exc #0 */
#define _EXC_RESET 1
#define _EXC_NMI 2
