arch/xtensa: smp: only zero BSS only when boot from CPU #0
Under SMP, the main BSS section only needs to be zero-ed on CPU #0.
Other CPUs should not zero out BSS, or else it may cause CPU #0 to
crash on invalid data.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
diff --git a/arch/xtensa/core/crt1.S b/arch/xtensa/core/crt1.S
index bebecd7..f1d7186 100644
--- a/arch/xtensa/core/crt1.S
+++ b/arch/xtensa/core/crt1.S
@@ -136,6 +136,14 @@
/* Clear a0 again as possible CALLX to __memmap_init changed it. */
movi a0, 0
# endif
+
+# ifdef CONFIG_SMP
+ /* Only clear BSS when running on core 0 */
+ rsr a3, PRID
+ extui a3, a3, 0, 8 /* extract core ID */
+ bnez a3, .L3zte
+# endif
+
/*
* Clear the BSS (uninitialized data) segments.
* This code supports multiple zeroed sections (*.bss).
