usb: dc_dw: Improve TX perf and reliability
During large USB transfer it's pretty common to call ep_write whereas
the previous TX transfer is not achieved and so the TX FIFO space is
not available. Sleeping 20ms in this case introduce a relatively high
latency and reduce the throughput.
This can be observed when pinging the board with CDC-ECM net class.
ping reply is split into 2 USB TX transfer, the second one is only
triggered after 20ms, making ping latency > 20ms.
To fix this, just continuously read the FIFO availabilty and fire TX
as soon as possible.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
1 file changed
