drivers: espi: npcx: add espi support for npck3
This commit adds eSPI support for npck3, including support for the
maximum frequency of 66MHz. The method to read the level of eSPI reset
pin differs on npck3, so the definition of eSPI_RST has been updated
accordingly.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
diff --git a/boards/nuvoton/npck3m8k_evb/npck3m8k_evb.dts b/boards/nuvoton/npck3m8k_evb/npck3m8k_evb.dts
index becdab3..76ba87c 100644
--- a/boards/nuvoton/npck3m8k_evb/npck3m8k_evb.dts
+++ b/boards/nuvoton/npck3m8k_evb/npck3m8k_evb.dts
@@ -94,7 +94,7 @@
};
&espi0 {
- status = "disabled";
+ status = "okay";
pinctrl-0 = <&espi_lpc_gp10_f7>;
pinctrl-names = "default";
};
diff --git a/drivers/espi/espi_npcx.c b/drivers/espi/espi_npcx.c
index dc57efc..f656082 100644
--- a/drivers/espi/espi_npcx.c
+++ b/drivers/espi/espi_npcx.c
@@ -25,6 +25,12 @@
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(espi, CONFIG_ESPI_LOG_LEVEL);
+#if defined(CONFIG_NPCX_SOC_VARIANT_NPCKN)
+BUILD_ASSERT(DT_INST_NODE_HAS_PROP(0, rst_gpios), "Need rst_gpios to be defined");
+#else
+BUILD_ASSERT(!DT_INST_NODE_HAS_PROP(0, rst_gpios), "Reset of eSPI via GPIO is not supported");
+#endif
+
struct espi_npcx_config {
uintptr_t base;
/* clock configuration */
@@ -33,6 +39,9 @@
struct npcx_wui espi_rst_wui;
/* pinmux configuration */
const struct pinctrl_dev_config *pcfg;
+#if DT_INST_NODE_HAS_PROP(0, rst_gpios)
+ struct gpio_dt_spec reset_pin;
+#endif
};
struct espi_npcx_data {
@@ -701,12 +710,19 @@
static void espi_vw_espi_rst_isr(const struct device *dev, struct npcx_wui *wui)
{
- struct espi_reg *const inst = HAL_INSTANCE(dev);
struct espi_npcx_data *const data = dev->data;
struct espi_event evt = { ESPI_BUS_RESET, 0, 0 };
- data->espi_rst_level = IS_BIT_SET(inst->ESPISTS,
- NPCX_ESPISTS_ESPIRST_LVL);
+#if DT_INST_NODE_HAS_PROP(0, rst_gpios)
+ const struct espi_npcx_config *const config = dev->config;
+
+ data->espi_rst_level = gpio_pin_get_raw(config->reset_pin.port,
+ config->reset_pin.pin);
+#else
+ struct espi_reg *const inst = HAL_INSTANCE(dev);
+
+ data->espi_rst_level = IS_BIT_SET(inst->ESPISTS, NPCX_ESPISTS_ESPIRST_LVL);
+#endif
LOG_DBG("eSPI RST level is %d!", data->espi_rst_level);
evt.evt_data = data->espi_rst_level;
@@ -735,7 +751,7 @@
case 50:
max_freq = NPCX_ESPI_MAXFREQ_50;
break;
-#ifdef CONFIG_SOC_SERIES_NPCX4
+#if defined(CONFIG_ESPI_NPCX_NPCXN_V3) || defined(CONFIG_ESPI_NPCX_NPCKN_V1)
case 66:
max_freq = NPCX_ESPI_MAXFREQ_66;
break;
@@ -1407,6 +1423,9 @@
.espi_rst_wui = NPCX_DT_WUI_ITEM_BY_NAME(0, espi_rst_wui),
.clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
+#if DT_INST_NODE_HAS_PROP(0, rst_gpios)
+ .reset_pin = GPIO_DT_SPEC_INST_GET(0, rst_gpios),
+#endif
};
DEVICE_DT_INST_DEFINE(0, &espi_npcx_init, NULL,
@@ -1427,6 +1446,13 @@
return -ENODEV;
}
+#if DT_INST_NODE_HAS_PROP(0, rst_gpios)
+ if (!gpio_is_ready_dt(&config->reset_pin)) {
+ LOG_ERR("eSPI reset pin not ready");
+ return -ENODEV;
+ }
+#endif
+
/* Turn on eSPI device clock first */
ret = clock_control_on(clk_dev, (clock_control_subsys_t)
&config->clk_cfg);
diff --git a/dts/arm/nuvoton/npck/npck3.dtsi b/dts/arm/nuvoton/npck/npck3.dtsi
index 104e778..ec4baff 100644
--- a/dts/arm/nuvoton/npck/npck3.dtsi
+++ b/dts/arm/nuvoton/npck/npck3.dtsi
@@ -252,6 +252,8 @@
rx-plsize = <64>;
tx-plsize = <64>;
+ rst-gpios = <&gpio1 0 0>;
+
#address-cells = <1>;
#size-cells = <1>;
diff --git a/dts/bindings/espi/nuvoton,npcx-espi.yaml b/dts/bindings/espi/nuvoton,npcx-espi.yaml
index 51bdd77..5125196 100644
--- a/dts/bindings/espi/nuvoton,npcx-espi.yaml
+++ b/dts/bindings/espi/nuvoton,npcx-espi.yaml
@@ -31,6 +31,10 @@
For example the WUI mapping on NPCX7 would be
espi-rst-wui = <&wui_cr_sin1>;
+ rst-gpios:
+ type: phandle-array
+ description: Definition of the eSPI reset GPIO pin for the NPCKn variant.
+
rx-plsize:
type: int
required: true
diff --git a/soc/nuvoton/npcx/npck3/Kconfig b/soc/nuvoton/npcx/npck3/Kconfig
index 423c92c..e4f1e5b 100644
--- a/soc/nuvoton/npcx/npck3/Kconfig
+++ b/soc/nuvoton/npcx/npck3/Kconfig
@@ -11,6 +11,7 @@
select CPU_HAS_ARM_MPU
select HAS_PM
select HAS_SWO
+ select SOC_EARLY_INIT_HOOK
if SOC_SERIES_NPCK3
diff --git a/soc/nuvoton/npcx/npck3/soc.c b/soc/nuvoton/npcx/npck3/soc.c
index de1057a..1fadbae 100644
--- a/soc/nuvoton/npcx/npck3/soc.c
+++ b/soc/nuvoton/npcx/npck3/soc.c
@@ -12,6 +12,8 @@
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+extern void scfg_init(void);
+
void soc_early_init_hook(void)
{
struct glue_reg *inst_glue = (struct glue_reg *)
@@ -29,4 +31,6 @@
/* Core debugging interface is disabled */
inst_scfg->DEVCNT |= BIT(1);
}
+
+ scfg_init();
}
