arch: aarch32: add caches capability to Cortex-R52
Support I/D cache for Cortex-R52 to run with cache on NXP S32Z/E.
Make sure no data is present in the D-Cache before initializing mpu
Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
diff --git a/arch/arm/core/aarch32/cortex_a_r/Kconfig b/arch/arm/core/aarch32/cortex_a_r/Kconfig
index 00ed0bb..418aa9a 100644
--- a/arch/arm/core/aarch32/cortex_a_r/Kconfig
+++ b/arch/arm/core/aarch32/cortex_a_r/Kconfig
@@ -97,6 +97,8 @@
bool
select CPU_AARCH32_CORTEX_R
select AARCH32_ARMV8_R
+ select CPU_HAS_ICACHE
+ select CPU_HAS_DCACHE
help
This option signifies the use of a Cortex-R52 CPU
diff --git a/arch/arm/core/aarch32/mpu/arm_mpu.c b/arch/arm/core/aarch32/mpu/arm_mpu.c
index 55b20a0..f41f497 100644
--- a/arch/arm/core/aarch32/mpu/arm_mpu.c
+++ b/arch/arm/core/aarch32/mpu/arm_mpu.c
@@ -350,11 +350,17 @@
/* Clean and invalidate data cache if it is enabled and
* that was not already done at boot
*/
+#if defined(CONFIG_CPU_AARCH32_CORTEX_R)
+ if (__get_SCTLR() & SCTLR_C_Msk) {
+ L1C_CleanInvalidateDCacheAll();
+ }
+#else
#if !defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
if (SCB->CCR & SCB_CCR_DC_Msk) {
SCB_CleanInvalidateDCache();
}
#endif
+#endif
#endif /* CONFIG_NOCACHE_MEMORY */
/* Architecture-specific configuration */
