drivers: ethernet: Run clang-format before applying a patch
This patch just formats the file before the real patch, otherwise
the changes would be hard to read.
The only addition was a third parameter (NULL) to all the usages
of the macro WAIT_FOR, since the dangling comma triggered conflicts
between clang-format and check_compliance.py.
Signed-off-by: Marcelo Roberto Jimenez <marcelo.jimenez@gmail.com>
diff --git a/drivers/ethernet/eth_xmc4xxx.c b/drivers/ethernet/eth_xmc4xxx.c
index 81294da..1d2a4f3 100644
--- a/drivers/ethernet/eth_xmc4xxx.c
+++ b/drivers/ethernet/eth_xmc4xxx.c
@@ -43,14 +43,20 @@
#define INFINEON_OUI_B1 0x03
#define INFINEON_OUI_B2 0x19
-#define MODULO_INC_TX(val) {(val) = (++(val) < NUM_TX_DMA_DESCRIPTORS) ? (val) : 0; }
-#define MODULO_INC_RX(val) {(val) = (++(val) < NUM_RX_DMA_DESCRIPTORS) ? (val) : 0; }
+#define MODULO_INC_TX(val) \
+ { \
+ (val) = (++(val) < NUM_TX_DMA_DESCRIPTORS) ? (val) : 0; \
+ }
+#define MODULO_INC_RX(val) \
+ { \
+ (val) = (++(val) < NUM_RX_DMA_DESCRIPTORS) ? (val) : 0; \
+ }
#define IS_OWNED_BY_DMA_TX(desc) (((desc)->status & ETH_MAC_DMA_TDES0_OWN) != 0)
#define IS_OWNED_BY_DMA_RX(desc) (((desc)->status & ETH_MAC_DMA_RDES0_OWN) != 0)
#define IS_START_OF_FRAME_RX(desc) (((desc)->status & ETH_MAC_DMA_RDES0_FS) != 0)
-#define IS_END_OF_FRAME_RX(desc) (((desc)->status & ETH_MAC_DMA_RDES0_LS) != 0)
+#define IS_END_OF_FRAME_RX(desc) (((desc)->status & ETH_MAC_DMA_RDES0_LS) != 0)
#define IS_TIMESTAMP_AVAILABLE_RX(desc) (((desc)->status & ETH_MAC_DMA_RDES0_TSA) != 0)
#define IS_TIMESTAMP_AVAILABLE_TX(desc) (((desc)->status & ETH_MAC_DMA_TDES0_TTSS) != 0)
@@ -69,23 +75,23 @@
XMC_ETH_MAC_EVENT_RECEIVE | XMC_ETH_MAC_EVENT_TRANSMIT | ETH_INTERRUPT_ENABLE_NIE_Msk | \
ETH_INTERRUPT_ENABLE_AIE_Msk)
-#define ETH_MAC_DISABLE_MMC_INTERRUPT_MSK 0x03ffffffu
-#define ETH_MAC_DISABLE_MMC_IPC_RECEIVE_INTERRUPT_MSK 0x3fff3fffu
+#define ETH_MAC_DISABLE_MMC_INTERRUPT_MSK 0x03ffffffu
+#define ETH_MAC_DISABLE_MMC_IPC_RECEIVE_INTERRUPT_MSK 0x3fff3fffu
#define ETH_STATUS_CLEARABLE_BITS 0x1e7ffu
#define ETH_RX_DMA_DESC_SECOND_ADDR_CHAINED_MASK BIT(14)
-#define ETH_RESET_TIMEOUT_USEC 200000u
+#define ETH_RESET_TIMEOUT_USEC 200000u
#define ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC 100000u
-#define ETH_LINK_SPEED_10M 0
+#define ETH_LINK_SPEED_10M 0
#define ETH_LINK_SPEED_100M 1
#define ETH_LINK_DUPLEX_HALF 0
#define ETH_LINK_DUPLEX_FULL 1
-#define ETH_PTP_CLOCK_FREQUENCY 50000000
+#define ETH_PTP_CLOCK_FREQUENCY 50000000
#define ETH_PTP_RATE_ADJUST_RATIO_MIN 0.9
#define ETH_PTP_RATE_ADJUST_RATIO_MAX 1.1
@@ -467,7 +473,6 @@
dma_desc = &rx_dma_desc[tail];
}
-
MODULO_INC_RX(tail);
dev_data->dma_desc_rx_tail = tail;
@@ -605,12 +610,10 @@
reg &= ~(ETH_MAC_CONFIGURATION_DM_Msk | ETH_MAC_CONFIGURATION_FES_Msk);
- val = PHY_LINK_IS_FULL_DUPLEX(state->speed) ? ETH_LINK_DUPLEX_FULL :
- ETH_LINK_DUPLEX_HALF;
+ val = PHY_LINK_IS_FULL_DUPLEX(state->speed) ? ETH_LINK_DUPLEX_FULL : ETH_LINK_DUPLEX_HALF;
reg |= FIELD_PREP(ETH_MAC_CONFIGURATION_DM_Msk, val);
- val = PHY_LINK_IS_SPEED_100M(state->speed) ? ETH_LINK_SPEED_100M :
- ETH_LINK_SPEED_10M;
+ val = PHY_LINK_IS_SPEED_100M(state->speed) ? ETH_LINK_SPEED_100M : ETH_LINK_SPEED_10M;
reg |= FIELD_PREP(ETH_MAC_CONFIGURATION_FES_Msk, val);
regs->MAC_CONFIGURATION = reg;
@@ -708,8 +711,8 @@
for (int i = 0; i < NUM_RX_DMA_DESCRIPTORS; i++) {
XMC_ETH_MAC_DMA_DESC_t *dma_desc = &rx_dma_desc[i];
- struct net_buf *rx_buf = net_pkt_get_reserve_rx_data(CONFIG_NET_BUF_DATA_SIZE,
- K_NO_WAIT);
+ struct net_buf *rx_buf =
+ net_pkt_get_reserve_rx_data(CONFIG_NET_BUF_DATA_SIZE, K_NO_WAIT);
if (rx_buf == NULL) {
eth_xmc4xxx_free_rx_bufs(dev);
@@ -733,8 +736,8 @@
dev_cfg->regs->BUS_MODE |= ETH_BUS_MODE_SWR_Msk;
/* reset may fail if the clocks are not properly setup */
- if (!WAIT_FOR((dev_cfg->regs->BUS_MODE & ETH_BUS_MODE_SWR_Msk) == 0,
- ETH_RESET_TIMEOUT_USEC,)) {
+ if (!WAIT_FOR((dev_cfg->regs->BUS_MODE & ETH_BUS_MODE_SWR_Msk) == 0, ETH_RESET_TIMEOUT_USEC,
+ NULL)) {
return -ETIMEDOUT;
}
@@ -763,14 +766,14 @@
static inline int eth_xmc4xxx_init_timestamp_control_reg(ETH_GLOBAL_TypeDef *regs)
{
#if defined(CONFIG_NET_GPTP)
- regs->TIMESTAMP_CONTROL = ETH_TIMESTAMP_CONTROL_TSENA_Msk |
- ETH_TIMESTAMP_CONTROL_TSENALL_Msk;
+ regs->TIMESTAMP_CONTROL =
+ ETH_TIMESTAMP_CONTROL_TSENA_Msk | ETH_TIMESTAMP_CONTROL_TSENALL_Msk;
#endif
#if defined(CONFIG_PTP_CLOCK_XMC4XXX)
/* use fine control */
- regs->TIMESTAMP_CONTROL |= ETH_TIMESTAMP_CONTROL_TSCFUPDT_Msk |
- ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Msk;
+ regs->TIMESTAMP_CONTROL |=
+ ETH_TIMESTAMP_CONTROL_TSCFUPDT_Msk | ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Msk;
/* make ptp run at 50MHz - implies 20ns increment for each increment of the */
/* sub_second_register */
@@ -780,20 +783,20 @@
/* Therefore, K = ceil(f_out * 2^32 / f_cpu) */
uint32_t f_cpu = XMC_SCU_CLOCK_GetSystemClockFrequency();
- uint32_t K = (BIT64(32) * ETH_PTP_CLOCK_FREQUENCY + f_cpu / 2) / f_cpu;
+ uint32_t K = (BIT64(32) * ETH_PTP_CLOCK_FREQUENCY + f_cpu / 2) / f_cpu;
regs->TIMESTAMP_ADDEND = K;
/* Addend register update */
regs->TIMESTAMP_CONTROL |= ETH_TIMESTAMP_CONTROL_TSADDREG_Msk;
if (!WAIT_FOR((regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSADDREG_Msk) == 0,
- ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC,)) {
+ ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC, NULL)) {
return -ETIMEDOUT;
}
regs->TIMESTAMP_CONTROL |= ETH_TIMESTAMP_CONTROL_TSINIT_Msk;
if (!WAIT_FOR((regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSINIT_Msk) == 0,
- ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC,)) {
+ ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC, NULL)) {
return -ETIMEDOUT;
}
#endif
@@ -808,8 +811,7 @@
int ret;
sys_slist_init(&dev_data->tx_frame_list);
- k_sem_init(&dev_data->tx_desc_sem, NUM_TX_DMA_DESCRIPTORS,
- NUM_TX_DMA_DESCRIPTORS);
+ k_sem_init(&dev_data->tx_desc_sem, NUM_TX_DMA_DESCRIPTORS, NUM_TX_DMA_DESCRIPTORS);
if (!device_is_ready(dev_cfg->phy_dev)) {
LOG_ERR("Phy device not ready");
@@ -842,7 +844,6 @@
/* disable jumbo frames */
dev_cfg->regs->MAC_CONFIGURATION &= ~ETH_MAC_CONFIGURATION_JE_Msk;
-
/* Initialize Filter registers - disable zero quanta pause*/
dev_cfg->regs->FLOW_CONTROL = ETH_FLOW_CONTROL_DZPQ_Msk;
@@ -893,8 +894,8 @@
static enum ethernet_hw_caps eth_xmc4xxx_capabilities(const struct device *dev)
{
ARG_UNUSED(dev);
- enum ethernet_hw_caps caps = ETHERNET_LINK_10BASE | ETHERNET_LINK_100BASE |
- ETHERNET_HW_TX_CHKSUM_OFFLOAD | ETHERNET_HW_RX_CHKSUM_OFFLOAD;
+ enum ethernet_hw_caps caps = ETHERNET_LINK_10BASE | ETHERNET_LINK_100BASE |
+ ETHERNET_HW_TX_CHKSUM_OFFLOAD | ETHERNET_HW_RX_CHKSUM_OFFLOAD;
#if defined(CONFIG_PTP_CLOCK_XMC4XXX)
caps |= ETHERNET_PTP;
@@ -947,7 +948,6 @@
}
#endif
-
#if defined(CONFIG_ETH_XMC4XXX_VLAN_HW_FILTER)
int eth_xmc4xxx_vlan_setup(const struct device *dev, struct net_if *iface, uint16_t tag,
bool enable)
@@ -959,8 +959,7 @@
if (enable) {
dev_cfg->regs->VLAN_TAG = FIELD_PREP(ETH_VLAN_TAG_VL_Msk, tag) |
- ETH_VLAN_TAG_ETV_Msk |
- ETH_VLAN_TAG_ESVL_Msk;
+ ETH_VLAN_TAG_ETV_Msk | ETH_VLAN_TAG_ESVL_Msk;
dev_cfg->regs->MAC_FRAME_FILTER |= ETH_MAC_FRAME_FILTER_VTFE_Msk;
} else {
dev_cfg->regs->VLAN_TAG = 0;
@@ -996,19 +995,18 @@
.phy_dev = DEVICE_DT_GET(DT_INST_PHANDLE(0, phy_handle)),
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
.port_ctrl = {
- .rxd0 = DT_INST_ENUM_IDX(0, rxd0_port_ctrl),
- .rxd1 = DT_INST_ENUM_IDX(0, rxd1_port_ctrl),
- .rxd2 = DT_INST_ENUM_IDX_OR(0, rxd2_port_ctrl, 0),
- .rxd3 = DT_INST_ENUM_IDX_OR(0, rxd3_port_ctrl, 0),
- .clk_rmii = DT_INST_ENUM_IDX(0, rmii_rx_clk_port_ctrl),
- .crs_dv = DT_INST_ENUM_IDX(0, crs_rx_dv_port_ctrl),
- .crs = DT_INST_ENUM_IDX_OR(0, crs_port_ctrl, 0),
- .rxer = DT_INST_ENUM_IDX(0, rxer_port_ctrl),
- .col = DT_INST_ENUM_IDX_OR(0, col_port_ctrl, 0),
- .clk_tx = DT_INST_ENUM_IDX_OR(0, tx_clk_port_ctrl, 0),
- .mode = DT_INST_ENUM_IDX_OR(0, phy_connection_type, 0),
- }
-};
+ .rxd0 = DT_INST_ENUM_IDX(0, rxd0_port_ctrl),
+ .rxd1 = DT_INST_ENUM_IDX(0, rxd1_port_ctrl),
+ .rxd2 = DT_INST_ENUM_IDX_OR(0, rxd2_port_ctrl, 0),
+ .rxd3 = DT_INST_ENUM_IDX_OR(0, rxd3_port_ctrl, 0),
+ .clk_rmii = DT_INST_ENUM_IDX(0, rmii_rx_clk_port_ctrl),
+ .crs_dv = DT_INST_ENUM_IDX(0, crs_rx_dv_port_ctrl),
+ .crs = DT_INST_ENUM_IDX_OR(0, crs_port_ctrl, 0),
+ .rxer = DT_INST_ENUM_IDX(0, rxer_port_ctrl),
+ .col = DT_INST_ENUM_IDX_OR(0, col_port_ctrl, 0),
+ .clk_tx = DT_INST_ENUM_IDX_OR(0, tx_clk_port_ctrl, 0),
+ .mode = DT_INST_ENUM_IDX_OR(0, phy_connection_type, 0),
+ }};
static struct eth_xmc4xxx_data eth_xmc4xxx_data = {
.mac_addr = DT_INST_PROP_OR(0, local_mac_address, {0}),
@@ -1035,7 +1033,7 @@
dev_cfg->regs->TIMESTAMP_CONTROL |= ETH_TIMESTAMP_CONTROL_TSINIT_Msk;
if (!WAIT_FOR((dev_cfg->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSINIT_Msk) == 0,
- ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC,)) {
+ ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC, NULL)) {
return -ETIMEDOUT;
}
@@ -1088,7 +1086,7 @@
dev_cfg->regs->TIMESTAMP_CONTROL |= ETH_TIMESTAMP_CONTROL_TSUPDT_Msk;
if (!WAIT_FOR((dev_cfg->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSUPDT_Msk) == 0,
- ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC,)) {
+ ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC, NULL)) {
return -ETIMEDOUT;
}
@@ -1116,7 +1114,7 @@
/* Addend register update */
dev_cfg->regs->TIMESTAMP_CONTROL |= ETH_TIMESTAMP_CONTROL_TSADDREG_Msk;
if (!WAIT_FOR((dev_cfg->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSADDREG_Msk) == 0,
- ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC,)) {
+ ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC, NULL)) {
return -ETIMEDOUT;
}
