arch: xtensa: Get CPU clock frequency from DTS
The SoC initialization code used system clock frequency
as a CPU clock frequency. This commit corrects that by
obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
diff --git a/arch/xtensa/include/xtensa_rtos.h b/arch/xtensa/include/xtensa_rtos.h
index 0ebd0f3..16c11ff 100644
--- a/arch/xtensa/include/xtensa_rtos.h
+++ b/arch/xtensa/include/xtensa_rtos.h
@@ -46,10 +46,8 @@
#define XT_BOARD 1
#endif
-#ifdef CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
- #undef XT_CLOCK_FREQ
- #define XT_CLOCK_FREQ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
-#endif
+#undef XT_CLOCK_FREQ
+#define XT_CLOCK_FREQ DT_CPU_CLOCK_FREQUENCY
#ifndef XT_TIMER_INDEX
#if defined configXT_TIMER_INDEX
diff --git a/arch/xtensa/include/xtensa_timer.h b/arch/xtensa/include/xtensa_timer.h
index 1fa29f3..089b3e2 100644
--- a/arch/xtensa/include/xtensa_timer.h
+++ b/arch/xtensa/include/xtensa_timer.h
@@ -115,7 +115,7 @@
* anyway!).
*/
#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)
-#define XT_CLOCK_FREQ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
+#define XT_CLOCK_FREQ DT_CPU_CLOCK_FREQUENCY
#endif
#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)
diff --git a/soc/xtensa/esp32/dts_fixup.h b/soc/xtensa/esp32/dts_fixup.h
new file mode 100644
index 0000000..f17d286
--- /dev/null
+++ b/soc/xtensa/esp32/dts_fixup.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2018 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* SoC level DTS fixup file */
+
+#define DT_CPU_CLOCK_FREQUENCY DT_CADENCE_TENSILICA_XTENSA_LX6_0_CLOCK_FREQUENCY
+
+/* End of SoC Level DTS fixup file */
diff --git a/soc/xtensa/intel_s1000/dts_fixup.h b/soc/xtensa/intel_s1000/dts_fixup.h
index 66a1f83..3740d77 100644
--- a/soc/xtensa/intel_s1000/dts_fixup.h
+++ b/soc/xtensa/intel_s1000/dts_fixup.h
@@ -2,6 +2,8 @@
/* SoC level DTS fixup file */
+#define DT_CPU_CLOCK_FREQUENCY DT_CADENCE_TENSILICA_XTENSA_LX6_0_CLOCK_FREQUENCY
+
#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_80800_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_80800_CURRENT_SPEED
#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_80800_LABEL
diff --git a/soc/xtensa/sample_controller/dts_fixup.h b/soc/xtensa/sample_controller/dts_fixup.h
new file mode 100644
index 0000000..a38b46b
--- /dev/null
+++ b/soc/xtensa/sample_controller/dts_fixup.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2018 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* SoC level DTS fixup file */
+
+#define DT_CPU_CLOCK_FREQUENCY DT_SAMPLE_CONTROLLER_0_CLOCK_FREQUENCY
+
+/* End of SoC Level DTS fixup file */
