| commit | f3c681166b67bcd2a712b6520e1775a158ecbb90 | [log] [tgz] |
|---|---|---|
| author | Francois Ramu <francois.ramu@st.com> | Tue Jan 05 16:13:24 2021 +0100 |
| committer | Maureen Helm <maureen.helm@nxp.com> | Wed Jan 06 08:09:47 2021 -0600 |
| tree | 17927c28125011b509f70de475798d72b29cc0c2 | |
| parent | f58f6b8cfb2a21549d5fbaf66c5c2642920a8c4d [diff] |
drivers: clock_control: stm32g0 soc enables the PWR clock After system reset, the PWR interface clock must be enabled by setting the PWREN bit of the RCC_APBENR1 This sequence is needed to use the RTC. Signed-off-by: Francois Ramu <francois.ramu@st.com>