dts: arm: st: stm32g0: remove U suffix from "resets" in DTSI
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
diff --git a/dts/arm/st/g0/stm32g0.dtsi b/dts/arm/st/g0/stm32g0.dtsi
index ecd3183..2743b45 100644
--- a/dts/arm/st/g0/stm32g0.dtsi
+++ b/dts/arm/st/g0/stm32g0.dtsi
@@ -241,7 +241,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1_2, 14)>;
- resets = <&rctl STM32_RESET(APB1H, 14U)>;
+ resets = <&rctl STM32_RESET(APB1H, 14)>;
interrupts = <27 0>;
status = "disabled";
};
@@ -250,7 +250,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
- resets = <&rctl STM32_RESET(APB1L, 17U)>;
+ resets = <&rctl STM32_RESET(APB1L, 17)>;
interrupts = <28 0>;
status = "disabled";
};
@@ -271,7 +271,7 @@
reg = <0x40012C00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1_2, 11)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1H, 11U)>;
+ resets = <&rctl STM32_RESET(APB1H, 11)>;
interrupts = <13 0>, <14 0>;
interrupt-names = "brk_up_trg_com", "cc";
st,prescaler = <0>;
@@ -300,7 +300,7 @@
reg = <0x40000400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 1)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 1U)>;
+ resets = <&rctl STM32_RESET(APB1L, 1)>;
interrupts = <16 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -329,7 +329,7 @@
reg = <0x40002000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1_2, 15)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1H, 15U)>;
+ resets = <&rctl STM32_RESET(APB1H, 15)>;
interrupts = <19 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -352,7 +352,7 @@
reg = <0x40014400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1_2, 17)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1H, 17U)>;
+ resets = <&rctl STM32_RESET(APB1H, 17)>;
interrupts = <21 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -375,7 +375,7 @@
reg = <0x40014800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1_2, 18)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1H, 18U)>;
+ resets = <&rctl STM32_RESET(APB1H, 18)>;
interrupts = <22 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/g0/stm32g031.dtsi b/dts/arm/st/g0/stm32g031.dtsi
index cc89fef..7e2935a 100644
--- a/dts/arm/st/g0/stm32g031.dtsi
+++ b/dts/arm/st/g0/stm32g031.dtsi
@@ -16,7 +16,7 @@
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x40008000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 20)>;
- resets = <&rctl STM32_RESET(APB1L, 20U)>;
+ resets = <&rctl STM32_RESET(APB1L, 20)>;
interrupts = <29 0>;
status = "disabled";
};
@@ -31,7 +31,7 @@
reg = <0x40000000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 0)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 0U)>;
+ resets = <&rctl STM32_RESET(APB1L, 0)>;
interrupts = <15 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/g0/stm32g050.dtsi b/dts/arm/st/g0/stm32g050.dtsi
index 0912b8b..86d953a 100644
--- a/dts/arm/st/g0/stm32g050.dtsi
+++ b/dts/arm/st/g0/stm32g050.dtsi
@@ -15,7 +15,7 @@
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 4)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 4U)>;
+ resets = <&rctl STM32_RESET(APB1L, 4)>;
interrupts = <17 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -27,7 +27,7 @@
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 5)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 5U)>;
+ resets = <&rctl STM32_RESET(APB1L, 5)>;
interrupts = <18 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/g0/stm32g051.dtsi b/dts/arm/st/g0/stm32g051.dtsi
index 2dd5134..424b1d7 100644
--- a/dts/arm/st/g0/stm32g051.dtsi
+++ b/dts/arm/st/g0/stm32g051.dtsi
@@ -15,7 +15,7 @@
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 4)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 4U)>;
+ resets = <&rctl STM32_RESET(APB1L, 4)>;
interrupts = <17 0>;
interrupt-names = "global";
status = "disabled";
@@ -31,7 +31,7 @@
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 5)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 5U)>;
+ resets = <&rctl STM32_RESET(APB1L, 5)>;
interrupts = <18 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -48,7 +48,7 @@
reg = <0x40014000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1_2, 16)>,
<&rcc STM32_SRC_TIMPCLK1 TIM15_SEL(0)>;
- resets = <&rctl STM32_RESET(APB1H, 16U)>;
+ resets = <&rctl STM32_RESET(APB1H, 16)>;
interrupts = <20 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/g0/stm32g070.dtsi b/dts/arm/st/g0/stm32g070.dtsi
index 338b08b..2120169 100644
--- a/dts/arm/st/g0/stm32g070.dtsi
+++ b/dts/arm/st/g0/stm32g070.dtsi
@@ -15,7 +15,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
- resets = <&rctl STM32_RESET(APB1L, 18U)>;
+ resets = <&rctl STM32_RESET(APB1L, 18)>;
interrupts = <29 0>;
status = "disabled";
};
@@ -24,7 +24,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
- resets = <&rctl STM32_RESET(APB1L, 19U)>;
+ resets = <&rctl STM32_RESET(APB1L, 19)>;
interrupts = <29 0>;
status = "disabled";
};
@@ -34,7 +34,7 @@
reg = <0x40014000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1_2, 16)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1H, 16U)>;
+ resets = <&rctl STM32_RESET(APB1H, 16)>;
interrupts = <20 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/g0/stm32g071.dtsi b/dts/arm/st/g0/stm32g071.dtsi
index 20243db..7da03bf 100644
--- a/dts/arm/st/g0/stm32g071.dtsi
+++ b/dts/arm/st/g0/stm32g071.dtsi
@@ -16,7 +16,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
- resets = <&rctl STM32_RESET(APB1L, 18U)>;
+ resets = <&rctl STM32_RESET(APB1L, 18)>;
interrupts = <29 0>;
status = "disabled";
};
@@ -25,7 +25,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
- resets = <&rctl STM32_RESET(APB1L, 19U)>;
+ resets = <&rctl STM32_RESET(APB1L, 19)>;
interrupts = <29 0>;
status = "disabled";
};
diff --git a/dts/arm/st/g0/stm32g0_crypt.dtsi b/dts/arm/st/g0/stm32g0_crypt.dtsi
index 609425d..93f8f07 100644
--- a/dts/arm/st/g0/stm32g0_crypt.dtsi
+++ b/dts/arm/st/g0/stm32g0_crypt.dtsi
@@ -14,7 +14,7 @@
compatible = "st,stm32-aes";
reg = <0x40026000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB1, 16)>;
- resets = <&rctl STM32_RESET(AHB1, 16U)>;
+ resets = <&rctl STM32_RESET(AHB1, 16)>;
interrupts = <31 0>;
status = "disabled";
};
diff --git a/dts/arm/st/g0/stm32g0b0.dtsi b/dts/arm/st/g0/stm32g0b0.dtsi
index 12a4797..0bd63fc 100644
--- a/dts/arm/st/g0/stm32g0b0.dtsi
+++ b/dts/arm/st/g0/stm32g0b0.dtsi
@@ -25,7 +25,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 8)>;
- resets = <&rctl STM32_RESET(APB1L, 8U)>;
+ resets = <&rctl STM32_RESET(APB1L, 8)>;
interrupts = <29 0>;
status = "disabled";
};
@@ -34,7 +34,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 9)>;
- resets = <&rctl STM32_RESET(APB1L, 9U)>;
+ resets = <&rctl STM32_RESET(APB1L, 9)>;
interrupts = <29 0>;
status = "disabled";
};
@@ -44,7 +44,7 @@
reg = <0x40000800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 2)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 2U)>;
+ resets = <&rctl STM32_RESET(APB1L, 2)>;
interrupts = <16 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/g0/stm32g0b1.dtsi b/dts/arm/st/g0/stm32g0b1.dtsi
index 1c78a1c..010648a 100644
--- a/dts/arm/st/g0/stm32g0b1.dtsi
+++ b/dts/arm/st/g0/stm32g0b1.dtsi
@@ -58,7 +58,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 8)>;
- resets = <&rctl STM32_RESET(APB1L, 8U)>;
+ resets = <&rctl STM32_RESET(APB1L, 8)>;
interrupts = <29 0>;
status = "disabled";
};
@@ -67,7 +67,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 9)>;
- resets = <&rctl STM32_RESET(APB1L, 9U)>;
+ resets = <&rctl STM32_RESET(APB1L, 9)>;
interrupts = <29 0>;
status = "disabled";
};
@@ -76,7 +76,7 @@
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x40008400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 7)>;
- resets = <&rctl STM32_RESET(APB1L, 7U)>;
+ resets = <&rctl STM32_RESET(APB1L, 7)>;
interrupts = <28 0>;
status = "disabled";
};
@@ -86,7 +86,7 @@
reg = <0x40000800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 2)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 2U)>;
+ resets = <&rctl STM32_RESET(APB1L, 2)>;
interrupts = <16 0>;
interrupt-names = "global";
st,prescaler = <0>;
