fcbfe74df1a52a92c9f10d8aedb0f9199d92dbbf - third_party/github/zephyrproject-rtos/zephyr

commit	fcbfe74df1a52a92c9f10d8aedb0f9199d92dbbf	[log] [tgz]
author	Gerard Marull-Paretas <gerard@teslabs.com>	Wed Jan 10 15:38:15 2024 +0100
committer	Carles Cufí <carles.cufi@nordicsemi.no>	Mon Jan 15 09:58:03 2024 +0100
tree	c3396b92eb9957f43613ba73ae114420ad7dd5e0
parent	f1ef55ec5aa096236c78db1d6515cf06b16a4973 [diff]

arch: riscv: define some RISC-V exception codes

As defined in Table 3.6 of "The RISC-V Instruction Set Manual, Volume
II: Privileged Architecture". Delete all spread definitions of the same,
weirdly prefixed with "SOC".

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>

arch/riscv/core/isr.S[diff]
include/zephyr/arch/riscv/irq.h[diff]
soc/riscv/common/riscv-privileged/soc_common.h[diff]
soc/riscv/espressif_esp32/esp32c3/soc.h[diff]
soc/riscv/ite_ec/common/soc_common.h[diff]
soc/riscv/openisa_rv32m1/soc_ri5cy.h[diff]
soc/riscv/openisa_rv32m1/soc_zero_riscy.h[diff]

7 files changed