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pigweed/third_party/github/zephyrproject-rtos/zephyr/fd42bf7443cb2f36619be0eab7aa378c30f49da7^!/.
commit
fd42bf7443cb2f36619be0eab7aa378c30f49da7
[log]
author
Patrik Flykt <patrik.flykt@intel.com>
Thu Mar 14 16:04:29 2019 -0600
committer
Anas Nashif <anas.nashif@intel.com>
Wed Apr 03 17:31:00 2019 -0400
tree
a8e4ecc794574a3606daab8a60b7b53e012625b1
parent
5aecf9db37f5c67551fbbc6621e1f0a25698c4d2 [diff]
soc: Rename reserved function names

Rename reserved function names in the soc/ subdirectory.

Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>

diff --git a/arch/arm/include/cortex_m/exc.h b/arch/arm/include/cortex_m/exc.h
index df89eb0..4306b35 100644
--- a/arch/arm/include/cortex_m/exc.h
+++ b/arch/arm/include/cortex_m/exc.h

@@ -144,7 +144,7 @@
  *
  * @return N/A
  */
-static ALWAYS_INLINE void _ClearFaults(void)
+static ALWAYS_INLINE void z_clearfaults(void)
 {
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)

diff --git a/drivers/pinmux/pinmux_esp32.c b/drivers/pinmux/pinmux_esp32.c
index a796e59..8f0819f 100644
--- a/drivers/pinmux/pinmux_esp32.c
+++ b/drivers/pinmux/pinmux_esp32.c

@@ -112,7 +112,7 @@
 	return -EINVAL;
 }
 
-#define CFG(id)   ((GPIO_ ## id ## _REG) & 0xff)
+#define CFG(id)   ((GPIO_ ## id ## Z_REG) & 0xff)
 static int pinmux_input(struct device *dev, u32_t pin, u8_t func)
 {
 	static const u8_t offs[2][3] = {

diff --git a/soc/arc/quark_se_c1000_ss/power.c b/soc/arc/quark_se_c1000_ss/power.c
index 0663b5e..bd314c2 100644
--- a/soc/arc/quark_se_c1000_ss/power.c
+++ b/soc/arc/quark_se_c1000_ss/power.c

@@ -18,20 +18,20 @@
 #include "vreg.h"
 
 #if (defined(CONFIG_SYS_POWER_DEEP_SLEEP_STATES))
-extern void _power_soc_sleep(void);
-extern void _power_soc_deep_sleep(void);
-extern void _power_soc_lpss_mode(void);
+extern void z_power_soc_sleep(void);
+extern void z_power_soc_deep_sleep(void);
+extern void z_power_soc_lpss_mode(void);
 
-static void _deep_sleep(enum power_states state)
+static void deep_sleep(enum power_states state)
 {
 	qm_power_soc_set_ss_restore_flag();
 
 	switch (state) {
 	case SYS_POWER_STATE_DEEP_SLEEP_2:
-		_power_soc_sleep();
+		z_power_soc_sleep();
 		break;
 	case SYS_POWER_STATE_DEEP_SLEEP_3:
-		_power_soc_deep_sleep();
+		z_power_soc_deep_sleep();
 		break;
 	default:
 		break;
@@ -54,11 +54,11 @@
 	case SYS_POWER_STATE_DEEP_SLEEP_1:
 		qm_ss_power_soc_lpss_enable();
 		qm_power_soc_set_ss_restore_flag();
-		_power_soc_lpss_mode();
+		z_power_soc_lpss_mode();
 		break;
 	case SYS_POWER_STATE_DEEP_SLEEP_2:
 	case SYS_POWER_STATE_DEEP_SLEEP_3:
-		_deep_sleep(state);
+		deep_sleep(state);
 		break;
 #endif
 	default:
@@ -90,7 +90,7 @@
 		 * its execution.
 		 */
 		if ((QM_SCSS_GP->gp0 & GP0_BIT_SLEEP_READY) == 0) {
-			_quark_se_ss_ready();
+			z_quark_se_ss_ready();
 			__builtin_arc_seti(0);
 		} else {
 			QM_SCSS_GP->gp0 &= ~GP0_BIT_SLEEP_READY;

diff --git a/soc/arc/quark_se_c1000_ss/soc.c b/soc/arc/quark_se_c1000_ss/soc.c
index 68a3df3..38c88fd 100644
--- a/soc/arc/quark_se_c1000_ss/soc.c
+++ b/soc/arc/quark_se_c1000_ss/soc.c

@@ -24,7 +24,7 @@
 {
 	ARG_UNUSED(arg);
 
-	_quark_se_ss_ready();
+	quark_se_ss_ready();
 
 	return 0;
 }

diff --git a/soc/arc/quark_se_c1000_ss/soc.h b/soc/arc/quark_se_c1000_ss/soc.h
index ca57697..e920271 100644
--- a/soc/arc/quark_se_c1000_ss/soc.h
+++ b/soc/arc/quark_se_c1000_ss/soc.h

@@ -201,7 +201,7 @@
 #define DT_RTC_0_IRQ_FLAGS			(IOAPIC_EDGE | IOAPIC_HIGH)
 
 
-static inline void _quark_se_ss_ready(void)
+static inline void quark_se_ss_ready(void)
 {
 	shared_data->flags |= ARC_READY;
 }

diff --git a/soc/arc/quark_se_c1000_ss/soc_power.S b/soc/arc/quark_se_c1000_ss/soc_power.S
index b333599..4be6787 100644
--- a/soc/arc/quark_se_c1000_ss/soc_power.S
+++ b/soc/arc/quark_se_c1000_ss/soc_power.S

@@ -11,11 +11,11 @@
 #ifdef CONFIG_SYS_POWER_DEEP_SLEEP_STATES
 GDATA(_pm_arc_context)
 
-GTEXT(_sys_resume_from_deep_sleep)
-GTEXT(_power_restore_cpu_context)
-GTEXT(_power_soc_sleep)
-GTEXT(_power_soc_deep_sleep)
-GTEXT(_power_soc_lpss_mode)
+GTEXT(sys_resume_from_deep_sleep)
+GTEXT(z_power_restore_cpu_context)
+GTEXT(z_power_soc_sleep)
+GTEXT(z_power_soc_deep_sleep)
+GTEXT(z_power_soc_lpss_mode)
 
 #define GPS0_REGISTER  0xb0800100
 #define GP0_REGISTER 0xb0800114
@@ -47,7 +47,7 @@
 
 	j_s [blink] /* Jump to context of BLINK register. */
 
-SECTION_FUNC(TEXT, _power_soc_sleep)
+SECTION_FUNC(TEXT, z_power_soc_sleep)
 	/*
 	 * Save the return address.
 	 * The restore function will pop this and jump
@@ -60,7 +60,7 @@
 	j @qm_power_soc_sleep
 	/* Does not return */
 
-SECTION_FUNC(TEXT, _power_soc_deep_sleep)
+SECTION_FUNC(TEXT, z_power_soc_deep_sleep)
 	/*
 	 * Save the return address.
 	 * The restore function will pop this and jump
@@ -73,7 +73,7 @@
 	j @qm_power_soc_deep_sleep
 	/* Does not return */
 
-SECTION_FUNC(TEXT, _power_soc_lpss_mode)
+SECTION_FUNC(TEXT, z_power_soc_lpss_mode)
 	/*
 	 * Setup 'sleep' instruction operand.
 	 */

diff --git a/soc/arm/atmel_sam/sam3x/soc.c b/soc/arm/atmel_sam/sam3x/soc.c
index a36db7f..9bcaad2 100644
--- a/soc/arm/atmel_sam/sam3x/soc.c
+++ b/soc/arm/atmel_sam/sam3x/soc.c

@@ -209,7 +209,7 @@
 
 	key = irq_lock();
 
-	_ClearFaults();
+	z_clearfaults();
 
 	/*
 	 * Set FWS (Flash Wait State) value before increasing Master Clock

diff --git a/soc/arm/atmel_sam/sam4s/soc.c b/soc/arm/atmel_sam/sam4s/soc.c
index 880101e..6bc8d72 100644
--- a/soc/arm/atmel_sam/sam4s/soc.c
+++ b/soc/arm/atmel_sam/sam4s/soc.c

@@ -197,7 +197,7 @@
 	key = irq_lock();
 
 	/* Clear all faults. */
-	_ClearFaults();
+	z_clearfaults();
 
 	/*
 	 * Set FWS (Flash Wait State) value before increasing Master Clock

diff --git a/soc/arm/atmel_sam/same70/soc.c b/soc/arm/atmel_sam/same70/soc.c
index 6c8d0da..d4dd0c3 100644
--- a/soc/arm/atmel_sam/same70/soc.c
+++ b/soc/arm/atmel_sam/same70/soc.c

@@ -234,7 +234,7 @@
 	}
 
 	/* Clear all faults */
-	_ClearFaults();
+	z_clearfaults();
 
 	/*
 	 * Set FWS (Flash Wait State) value before increasing Master Clock

diff --git a/soc/arm/atmel_sam0/samd20/soc.c b/soc/arm/atmel_sam0/samd20/soc.c
index 6441750..ee77f0f 100644
--- a/soc/arm/atmel_sam0/samd20/soc.c
+++ b/soc/arm/atmel_sam0/samd20/soc.c

@@ -172,7 +172,7 @@
 
 	key = irq_lock();
 
-	_ClearFaults();
+	z_clearfaults();
 
 	flash_waitstates_init();
 	osc8m_init();

diff --git a/soc/arm/atmel_sam0/samd21/soc.c b/soc/arm/atmel_sam0/samd21/soc.c
index edfec76..f56218b 100644
--- a/soc/arm/atmel_sam0/samd21/soc.c
+++ b/soc/arm/atmel_sam0/samd21/soc.c

@@ -173,7 +173,7 @@
 
 	key = irq_lock();
 
-	_ClearFaults();
+	z_clearfaults();
 
 	flash_waitstates_init();
 	osc8m_init();

diff --git a/soc/arm/nordic_nrf/nrf52/soc.c b/soc/arm/nordic_nrf/nrf52/soc.c
index 1209405..44e9edb 100644
--- a/soc/arm/nordic_nrf/nrf52/soc.c
+++ b/soc/arm/nordic_nrf/nrf52/soc.c

@@ -69,7 +69,7 @@
 	nrf_power_dcdcen_set(true);
 #endif
 
-	_ClearFaults();
+	z_clearfaults();
 
 	/* Install default handler that simply resets the CPU
 	* if configured in the kernel, NOP otherwise

diff --git a/soc/arm/nordic_nrf/nrf91/soc.c b/soc/arm/nordic_nrf/nrf91/soc.c
index 62a201b..72a53db 100644
--- a/soc/arm/nordic_nrf/nrf91/soc.c
+++ b/soc/arm/nordic_nrf/nrf91/soc.c

@@ -50,7 +50,7 @@
 	NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
 #endif
 
-	_ClearFaults();
+	z_clearfaults();
 
 	/* Install default handler that simply resets the CPU
 	* if configured in the kernel, NOP otherwise

diff --git a/soc/arm/nxp_imx/mcimx6x_m4/soc.c b/soc/arm/nxp_imx/mcimx6x_m4/soc.c
index d20a3d0..f22e169 100644
--- a/soc/arm/nxp_imx/mcimx6x_m4/soc.c
+++ b/soc/arm/nxp_imx/mcimx6x_m4/soc.c

@@ -187,7 +187,7 @@
 	/* Initialize Cache */
 	SOC_CacheInit();
 
-	_ClearFaults();
+	z_clearfaults();
 
 	/* Initialize clock */
 	SOC_ClockInit();

diff --git a/soc/arm/nxp_imx/rt/soc.c b/soc/arm/nxp_imx/rt/soc.c
index bda9b54..126a07f 100644
--- a/soc/arm/nxp_imx/rt/soc.c
+++ b/soc/arm/nxp_imx/rt/soc.c

@@ -210,7 +210,7 @@
 		SCB_EnableDCache();
 	}
 
-	_ClearFaults();
+	z_clearfaults();
 
 	/* Initialize system clock */
 	clkInit();

diff --git a/soc/arm/nxp_kinetis/k6x/soc.c b/soc/arm/nxp_kinetis/k6x/soc.c
index cd03b97..179ec66 100644
--- a/soc/arm/nxp_kinetis/k6x/soc.c
+++ b/soc/arm/nxp_kinetis/k6x/soc.c

@@ -180,7 +180,7 @@
 	SYSMPU->CESR = temp_reg;
 #endif /* !CONFIG_ARM_MPU */
 
-	_ClearFaults();
+	z_clearfaults();
 
 	/* Initialize PLL/system clock to 120 MHz */
 	clkInit();

diff --git a/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c b/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c
index 9c7550a..9c7962e 100644
--- a/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c
+++ b/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c

@@ -189,7 +189,7 @@
 	/* release I/O power hold to allow normal run state */
 	PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
 
-	_ClearFaults();
+	z_clearfaults();
 
 	/* Initialize PLL/system clock to 48 MHz */
 	clkInit();

diff --git a/soc/arm/nxp_lpc/lpc54xxx/soc.c b/soc/arm/nxp_lpc/lpc54xxx/soc.c
index 9fe3462..ee526d8 100644
--- a/soc/arm/nxp_lpc/lpc54xxx/soc.c
+++ b/soc/arm/nxp_lpc/lpc54xxx/soc.c

@@ -87,7 +87,7 @@
 	/* disable interrupts */
 	oldLevel = irq_lock();
 
-	_ClearFaults();
+	z_clearfaults();
 
 	/* Initialize FRO/system clock to 48 MHz */
 	clkInit();

diff --git a/soc/arm/silabs_exx32/common/soc.c b/soc/arm/silabs_exx32/common/soc.c
index d6b67f8..24d8334 100644
--- a/soc/arm/silabs_exx32/common/soc.c
+++ b/soc/arm/silabs_exx32/common/soc.c

@@ -119,7 +119,7 @@
 	/* handle chip errata */
 	CHIP_Init();
 
-	_ClearFaults();
+	z_clearfaults();
 
 #ifdef CONFIG_SOC_GECKO_EMU_DCDC
 	dcdc_init();

diff --git a/soc/arm/st_stm32/stm32f0/soc.c b/soc/arm/st_stm32/stm32f0/soc.c
index c9d10f6..b652909 100644
--- a/soc/arm/st_stm32/stm32f0/soc.c
+++ b/soc/arm/st_stm32/stm32f0/soc.c

@@ -62,7 +62,7 @@
 
 	key = irq_lock();
 
-	_ClearFaults();
+	z_clearfaults();
 
 	/* Install default handler that simply resets the CPU
 	 * if configured in the kernel, NOP otherwise

diff --git a/soc/arm/st_stm32/stm32f1/soc.c b/soc/arm/st_stm32/stm32f1/soc.c
index 74bed86..714eb3b 100644
--- a/soc/arm/st_stm32/stm32f1/soc.c
+++ b/soc/arm/st_stm32/stm32f1/soc.c

@@ -30,7 +30,7 @@
 
 	key = irq_lock();
 
-	_ClearFaults();
+	z_clearfaults();
 
 	/* Install default handler that simply resets the CPU
 	 * if configured in the kernel, NOP otherwise

diff --git a/soc/arm/st_stm32/stm32f2/soc.c b/soc/arm/st_stm32/stm32f2/soc.c
index b027196..78fbc78 100644
--- a/soc/arm/st_stm32/stm32f2/soc.c
+++ b/soc/arm/st_stm32/stm32f2/soc.c

@@ -34,7 +34,7 @@
 
 	key = irq_lock();
 
-	_ClearFaults();
+	z_clearfaults();
 
 	/* Install default handler that simply resets the CPU
 	 * if configured in the kernel, NOP otherwise

diff --git a/soc/arm/st_stm32/stm32f3/soc.c b/soc/arm/st_stm32/stm32f3/soc.c
index 9b68c05..042d31c 100644
--- a/soc/arm/st_stm32/stm32f3/soc.c
+++ b/soc/arm/st_stm32/stm32f3/soc.c

@@ -30,7 +30,7 @@
 
 	key = irq_lock();
 
-	_ClearFaults();
+	z_clearfaults();
 
 	/* Install default handler that simply resets the CPU
 	 * if configured in the kernel, NOP otherwise

diff --git a/soc/arm/st_stm32/stm32f4/soc.c b/soc/arm/st_stm32/stm32f4/soc.c
index cd24d70..952efbd 100644
--- a/soc/arm/st_stm32/stm32f4/soc.c
+++ b/soc/arm/st_stm32/stm32f4/soc.c

@@ -31,7 +31,7 @@
 
 	key = irq_lock();
 
-	_ClearFaults();
+	z_clearfaults();
 
 	/* Install default handler that simply resets the CPU
 	 * if configured in the kernel, NOP otherwise

diff --git a/soc/arm/st_stm32/stm32f7/soc.c b/soc/arm/st_stm32/stm32f7/soc.c
index 87261df..2e6a711 100644
--- a/soc/arm/st_stm32/stm32f7/soc.c
+++ b/soc/arm/st_stm32/stm32f7/soc.c

@@ -37,7 +37,7 @@
 		SCB_EnableDCache();
 	}
 
-	_ClearFaults();
+	z_clearfaults();
 
 	/* Install default handler that simply resets the CPU
 	 * if configured in the kernel, NOP otherwise

diff --git a/soc/arm/st_stm32/stm32l0/soc.c b/soc/arm/st_stm32/stm32l0/soc.c
index 3254c18..2cce2a7 100644
--- a/soc/arm/st_stm32/stm32l0/soc.c
+++ b/soc/arm/st_stm32/stm32l0/soc.c

@@ -32,7 +32,7 @@
 
 	key = irq_lock();
 
-	_ClearFaults();
+	z_clearfaults();
 
 	/* Install default handler that simply resets the CPU
 	 * if configured in the kernel, NOP otherwise

diff --git a/soc/arm/st_stm32/stm32l4/soc.c b/soc/arm/st_stm32/stm32l4/soc.c
index 96abca3..01ffd28 100644
--- a/soc/arm/st_stm32/stm32l4/soc.c
+++ b/soc/arm/st_stm32/stm32l4/soc.c

@@ -31,7 +31,7 @@
 
 	key = irq_lock();
 
-	_ClearFaults();
+	z_clearfaults();
 
 	/* Install default handler that simply resets the CPU
 	 * if configured in the kernel, NOP otherwise

diff --git a/soc/arm/ti_lm3s6965/reboot.S b/soc/arm/ti_lm3s6965/reboot.S
index f0defaf..6c74cd6 100644
--- a/soc/arm/ti_lm3s6965/reboot.S
+++ b/soc/arm/ti_lm3s6965/reboot.S

@@ -13,8 +13,8 @@
 
 GDATA(_interrupt_stack)
 
-GTEXT(_do_software_reboot)
-SECTION_FUNC(TEXT,_do_software_reboot)
+GTEXT(z_do_software_reboot)
+SECTION_FUNC(TEXT,z_do_software_reboot)
 
 	eors r0, r0
 
@@ -26,8 +26,8 @@
 	bx r0
 
 
-GTEXT(_force_exit_one_nested_irq)
-SECTION_FUNC(TEXT,_force_exit_one_nested_irq)
+GTEXT(z_force_exit_one_nested_irq)
+SECTION_FUNC(TEXT,z_force_exit_one_nested_irq)
 
 	ldr r0, =_SCS_ICSR_RETTOBASE
 	ldr r1, =_SCS_ICSR
@@ -41,9 +41,9 @@
 	*/
 	ittee eq
 		ldreq lr, =0xfffffff1
-		ldreq r2, =_force_exit_one_nested_irq
+		ldreq r2, =z_force_exit_one_nested_irq
 		ldrne lr, =0xfffffffd
-		ldrne r2, =_do_software_reboot
+		ldrne r2, =z_do_software_reboot
 
 	ldr ip, =_interrupt_stack
 	add.w ip, ip, #(___esf_t_SIZEOF * 2) /* enough for a stack frame */

diff --git a/soc/arm/ti_lm3s6965/sys_arch_reboot.c b/soc/arm/ti_lm3s6965/sys_arch_reboot.c
index f0a7692..9140eac 100644
--- a/soc/arm/ti_lm3s6965/sys_arch_reboot.c
+++ b/soc/arm/ti_lm3s6965/sys_arch_reboot.c

@@ -28,8 +28,8 @@
      * which address can _always_ be found in the vector table reset slot
      * located at address 0x4.
      */
-	extern void _do_software_reboot(void);
-	extern void _force_exit_one_nested_irq(void);
+	extern void z_do_software_reboot(void);
+	extern void z_force_exit_one_nested_irq(void);
 	/*
 	 * force enable interrupts locked via PRIMASK if somehow disabled: the
 	 * boot code does not enable them
@@ -37,10 +37,10 @@
 	__asm__ volatile("cpsie i" :::);
 
 	if ((SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) == 0) {
-		_do_software_reboot();
+		z_do_software_reboot();
 	} else {
 		__asm__ volatile(
-			"ldr r0,  =_force_exit_one_nested_irq\n\t"
+			"ldr r0,  =z_force_exit_one_nested_irq\n\t"
 			"bx r0\n\t"
 			:::);
 	}

diff --git a/soc/x86/intel_quark/quark_se/power.c b/soc/x86/intel_quark/quark_se/power.c
index f420f4b..51adfb5 100644
--- a/soc/x86/intel_quark/quark_se/power.c
+++ b/soc/x86/intel_quark/quark_se/power.c

@@ -21,15 +21,15 @@
 u64_t _pm_save_idtr;
 u32_t _pm_save_esp;
 
-extern void _power_soc_sleep(void);
-extern void _power_restore_cpu_context(void);
-extern void _power_soc_deep_sleep(void);
+extern void z_power_soc_sleep(void);
+extern void z_power_restore_cpu_context(void);
+extern void z_power_soc_deep_sleep(void);
 
 #if (defined(CONFIG_SYS_POWER_DEEP_SLEEP_STATES))
 static u32_t  *__x86_restore_info =
 	(u32_t *)CONFIG_BSP_SHARED_RESTORE_INFO_RAM_ADDR;
 
-static void _deep_sleep(enum power_states state)
+static void deep_sleep(enum power_states state)
 {
 	/*
 	 * Setting resume vector inside the restore_cpu_context
@@ -39,17 +39,17 @@
 	 * can be done before cpu context is restored and control
 	 * transferred to _sys_suspend.
 	 */
-	qm_x86_set_resume_vector(_power_restore_cpu_context,
+	qm_x86_set_resume_vector(z_power_restore_cpu_context,
 				 *__x86_restore_info);
 
 	qm_power_soc_set_x86_restore_flag();
 
 	switch (state) {
 	case SYS_POWER_STATE_DEEP_SLEEP_1:
-		_power_soc_sleep();
+		z_power_soc_sleep();
 		break;
 	case SYS_POWER_STATE_DEEP_SLEEP_2:
-		_power_soc_deep_sleep();
+		z_power_soc_deep_sleep();
 		break;
 	default:
 		break;
@@ -74,7 +74,7 @@
 #if (defined(CONFIG_SYS_POWER_DEEP_SLEEP_STATES))
 	case SYS_POWER_STATE_DEEP_SLEEP_1:
 	case SYS_POWER_STATE_DEEP_SLEEP_2:
-		_deep_sleep(state);
+		deep_sleep(state);
 		break;
 #endif
 	default:
@@ -96,7 +96,7 @@
 #if (defined(CONFIG_SYS_POWER_DEEP_SLEEP_STATES))
 	case SYS_POWER_STATE_DEEP_SLEEP_2:
 #ifdef CONFIG_ARC_INIT
-		_arc_init(NULL);
+		z_arc_init(NULL);
 #endif /* CONFIG_ARC_INIT */
 		/* Fallthrough */
 	case SYS_POWER_STATE_DEEP_SLEEP_1:

diff --git a/soc/x86/intel_quark/quark_se/soc.c b/soc/x86/intel_quark/quark_se/soc.c
index 334b339..ca23625 100644
--- a/soc/x86/intel_quark/quark_se/soc.c
+++ b/soc/x86/intel_quark/quark_se/soc.c

@@ -62,7 +62,7 @@
  * @return N/A
  */
 /* This function is also called at deep sleep resume. */
-int _arc_init(struct device *arg)
+int z_arc_init(struct device *arg)
 {
 	u32_t *reset_vector;
 
@@ -108,7 +108,7 @@
 	return 0;
 }
 
-SYS_INIT(_arc_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+SYS_INIT(z_arc_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
 
 #endif /*CONFIG_ARC_INIT*/
 

diff --git a/soc/x86/intel_quark/quark_se/soc.h b/soc/x86/intel_quark/quark_se/soc.h
index adf2c02..7150076 100644
--- a/soc/x86/intel_quark/quark_se/soc.h
+++ b/soc/x86/intel_quark/quark_se/soc.h

@@ -84,7 +84,7 @@
 #endif /*  _ASMLANGUAGE */
 
 #ifdef CONFIG_ARC_INIT
-int _arc_init(struct device *arg);
+int z_arc_init(struct device *arg);
 #endif /* CONFIG_ARC_INIT */
 
 #endif /* __SOC_H_ */

diff --git a/soc/x86/intel_quark/quark_se/soc_power.S b/soc/x86/intel_quark/quark_se/soc_power.S
index 9fda1c5..2fabdcc 100644
--- a/soc/x86/intel_quark/quark_se/soc_power.S
+++ b/soc/x86/intel_quark/quark_se/soc_power.S

@@ -11,10 +11,10 @@
 GDATA(_pm_save_idtr)
 GDATA(_pm_save_esp)
 
-GTEXT(_sys_resume_from_deep_sleep)
-GTEXT(_power_restore_cpu_context)
-GTEXT(_power_soc_sleep)
-GTEXT(_power_soc_deep_sleep)
+GTEXT(sys_resume_from_deep_sleep)
+GTEXT(z_power_restore_cpu_context)
+GTEXT(z_power_soc_sleep)
+GTEXT(z_power_soc_deep_sleep)
 
 SECTION_FUNC(TEXT, save_cpu_context)
 	movl %esp, %eax                 /* save ptr to return address */
@@ -43,7 +43,7 @@
 	pushl (%eax)                    /* push return address */
 	ret
 
-SECTION_FUNC(TEXT, _power_restore_cpu_context)
+SECTION_FUNC(TEXT, z_power_restore_cpu_context)
 	lgdtl _pm_save_gdtr		/* restore gdtr */
 	lidtl _pm_save_idtr		/* restore idtr */
 	movl _pm_save_esp, %esp		/* restore saved stack ptr */
@@ -70,23 +70,23 @@
 	 *
 	 *          Saved context
 	 * ESP ---> Return address of save_cpu_context
-	 *          Return address of _power_soc_sleep/deep_sleep
+	 *          Return address of z_power_soc_sleep/deep_sleep
 	 *
 	 * We just popped the saved context. Next we pop out the address
 	 * of the caller of save_cpu_context.Then the ret would return
-	 * to caller of _power_soc_sleep or _power_soc_deep_sleep.
+	 * to caller of z_power_soc_sleep or z_power_soc_deep_sleep.
 	 *
 	 */
 	addl $4, %esp
 	ret
 
-SECTION_FUNC(TEXT, _power_soc_sleep)
+SECTION_FUNC(TEXT, z_power_soc_sleep)
 	call save_cpu_context
 	wbinvd
 	call qm_power_soc_sleep
 	/* Does not return */
 
-SECTION_FUNC(TEXT, _power_soc_deep_sleep)
+SECTION_FUNC(TEXT, z_power_soc_deep_sleep)
 	call save_cpu_context
 	wbinvd
 	call qm_power_soc_deep_sleep
@@ -104,8 +104,8 @@
  */
 SECTION_FUNC(TEXT, _sys_resume_from_deep_sleep)
 	movl $CONFIG_BSP_SHARED_RESTORE_INFO_RAM_ADDR, %eax
-	cmpl $_power_restore_cpu_context, (%eax)
-	je _power_restore_cpu_context
+	cmpl $z_power_restore_cpu_context, (%eax)
+	je z_power_restore_cpu_context
 	ret
 
 #endif

diff --git a/soc/xtensa/esp32/esp32-mp.c b/soc/xtensa/esp32/esp32-mp.c
index 55029b7..d700753 100644
--- a/soc/xtensa/esp32/esp32-mp.c
+++ b/soc/xtensa/esp32/esp32-mp.c

@@ -11,16 +11,16 @@
 #include <spinlock.h>
 #include <kernel_structs.h>
 
-#define _REG(base, off) (*(volatile u32_t *)((base) + (off)))
+#define Z_REG(base, off) (*(volatile u32_t *)((base) + (off)))
 
 #define RTC_CNTL_BASE             0x3ff48000
-#define RTC_CNTL_OPTIONS0     _REG(RTC_CNTL_BASE, 0x0)
-#define RTC_CNTL_SW_CPU_STALL _REG(RTC_CNTL_BASE, 0xac)
+#define RTC_CNTL_OPTIONS0     Z_REG(RTC_CNTL_BASE, 0x0)
+#define RTC_CNTL_SW_CPU_STALL Z_REG(RTC_CNTL_BASE, 0xac)
 
 #define DPORT_BASE                 0x3ff00000
-#define DPORT_APPCPU_CTRL_A    _REG(DPORT_BASE, 0x02C)
-#define DPORT_APPCPU_CTRL_B    _REG(DPORT_BASE, 0x030)
-#define DPORT_APPCPU_CTRL_C    _REG(DPORT_BASE, 0x034)
+#define DPORT_APPCPU_CTRL_A    Z_REG(DPORT_BASE, 0x02C)
+#define DPORT_APPCPU_CTRL_B    Z_REG(DPORT_BASE, 0x030)
+#define DPORT_APPCPU_CTRL_C    Z_REG(DPORT_BASE, 0x034)
 
 struct cpustart_rec {
 	int cpu;
@@ -103,10 +103,10 @@
  * set to zero for the called function (a null return value is the
  * signal for "top of stack" to the debugger).
  */
-void _appcpu_stack_switch(void *stack, void *entry);
+void z_appcpu_stack_switch(void *stack, void *entry);
 __asm__("\n"
 	".align 4"		"\n"
-	"_appcpu_stack_switch:"	"\n\t"
+	"z_appcpu_stack_switch:"	"\n\t"
 
 	"entry a1, 16"		"\n\t"
 
@@ -153,7 +153,7 @@
  */
 static void appcpu_entry1(void)
 {
-	_appcpu_stack_switch(appcpu_top, appcpu_entry2);
+	z_appcpu_stack_switch(appcpu_top, appcpu_entry2);
 }
 
 /* The calls and sequencing here were extracted from the ESP-32