commit a1048d4f96e15f4166269bd1c2c05b8402c2c5f3
author Pieter De Gendt <pieter.degendt@basalte.be> Thu Sep 11 08:43:03 2025 +0200
committer Pieter De Gendt <pieter.degendt@basalte.be> Mon Sep 15 10:59:48 2025 +0200
tree be31ca1f36f5c61058b21e7374fa0ab39c89034d
parent c8cac78c6ce975142ab11ed949b17b711e107681

arch: common: nocache.ld: One nocache MPU region

Combine the load and noload cache regions for a single MPU aligned block.
This is required to have an MPU region with a size that is a power of 2.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
(cherry picked from commit 8f7908694a1879bebcdf269665574a029d2beeb1)

arch/common/nocache.ld

diff --git a/arch/common/nocache.ld b/arch/common/nocache.ld
index b51192f..2f26748 100644
--- a/arch/common/nocache.ld
+++ b/arch/common/nocache.ld
@@ -14,7 +14,7 @@
 #if defined(CONFIG_MMU)
 	MMU_ALIGN;
 #else
-	MPU_ALIGN(_nocache_noload_ram_size);
+	MPU_ALIGN(_nocache_ram_size);
 #endif
 	_nocache_ram_start = .;
 	_nocache_noload_ram_start = .;
@@ -23,11 +23,6 @@
 
 #include <snippets-nocache-section.ld>
 
-#if defined(CONFIG_MMU)
-	MMU_ALIGN;
-#else
-	MPU_ALIGN(_nocache_noload_ram_size);
-#endif
 	_nocache_noload_ram_end = .;
 } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
 _nocache_noload_ram_size = _nocache_noload_ram_end - _nocache_noload_ram_start;
@@ -35,11 +30,6 @@
 /* Non-cached loadable region of RAM and ROM */
 SECTION_DATA_PROLOGUE(_NOCACHE_LOAD_SECTION_NAME,,)
 {
-#if defined(CONFIG_MMU)
-	MMU_ALIGN;
-#else
-	MPU_ALIGN(_nocache_load_ram_size);
-#endif
 	_nocache_load_ram_start = .;
 	*(.nocache_load)
 	*(".nocache_load.*")
@@ -47,7 +37,7 @@
 #if defined(CONFIG_MMU)
 	MMU_ALIGN;
 #else
-	MPU_ALIGN(_nocache_load_ram_size);
+	MPU_ALIGN(_nocache_ram_size);
 #endif
 	_nocache_load_ram_end = .;
 	_nocache_ram_end = .;