pw_cpu_exception_cortex_m: Move armv7m->cortex_m
Moves the armv7m implementation of pw_cpu_exception to
pw_cpu_exception_cortex_m since much of the logic can be shared between
ARMv8-M and ARMv7-M. Symbol names are also updated to reflect current
naming style for extern "C" symbols. Old names will be removed in
pwrev/31060.
Warning, symbol renames are breaking!
pw_CpuExceptionEntry -> pw_cpu_exception_Entry
pw_CpuExceptionDefaultHandler -> pw_cpu_exception_DefaultHandler
Change-Id: I7ab99ac7637c436ba959d7546043090c66fe4215
Reviewed-on: https://pigweed-review.googlesource.com/c/pigweed/pigweed/+/30922
Commit-Queue: Auto-Submit <auto-submit@pigweed.google.com.iam.gserviceaccount.com>
Reviewed-by: Ewout van Bekkum <ewout@google.com>
Pigweed-Auto-Submit: Armando Montanez <amontanez@google.com>
diff --git a/BUILD.gn b/BUILD.gn
index cb7f78c..d5d3032 100644
--- a/BUILD.gn
+++ b/BUILD.gn
@@ -263,7 +263,7 @@
"$dir_pw_checksum:tests",
"$dir_pw_chrono:tests",
"$dir_pw_containers:tests",
- "$dir_pw_cpu_exception_armv7m:tests",
+ "$dir_pw_cpu_exception_cortex_m:tests",
"$dir_pw_fuzzer:tests",
"$dir_pw_hdlc:tests",
"$dir_pw_hex_dump:tests",
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 20870ee..9447bda 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -36,7 +36,7 @@
add_subdirectory(pw_chrono_stl EXCLUDE_FROM_ALL)
add_subdirectory(pw_containers EXCLUDE_FROM_ALL)
add_subdirectory(pw_cpu_exception EXCLUDE_FROM_ALL)
-add_subdirectory(pw_cpu_exception_armv7m EXCLUDE_FROM_ALL)
+add_subdirectory(pw_cpu_exception_cortex_m EXCLUDE_FROM_ALL)
add_subdirectory(pw_hdlc EXCLUDE_FROM_ALL)
add_subdirectory(pw_kvs EXCLUDE_FROM_ALL)
add_subdirectory(pw_log EXCLUDE_FROM_ALL)
diff --git a/README.md b/README.md
index 0938a5b..c8804b9 100644
--- a/README.md
+++ b/README.md
@@ -122,7 +122,7 @@
See the "Module Guides" in the documentation for the complete list and
documentation for each, but is a selection of some others:
- - `pw_cpu_exception_armv7m`: Robust low level hardware fault handler for ARM
+ - `pw_cpu_exception_cortex_m`: Robust low level hardware fault handler for ARM
Cortex-M; the handler even has unit tests written in assembly to verify
nested-hardware-fault handling!
diff --git a/docs/BUILD.gn b/docs/BUILD.gn
index 9998446..a9dd619 100644
--- a/docs/BUILD.gn
+++ b/docs/BUILD.gn
@@ -65,7 +65,7 @@
"$dir_pw_cli:docs",
"$dir_pw_containers:docs",
"$dir_pw_cpu_exception:docs",
- "$dir_pw_cpu_exception_armv7m:docs",
+ "$dir_pw_cpu_exception_cortex_m:docs",
"$dir_pw_docgen:docs",
"$dir_pw_doctor:docs",
"$dir_pw_env_setup:docs",
diff --git a/pw_cpu_exception/BUILD.gn b/pw_cpu_exception/BUILD.gn
index 7c6f45d..879bb9c 100644
--- a/pw_cpu_exception/BUILD.gn
+++ b/pw_cpu_exception/BUILD.gn
@@ -69,7 +69,7 @@
# This library is technically optional. It is recommended to use `support` when
# doing basic dumps of CPU state. As an alternative, projects may choose to
# directly depend on the entry backend if they require direct access to
-# pw_CpuExceptionState members.
+# pw_cpu_exception_State members.
pw_facade("support") {
backend = pw_cpu_exception_SUPPORT_BACKEND
public_configs = [ ":default_config" ]
diff --git a/pw_cpu_exception/basic_handler.cc b/pw_cpu_exception/basic_handler.cc
index 689fad3..5bcdadf 100644
--- a/pw_cpu_exception/basic_handler.cc
+++ b/pw_cpu_exception/basic_handler.cc
@@ -18,7 +18,7 @@
namespace pw::cpu_exception {
-extern "C" void pw_CpuExceptionDefaultHandler(pw_CpuExceptionState*) {
+extern "C" void pw_cpu_exception_DefaultHandler(pw_cpu_exception_State*) {
PW_LOG_CRITICAL("Unhandled CPU exception encountered!");
// TODO(pwbug/95): Replace with pw_abort when that module exists.
std::abort();
diff --git a/pw_cpu_exception/docs.rst b/pw_cpu_exception/docs.rst
index ec4892b..d375623 100644
--- a/pw_cpu_exception/docs.rst
+++ b/pw_cpu_exception/docs.rst
@@ -12,13 +12,13 @@
Setup
=====
-An application using this module **must** connect ``pw_CpuExceptionEntry()`` to
-the platform's CPU exception handler interrupt so ``pw_CpuExceptionEntry()`` is
+An application using this module **must** connect ``pw_cpu_exception_Entry()`` to
+the platform's CPU exception handler interrupt so ``pw_cpu_exception_Entry()`` is
called immediately upon a CPU exception. For specifics on how this may be done,
see the backend documentation for your architecture.
Applications must also provide an implementation for
-``pw_CpuExceptionDefaultHandler()``. The behavior of this functions is entirely
+``pw_cpu_exception_DefaultHandler()``. The behavior of this functions is entirely
up to the application/project, but some examples are provided below:
* Enter an infinite loop so the device can be debugged by JTAG.
@@ -31,24 +31,24 @@
Module Usage
============
Basic usage of this module entails applications supplying a definition for
-``pw_CpuExceptionDefaultHandler()``. ``pw_CpuExceptionDefaultHandler()`` should
+``pw_cpu_exception_DefaultHandler()``. ``pw_cpu_exception_DefaultHandler()`` should
contain any logic to determine if a exception can be recovered from, as well as
necessary actions to properly recover. If the device cannot recover from the
exception, the function should **not** return.
-``pw_CpuExceptionDefaultHandler()`` is called indirectly, and may be overridden
-at runtime via ``pw_CpuExceptionSetHandler()``. The handler can also be reset to
-point to ``pw_CpuExceptionDefaultHandler()`` by calling
-``pw_CpuExceptionRestoreDefaultHandler()``.
+``pw_cpu_exception_DefaultHandler()`` is called indirectly, and may be overridden
+at runtime via ``pw_cpu_exception_SetHandler()``. The handler can also be reset to
+point to ``pw_cpu_exception_DefaultHandler()`` by calling
+``pw_cpu_exception_RestoreDefaultHandler()``.
When writing an exception handler, prefer to use the functions provided by this
interface rather than relying on the backend implementation of
-``pw_CpuExceptionState``. This allows better code portability as it helps
+``pw_cpu_exception_State``. This allows better code portability as it helps
prevent an application fault handler from being tied to a single backend.
For example; when logging or dumping CPU state, prefer ``ToString()`` or
``RawFaultingCpuState()`` over directly accessing members of a
-``pw_CpuExceptionState`` object.
+``pw_cpu_exception_State`` object.
Some exception handling behavior may require architecture-specific CPU state to
attempt to correct a fault. In this situation, the application's exception
@@ -60,15 +60,15 @@
mechanisms to capture CPU state for use by an application's exception handler,
and allow recovery from CPU exceptions when possible.
- * A backend should provide a definition for the ``pw_CpuExceptionState``
+ * A backend should provide a definition for the ``pw_cpu_exception_State``
struct that provides suitable means to access and modify any captured CPU
state.
* If an application's exception handler modifies the captured CPU state, the
state should be treated as though it were the original state of the CPU when
the exception occurred. The backend may need to manually restore some of the
modified state to ensure this on exception handler return.
- * A backend should implement the ``pw_CpuExceptionEntry()`` function that will
- call ``pw_HandleCpuException()`` after performing any necessary
+ * A backend should implement the ``pw_cpu_exception_Entry()`` function that will
+ call ``pw_cpu_exception_HandleException()`` after performing any necessary
actions prior to handing control to the application's exception handler
(e.g. capturing necessary CPU state).
diff --git a/pw_cpu_exception/public/pw_cpu_exception/entry.h b/pw_cpu_exception/public/pw_cpu_exception/entry.h
index 53b5a93..158c6e2 100644
--- a/pw_cpu_exception/public/pw_cpu_exception/entry.h
+++ b/pw_cpu_exception/public/pw_cpu_exception/entry.h
@@ -18,21 +18,22 @@
// platform. By default, this module invokes the following user-defined function
// after early exception handling completes:
//
-// pw_CpuExceptionDefaultHandler(pw_CpuExceptionState* state)
+// pw_cpu_exception_DefaultHandler(pw_cpu_exception_State* state)
//
// If platform-dependent access to the CPU registers is needed, then
// applications can include the respective backend module directly; for example
// cpu_exception_armv7m.
//
// IMPORTANT: To use this module, you MUST implement
-// pw_CpuExceptionDefaultHandler() in some part of your application.
+// pw_cpu_exception_DefaultHandler() in some part of your
+// application.
#include "pw_preprocessor/compiler.h"
#include "pw_preprocessor/util.h"
// Low-level raw exception entry handler.
//
-// Captures faulting CPU state into a platform-specific pw_CpuExceptionState
+// Captures faulting CPU state into a platform-specific pw_cpu_exception_State
// object, then calls the user-provided fault handler.
//
// This function should be called immediately after a fault; typically by being
@@ -40,4 +41,7 @@
//
// Note: applications should almost never invoke this directly; if you do, make
// sure you know what you are doing.
+PW_EXTERN_C PW_NO_PROLOGUE void pw_cpu_exception_Entry(void);
+
+// TODO(pwbug/311) Deprecated naming.
PW_EXTERN_C PW_NO_PROLOGUE void pw_CpuExceptionEntry(void);
diff --git a/pw_cpu_exception/public/pw_cpu_exception/handler.h b/pw_cpu_exception/public/pw_cpu_exception/handler.h
index 83c9bf4..f552b17 100644
--- a/pw_cpu_exception/public/pw_cpu_exception/handler.h
+++ b/pw_cpu_exception/public/pw_cpu_exception/handler.h
@@ -18,19 +18,19 @@
PW_EXTERN_C_START
-// Forward declaration of pw_CpuExceptionState. Definition provided by cpu
+// Forward declaration of pw_cpu_exception_State. Definition provided by cpu
// exception entry backend.
-struct pw_CpuExceptionState;
+struct pw_cpu_exception_State;
// By default, the exception entry function will terminate by handing execution
-// over to pw_CpuExceptionDefaultHandler(). This can be used to override the
+// over to pw_cpu_exception_DefaultHandler(). This can be used to override the
// current handler. This allows runtime insertion of an exception handler which
// may also be helpful for loading a bootloader exception handler by default
// that an application overrides.
-void pw_CpuExceptionSetHandler(void (*handler)(pw_CpuExceptionState*));
+void pw_cpu_exception_SetHandler(void (*handler)(pw_cpu_exception_State*));
-// Set the exception handler to point to pw_CpuExceptionDefaultHandler().
-void pw_CpuExceptionRestoreDefaultHandler(void);
+// Set the exception handler to point to pw_cpu_exception_DefaultHandler().
+void pw_cpu_exception_RestoreDefaultHandler(void);
// Application-defined recoverable CPU exception handler.
//
@@ -46,10 +46,19 @@
// attach.
//
// See the cpu_exception module documentation for more details.
-PW_USED void pw_CpuExceptionDefaultHandler(pw_CpuExceptionState* state);
+PW_USED void pw_cpu_exception_DefaultHandler(pw_cpu_exception_State* state);
// This is the underlying function the CPU exception entry backend should call.
// This calls the currently set handler.
-void pw_HandleCpuException(void* cpu_state);
+void pw_cpu_exception_HandleException(void* cpu_state);
+
+// TODO(pwbug/311) Deprecated naming.
+typedef pw_cpu_exception_State pw_CpuExceptionState;
+#define pw_CpuExceptionSetHandler(...) pw_cpu_exception_SetHandler(__VA_ARGS__)
+#define pw_CpuExceptionRestoreDefaultHandler(...) \
+ pw_cpu_exception_RestoreDefaultHandler(__VA_ARGS__)
+#define pw_CpuExceptionDefaultHandler(...) \
+ pw_cpu_exception_DefaultHandler(__VA_ARGS__)
+#define pw_HandleCpuException(...) pw_cpu_exception_HandleException(__VA_ARGS__)
PW_EXTERN_C_END
diff --git a/pw_cpu_exception/public/pw_cpu_exception/support.h b/pw_cpu_exception/public/pw_cpu_exception/support.h
index a078334..77baa18 100644
--- a/pw_cpu_exception/public/pw_cpu_exception/support.h
+++ b/pw_cpu_exception/public/pw_cpu_exception/support.h
@@ -13,32 +13,36 @@
// the License.
// This facade provides an API for capturing the contents of a
-// pw_CpuExceptionState struct in a platform-agnostic way. While this facade
+// pw_cpu_exception_State struct in a platform-agnostic way. While this facade
// does not provide a means to directly access individual members of a
-// pw_CpuExceptionState object, it does allow dumping CPU state without needing
-// to know any specifics about the underlying architecture.
+// pw_cpu_exception_State object, it does allow dumping CPU state without
+// needing to know any specifics about the underlying architecture.
#pragma once
#include <cstdint>
#include <span>
-// Forward declaration of pw_CpuExceptionState. Definition provided by backend.
-struct pw_CpuExceptionState;
+// Forward declaration of pw_cpu_exception_State. Definition provided by
+// backend.
+struct pw_cpu_exception_State;
+
+// TODO(pwbug/311) Deprecated naming.
+typedef pw_cpu_exception_State pw_CpuExceptionState;
namespace pw::cpu_exception {
// Gets raw CPU state as a single contiguous block of data. The particular
// contents will depend on the specific backend and platform.
std::span<const uint8_t> RawFaultingCpuState(
- const pw_CpuExceptionState& cpu_state);
+ const pw_cpu_exception_State& cpu_state);
// Writes CPU state as a formatted string to a string builder.
// NEVER depend on the format of this output. This is exclusively FYI human
// readable output.
-void ToString(const pw_CpuExceptionState& cpu_state,
+void ToString(const pw_cpu_exception_State& cpu_state,
const std::span<char>& dest);
// Logs captured CPU state using pw_log at PW_LOG_LEVEL_INFO.
-void LogCpuState(const pw_CpuExceptionState& cpu_state);
+void LogCpuState(const pw_cpu_exception_State& cpu_state);
} // namespace pw::cpu_exception
diff --git a/pw_cpu_exception/start_exception_handler.cc b/pw_cpu_exception/start_exception_handler.cc
index dc566d9..284bb34 100644
--- a/pw_cpu_exception/start_exception_handler.cc
+++ b/pw_cpu_exception/start_exception_handler.cc
@@ -16,21 +16,21 @@
namespace pw::cpu_exception {
-static void (*exception_handler)(pw_CpuExceptionState*) =
- &pw_CpuExceptionDefaultHandler;
+static void (*exception_handler)(pw_cpu_exception_State*) =
+ &pw_cpu_exception_DefaultHandler;
-extern "C" void pw_CpuExceptionSetHandler(
- void (*handler)(pw_CpuExceptionState*)) {
+extern "C" void pw_cpu_exception_SetHandler(
+ void (*handler)(pw_cpu_exception_State*)) {
exception_handler = handler;
}
-// Revert the exception handler to point to pw_CpuExceptionDefaultHandler().
-extern "C" void pw_CpuExceptionRestoreDefaultHandler() {
- exception_handler = &pw_CpuExceptionDefaultHandler;
+// Revert the exception handler to point to pw_cpu_exception_DefaultHandler().
+extern "C" void pw_cpu_exception_RestoreDefaultHandler() {
+ exception_handler = &pw_cpu_exception_DefaultHandler;
}
-extern "C" void pw_HandleCpuException(void* cpu_state) {
- exception_handler(reinterpret_cast<pw_CpuExceptionState*>(cpu_state));
+extern "C" void pw_cpu_exception_HandleException(void* cpu_state) {
+ exception_handler(reinterpret_cast<pw_cpu_exception_State*>(cpu_state));
}
} // namespace pw::cpu_exception
\ No newline at end of file
diff --git a/pw_cpu_exception_armv7m/BUILD b/pw_cpu_exception_armv7m/BUILD
index 9d90070..b98c438 100644
--- a/pw_cpu_exception_armv7m/BUILD
+++ b/pw_cpu_exception_armv7m/BUILD
@@ -19,16 +19,8 @@
filegroup(
name = "pw_cpu_exception_armv7m",
srcs = [
- "entry.cc",
- "cpu_state.cc",
- "proto_dump.cc",
"public/pw_cpu_exception_armv7m/cpu_state.h",
"public/pw_cpu_exception_armv7m/proto_dump.h",
"pw_cpu_exception_armv7m_private/cortex_m_constants.h",
],
)
-
-filegroup(
- name = "pw_cpu_exception_armv7m_test",
- srcs = ["exception_entry_test.cc"],
-)
diff --git a/pw_cpu_exception_armv7m/BUILD.gn b/pw_cpu_exception_armv7m/BUILD.gn
index a3d6016..ffa1899 100644
--- a/pw_cpu_exception_armv7m/BUILD.gn
+++ b/pw_cpu_exception_armv7m/BUILD.gn
@@ -15,10 +15,6 @@
import("//build_overrides/pigweed.gni")
import("$dir_pw_build/target_types.gni")
-import("$dir_pw_cpu_exception/backend.gni")
-import("$dir_pw_docgen/docs.gni")
-import("$dir_pw_protobuf_compiler/proto.gni")
-import("$dir_pw_unit_test/test.gni")
config("default_config") {
include_dirs = [ "public" ]
@@ -27,60 +23,20 @@
pw_source_set("support") {
public_configs = [ ":default_config" ]
- public_deps = [
- "$dir_pw_cpu_exception:support.facade",
- dir_pw_preprocessor,
- dir_pw_string,
- ]
- deps = [ dir_pw_log ]
+ public_deps = [ "$dir_pw_cpu_exception_cortex_m:support_armv7m" ]
public = [ "public/pw_cpu_exception_armv7m/cpu_state.h" ]
- sources = [
- "cpu_state.cc",
- "pw_cpu_exception_armv7m_private/cortex_m_constants.h",
- ]
}
pw_source_set("proto_dump") {
- public_deps = [
- ":support",
- dir_pw_protobuf,
- dir_pw_status,
- dir_pw_stream,
- ]
+ public_configs = [ ":default_config" ]
+ public_deps = [ "$dir_pw_cpu_exception_cortex_m:proto_dump_armv7m" ]
public = [ "public/pw_cpu_exception_armv7m/proto_dump.h" ]
- deps = [ ":cpu_state_protos.pwpb" ]
- sources = [ "proto_dump.cc" ]
-}
-
-pw_proto_library("cpu_state_protos") {
- sources = [ "pw_cpu_exception_armv7m_protos/cpu_state.proto" ]
}
pw_source_set("pw_cpu_exception_armv7m") {
- public_configs = [ ":default_config" ]
public_deps = [
":proto_dump",
":support",
- "$dir_pw_cpu_exception:entry.facade",
- "$dir_pw_cpu_exception:handler",
- "$dir_pw_preprocessor",
+ "$dir_pw_cpu_exception_cortex_m:cpu_exception_armv7m",
]
- sources = [
- "entry.cc",
- "pw_cpu_exception_armv7m_private/cortex_m_constants.h",
- ]
-}
-
-pw_test_group("tests") {
- enable_if = pw_cpu_exception_ENTRY_BACKEND == dir_pw_cpu_exception_armv7m
- tests = [ ":cpu_exception_entry_test" ]
-}
-
-pw_test("cpu_exception_entry_test") {
- deps = [ ":pw_cpu_exception_armv7m" ]
- sources = [ "exception_entry_test.cc" ]
-}
-
-pw_doc_group("docs") {
- sources = [ "docs.rst" ]
}
diff --git a/pw_cpu_exception_armv7m/CMakeLists.txt b/pw_cpu_exception_armv7m/CMakeLists.txt
index 55d3a01..ff92e06 100644
--- a/pw_cpu_exception_armv7m/CMakeLists.txt
+++ b/pw_cpu_exception_armv7m/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2020 The Pigweed Authors
+# Copyright 2021 The Pigweed Authors
#
# Licensed under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
@@ -15,6 +15,6 @@
include($ENV{PW_ROOT}/pw_build/pigweed.cmake)
pw_auto_add_simple_module(pw_cpu_exception_armv7m
- IMPLEMENTS_FACADE
- pw_cpu_exception
+ PUBLIC_DEPS
+ pw_cpu_exception_cortex_m
)
diff --git a/pw_cpu_exception_armv7m/public/pw_cpu_exception_armv7m/cpu_state.h b/pw_cpu_exception_armv7m/public/pw_cpu_exception_armv7m/cpu_state.h
index 23158c8..3c12945 100644
--- a/pw_cpu_exception_armv7m/public/pw_cpu_exception_armv7m/cpu_state.h
+++ b/pw_cpu_exception_armv7m/public/pw_cpu_exception_armv7m/cpu_state.h
@@ -13,85 +13,4 @@
// the License.
#pragma once
-#include <cstdint>
-
-#include "pw_preprocessor/compiler.h"
-
-namespace pw::cpu_exception {
-
-// This is dictated by ARMv7-M architecture. Do not change.
-PW_PACKED(struct) ArmV7mFaultRegisters {
- uint32_t r0;
- uint32_t r1;
- uint32_t r2;
- uint32_t r3;
- uint32_t r12;
- uint32_t lr; // Link register.
- uint32_t pc; // Program counter.
- uint32_t psr; // Program status register.
-};
-
-// This is dictated by ARMv7-M architecture. Do not change.
-PW_PACKED(struct) ArmV7mFaultRegistersFpu {
- uint32_t s0;
- uint32_t s1;
- uint32_t s2;
- uint32_t s3;
- uint32_t s4;
- uint32_t s5;
- uint32_t s6;
- uint32_t s7;
- uint32_t s8;
- uint32_t s9;
- uint32_t s10;
- uint32_t s11;
- uint32_t s12;
- uint32_t s13;
- uint32_t s14;
- uint32_t s15;
- uint32_t fpscr;
- uint32_t reserved;
-};
-
-// Bit in the PSR that indicates CPU added an extra word on the stack to
-// align it during context save for an exception.
-inline constexpr uint32_t kPsrExtraStackAlignBit = (1 << 9);
-
-// This is dictated by this module, and shouldn't change often.
-// Note that the order of entries in this struct is very important (as the
-// values are populated in assembly).
-//
-// NOTE: Memory mapped registers are NOT restored upon fault return!
-PW_PACKED(struct) ArmV7mExtraRegisters {
- // Memory mapped registers.
- uint32_t cfsr;
- uint32_t mmfar;
- uint32_t bfar;
- uint32_t icsr;
- uint32_t hfsr;
- uint32_t shcsr;
- // Special registers.
- uint32_t exc_return;
- uint32_t msp;
- uint32_t psp;
- uint32_t control;
- // General purpose registers.
- uint32_t r4;
- uint32_t r5;
- uint32_t r6;
- uint32_t r7;
- uint32_t r8;
- uint32_t r9;
- uint32_t r10;
- uint32_t r11;
-};
-
-} // namespace pw::cpu_exception
-
-PW_PACKED(struct) pw_CpuExceptionState {
- pw::cpu_exception::ArmV7mExtraRegisters extended;
- pw::cpu_exception::ArmV7mFaultRegisters base;
- // TODO(amontanez): FPU registers may or may not be here as well. Make the
- // availability of the FPU registers a compile-time configuration when FPU
- // register support is added.
-};
+#include "pw_cpu_exception_cortex_m/cpu_state.h"
diff --git a/pw_cpu_exception_armv7m/public/pw_cpu_exception_armv7m/proto_dump.h b/pw_cpu_exception_armv7m/public/pw_cpu_exception_armv7m/proto_dump.h
index b4d99a2..3b873da 100644
--- a/pw_cpu_exception_armv7m/public/pw_cpu_exception_armv7m/proto_dump.h
+++ b/pw_cpu_exception_armv7m/public/pw_cpu_exception_armv7m/proto_dump.h
@@ -13,21 +13,4 @@
// the License.
#pragma once
-#include "pw_cpu_exception_armv7m/cpu_state.h"
-#include "pw_protobuf/encoder.h"
-#include "pw_status/status.h"
-
-namespace pw::cpu_exception {
-
-// Dumps the cpu state struct as a proto (defined in
-// pw_cpu_exception_armv7m_protos/cpu_state.proto). The final proto is up to 144
-// bytes in size, so ensure your encoder is properly sized.
-//
-// Returns:
-// OK - Entire proto was written to the encoder.
-// RESOURCE_EXHAUSTED - Insufficient space to encode proto.
-// UNKNOWN - Some other proto encoding error occurred.
-Status DumpCpuStateProto(protobuf::Encoder& dest,
- const pw_CpuExceptionState& cpu_state);
-
-} // namespace pw::cpu_exception
+#include "pw_cpu_exception_cortex_m/proto_dump.h"
diff --git a/pw_cpu_exception_cortex_m/BUILD b/pw_cpu_exception_cortex_m/BUILD
new file mode 100644
index 0000000..a39d11c
--- /dev/null
+++ b/pw_cpu_exception_cortex_m/BUILD
@@ -0,0 +1,85 @@
+# Copyright 2021 The Pigweed Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License. You may obtain a copy of
+# the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations under
+# the License.
+
+load(
+ "//pw_build:pigweed.bzl",
+ "pw_cc_binary",
+ "pw_cc_library",
+ "pw_cc_test",
+)
+
+package(default_visibility = ["//visibility:public"])
+
+licenses(["notice"]) # Apache License 2.0
+
+pw_cc_library(
+ name = "support_armv7m",
+ includes = ["public"],
+ deps = [
+ "//pw_preprocessor",
+ "//pw_string",
+ "//pw_log",
+ ],
+ hdrs = [ "public/pw_cpu_exception_cortex_m/cpu_state.h" ],
+ srcs = [
+ "cpu_state.cc",
+ "pw_cpu_exception_cortex_m_private/cortex_m_constants.h",
+ ],
+)
+
+pw_cc_library(
+ name = "proto_dump_armv7m",
+ deps = [
+ ":support_armv7m",
+ ":cpu_state_protos",
+ "//pw_protobuf",
+ "//pw_status",
+ "//pw_stream",
+ ],
+ hdrs = ["public/pw_cpu_exception_cortex_m/proto_dump.h"],
+ srcs = ["proto_dump.cc"],
+)
+
+proto_library(
+ name = "cpu_state_protos",
+ srcs = ["pw_cpu_exception_cortex_m_protos/cpu_state.proto"],
+)
+
+# TODO(pwbug/296): The *_armv7m libraries work on ARMv8-M, but needs some minor
+# patches for complete correctness. Add *_armv8m targets that use the same files
+# but provide preprocessor defines to enable/disable architecture specific code.
+pw_cc_library(
+ name = "cpu_exception_armv7m",
+ deps = [
+ ":proto_dump_armv7m",
+ ":support_armv7m",
+ # TODO(pwbug/101): Need to add support for facades/backends to Bazel.
+ "//pw_cpu_exception",
+ "//pw_preprocessor",
+ ],
+ srcs = [
+ "entry.cc",
+ "pw_cpu_exception_cortex_m_private/cortex_m_constants.h",
+ ],
+)
+
+pw_cc_test(
+ name = "cpu_exception_entry_test",
+ srcs = [
+ "exception_entry_test.cc",
+ ],
+ deps = [
+ ":cpu_exception_armv7m",
+ ],
+)
diff --git a/pw_cpu_exception_cortex_m/BUILD.gn b/pw_cpu_exception_cortex_m/BUILD.gn
new file mode 100644
index 0000000..a0a9096
--- /dev/null
+++ b/pw_cpu_exception_cortex_m/BUILD.gn
@@ -0,0 +1,90 @@
+# Copyright 2019 The Pigweed Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License. You may obtain a copy of
+# the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations under
+# the License.
+
+import("//build_overrides/pigweed.gni")
+
+import("$dir_pw_build/target_types.gni")
+import("$dir_pw_cpu_exception/backend.gni")
+import("$dir_pw_docgen/docs.gni")
+import("$dir_pw_protobuf_compiler/proto.gni")
+import("$dir_pw_unit_test/test.gni")
+
+config("default_config") {
+ include_dirs = [ "public" ]
+ visibility = [ ":*" ]
+}
+
+pw_source_set("support_armv7m") {
+ public_configs = [ ":default_config" ]
+ public_deps = [
+ "$dir_pw_cpu_exception:support.facade",
+ dir_pw_preprocessor,
+ dir_pw_string,
+ ]
+ deps = [ dir_pw_log ]
+ public = [ "public/pw_cpu_exception_cortex_m/cpu_state.h" ]
+ sources = [
+ "cpu_state.cc",
+ "pw_cpu_exception_cortex_m_private/cortex_m_constants.h",
+ ]
+}
+
+pw_source_set("proto_dump_armv7m") {
+ public_deps = [
+ ":support_armv7m",
+ dir_pw_protobuf,
+ dir_pw_status,
+ dir_pw_stream,
+ ]
+ public = [ "public/pw_cpu_exception_cortex_m/proto_dump.h" ]
+ deps = [ ":cpu_state_protos.pwpb" ]
+ sources = [ "proto_dump.cc" ]
+}
+
+pw_proto_library("cpu_state_protos") {
+ sources = [ "pw_cpu_exception_cortex_m_protos/cpu_state.proto" ]
+}
+
+# TODO(pwbug/296): The *_armv7m libraries work on ARMv8-M, but needs some minor
+# patches for complete correctness. Add *_armv8m targets that use the same files
+# but provide preprocessor defines to enable/disable architecture specific code.
+pw_source_set("cpu_exception_armv7m") {
+ public_configs = [ ":default_config" ]
+ public_deps = [
+ ":proto_dump_armv7m",
+ ":support_armv7m",
+ "$dir_pw_cpu_exception:entry.facade",
+ "$dir_pw_cpu_exception:handler",
+ "$dir_pw_preprocessor",
+ ]
+ sources = [
+ "entry.cc",
+ "pw_cpu_exception_cortex_m_private/cortex_m_constants.h",
+ ]
+}
+
+pw_test_group("tests") {
+ enable_if = pw_cpu_exception_ENTRY_BACKEND ==
+ "$dir_pw_cpu_exception_cortex_m:cpu_exception_armv7m"
+ tests = [ ":cpu_exception_entry_test" ]
+}
+
+pw_test("cpu_exception_entry_test") {
+ deps = [ ":cpu_exception_armv7m" ]
+ sources = [ "exception_entry_test.cc" ]
+}
+
+pw_doc_group("docs") {
+ sources = [ "docs.rst" ]
+}
diff --git a/pw_cpu_exception_cortex_m/CMakeLists.txt b/pw_cpu_exception_cortex_m/CMakeLists.txt
new file mode 100644
index 0000000..c434a21
--- /dev/null
+++ b/pw_cpu_exception_cortex_m/CMakeLists.txt
@@ -0,0 +1,20 @@
+# Copyright 2020 The Pigweed Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License. You may obtain a copy of
+# the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations under
+# the License.
+
+include($ENV{PW_ROOT}/pw_build/pigweed.cmake)
+
+pw_auto_add_simple_module(pw_cpu_exception_cortex_m
+ IMPLEMENTS_FACADE
+ pw_cpu_exception
+)
diff --git a/pw_cpu_exception_armv7m/cpu_state.cc b/pw_cpu_exception_cortex_m/cpu_state.cc
similarity index 92%
rename from pw_cpu_exception_armv7m/cpu_state.cc
rename to pw_cpu_exception_cortex_m/cpu_state.cc
index 0c65f7f..7ee6e03 100644
--- a/pw_cpu_exception_armv7m/cpu_state.cc
+++ b/pw_cpu_exception_cortex_m/cpu_state.cc
@@ -12,14 +12,14 @@
// License for the specific language governing permissions and limitations under
// the License.
-#include "pw_cpu_exception_armv7m/cpu_state.h"
+#include "pw_cpu_exception_cortex_m/cpu_state.h"
#include <cinttypes>
#include <cstdint>
#include <span>
#include "pw_cpu_exception/support.h"
-#include "pw_cpu_exception_armv7m_private/cortex_m_constants.h"
+#include "pw_cpu_exception_cortex_m_private/cortex_m_constants.h"
#include "pw_log/log.h"
#include "pw_string/string_builder.h"
@@ -108,7 +108,7 @@
}
}
-void AnalyzeException(const pw_CpuExceptionState& cpu_state) {
+void AnalyzeException(const pw_cpu_exception_State& cpu_state) {
// This provides a high-level assessment of the cause of the exception.
// These conditionals are ordered by priority to ensure the most critical
// issues are highlighted first. These are not mutually exclusive; a bus fault
@@ -154,17 +154,17 @@
} // namespace
std::span<const uint8_t> RawFaultingCpuState(
- const pw_CpuExceptionState& cpu_state) {
+ const pw_cpu_exception_State& cpu_state) {
return std::span(reinterpret_cast<const uint8_t*>(&cpu_state),
sizeof(cpu_state));
}
// Using this function adds approximately 100 bytes to binary size.
-void ToString(const pw_CpuExceptionState& cpu_state,
+void ToString(const pw_cpu_exception_State& cpu_state,
const std::span<char>& dest) {
StringBuilder builder(dest);
- const ArmV7mFaultRegisters& base = cpu_state.base;
- const ArmV7mExtraRegisters& extended = cpu_state.extended;
+ const CortexMExceptionRegisters& base = cpu_state.base;
+ const CortexMExtraRegisters& extended = cpu_state.extended;
#define _PW_FORMAT_REGISTER(state_section, name) \
builder.Format("%s=0x%08" PRIx32 "\n", #name, state_section.name)
@@ -203,9 +203,9 @@
}
// Using this function adds approximately 100 bytes to binary size.
-void LogCpuState(const pw_CpuExceptionState& cpu_state) {
- const ArmV7mFaultRegisters& base = cpu_state.base;
- const ArmV7mExtraRegisters& extended = cpu_state.extended;
+void LogCpuState(const pw_cpu_exception_State& cpu_state) {
+ const CortexMExceptionRegisters& base = cpu_state.base;
+ const CortexMExtraRegisters& extended = cpu_state.extended;
AnalyzeException(cpu_state);
diff --git a/pw_cpu_exception_armv7m/docs.rst b/pw_cpu_exception_cortex_m/docs.rst
similarity index 86%
rename from pw_cpu_exception_armv7m/docs.rst
rename to pw_cpu_exception_cortex_m/docs.rst
index 5f1d58c..fd23ec6 100644
--- a/pw_cpu_exception_armv7m/docs.rst
+++ b/pw_cpu_exception_cortex_m/docs.rst
@@ -1,8 +1,8 @@
-.. _module-pw_cpu_exception_armv7m:
+.. _module-pw_cpu_exception_cortex_m:
------------------------
-pw_cpu_exception_armv7m
------------------------
+-------------------------
+pw_cpu_exception_cortex_m
+-------------------------
This backend provides an ARMv7-M implementation for the CPU exception module
frontend. See the CPU exception frontend module description for more
information.
@@ -13,13 +13,13 @@
application's exception handler is properly called during an exception.
**1. Use existing CMSIS functions**
- Inside of CMSIS fault handler functions, branch to ``pw_CpuExceptionEntry``.
+ Inside of CMSIS fault handler functions, branch to ``pw_cpu_exception_Entry``.
.. code-block:: cpp
__attribute__((naked)) void HardFault_Handler(void) {
asm volatile(
- " ldr r0, =pw_CpuExceptionEntry \n"
+ " ldr r0, =pw_cpu_exception_Entry \n"
" bx r0 \n");
}
@@ -50,11 +50,11 @@
__isr_vector_table:
.word __stack_start
.word Reset_Handler
- .word pw_CpuExceptionEntry
- .word pw_CpuExceptionEntry
- .word pw_CpuExceptionEntry
- .word pw_CpuExceptionEntry
- .word pw_CpuExceptionEntry
+ .word pw_cpu_exception_Entry
+ .word pw_cpu_exception_Entry
+ .word pw_cpu_exception_Entry
+ .word pw_cpu_exception_Entry
+ .word pw_cpu_exception_Entry
Note: ``__isr_vector_table`` and ``__stack_start`` are example names, and may
vary by platform. See your platform's assembly startup script.
@@ -65,7 +65,7 @@
exception_entry_test integration test), but keep in mind that your
application's exception handler will not be entered if an exception occurs
before the vector table entries are updated to point to
- ``pw_CpuExceptionEntry``.
+ ``pw_cpu_exception_Entry``.
Module Usage
============
@@ -74,9 +74,9 @@
is preferred.
However, some projects may need to explicitly access architecture-specific
-registers to attempt to recover from a CPU exception. ``pw_CpuExceptionState``
+registers to attempt to recover from a CPU exception. ``pw_cpu_exception_State``
provides access to the captured CPU state at the time of the fault. When the
-application-provided ``pw_CpuExceptionDefaultHandler()`` function returns, the
+application-provided ``pw_cpu_exception_DefaultHandler()`` function returns, the
CPU state is restored. This allows the exception handler to modify the captured
state so that execution can safely continue.
diff --git a/pw_cpu_exception_armv7m/entry.cc b/pw_cpu_exception_cortex_m/entry.cc
similarity index 83%
rename from pw_cpu_exception_armv7m/entry.cc
rename to pw_cpu_exception_cortex_m/entry.cc
index b90dcb7..97925f5 100644
--- a/pw_cpu_exception_armv7m/entry.cc
+++ b/pw_cpu_exception_cortex_m/entry.cc
@@ -18,10 +18,14 @@
#include <cstring>
#include "pw_cpu_exception/handler.h"
-#include "pw_cpu_exception_armv7m/cpu_state.h"
-#include "pw_cpu_exception_armv7m_private/cortex_m_constants.h"
+#include "pw_cpu_exception_cortex_m/cpu_state.h"
+#include "pw_cpu_exception_cortex_m_private/cortex_m_constants.h"
#include "pw_preprocessor/compiler.h"
+// TODO(pwbug/311): Deprecated naming.
+PW_EXTERN_C PW_NO_PROLOGUE __attribute__((alias("pw_cpu_exception_Entry"))) void
+pw_CpuExceptionEntry(void);
+
namespace pw::cpu_exception {
namespace {
@@ -37,13 +41,13 @@
// Checks exc_return in the captured CPU state to determine which stack pointer
// was in use prior to entering the exception handler.
-bool PspWasActive(const pw_CpuExceptionState& cpu_state) {
+bool PspWasActive(const pw_cpu_exception_State& cpu_state) {
return cpu_state.extended.exc_return & kExcReturnStackMask;
}
// Checks exc_return to determine if FPU state was pushed to the stack in
// addition to the base CPU context frame.
-bool FpuStateWasPushed(const pw_CpuExceptionState& cpu_state) {
+bool FpuStateWasPushed(const pw_cpu_exception_State& cpu_state) {
return !(cpu_state.extended.exc_return & kExcReturnBasicFrameMask);
}
@@ -51,17 +55,17 @@
//
// For more information see (See ARMv7-M Section B1.5.11, derived exceptions
// on exception entry).
-void CloneBaseRegistersFromPsp(pw_CpuExceptionState* cpu_state) {
+void CloneBaseRegistersFromPsp(pw_cpu_exception_State* cpu_state) {
// If CPU succeeded in pushing context to PSP, copy it to the MSP.
if (!(cpu_state->extended.cfsr & kCfsrStkerrMask) &&
!(cpu_state->extended.cfsr & kCfsrMstkerrMask)) {
- // TODO(amontanez): {r0-r3,r12} are captured in pw_CpuExceptionEntry(),
+ // TODO(amontanez): {r0-r3,r12} are captured in pw_cpu_exception_Entry(),
// so this only really needs to copy pc, lr, and psr. Could
// (possibly) improve speed, but would add marginally more
// complexity.
std::memcpy(&cpu_state->base,
reinterpret_cast<void*>(cpu_state->extended.psp),
- sizeof(ArmV7mFaultRegisters));
+ sizeof(CortexMExceptionRegisters));
} else {
// If CPU context wasn't pushed to stack on exception entry, we can't
// recover psr, lr, and pc from exception-time. Make these values clearly
@@ -77,7 +81,7 @@
//
// For more information see (See ARMv7-M Section B1.5.11, derived exceptions
// on exception entry).
-void RestoreBaseRegistersToPsp(pw_CpuExceptionState* cpu_state) {
+void RestoreBaseRegistersToPsp(pw_cpu_exception_State* cpu_state) {
// If CPU succeeded in pushing context to PSP on exception entry, restore the
// contents of cpu_state to the CPU-pushed register frame so the CPU can
// continue. Otherwise, don't attempt as we'll likely end up in an escalated
@@ -86,15 +90,15 @@
!(cpu_state->extended.cfsr & kCfsrMstkerrMask)) {
std::memcpy(reinterpret_cast<void*>(cpu_state->extended.psp),
&cpu_state->base,
- sizeof(ArmV7mFaultRegisters));
+ sizeof(CortexMExceptionRegisters));
}
}
// Determines the size of the CPU-pushed context frame.
-uint32_t CpuContextSize(const pw_CpuExceptionState& cpu_state) {
- uint32_t cpu_context_size = sizeof(ArmV7mFaultRegisters);
+uint32_t CpuContextSize(const pw_cpu_exception_State& cpu_state) {
+ uint32_t cpu_context_size = sizeof(CortexMExceptionRegisters);
if (FpuStateWasPushed(cpu_state)) {
- cpu_context_size += sizeof(ArmV7mFaultRegistersFpu);
+ cpu_context_size += sizeof(CortexMExceptionRegistersFpu);
}
if (cpu_state.base.psr & kPsrExtraStackAlignBit) {
// Account for the extra 4-bytes the processor
@@ -108,7 +112,7 @@
// On exception entry, the Program Stack Pointer is patched to reflect the state
// at exception-time. On exception return, it is restored to the appropriate
// location. This calculates the delta that is used for these patch operations.
-uint32_t CalculatePspDelta(const pw_CpuExceptionState& cpu_state) {
+uint32_t CalculatePspDelta(const pw_cpu_exception_State& cpu_state) {
// If CPU context was not pushed to program stack (because program stack
// wasn't in use, or an error occurred when pushing context), the PSP doesn't
// need to be shifted.
@@ -123,16 +127,16 @@
// On exception entry, the Main Stack Pointer is patched to reflect the state
// at exception-time. On exception return, it is restored to the appropriate
// location. This calculates the delta that is used for these patch operations.
-uint32_t CalculateMspDelta(const pw_CpuExceptionState& cpu_state) {
+uint32_t CalculateMspDelta(const pw_cpu_exception_State& cpu_state) {
if (PspWasActive(cpu_state)) {
// TODO(amontanez): Since FPU state isn't captured at this time, we ignore
// it when patching MSP. To add FPU capture support,
// delete this if block as CpuContextSize() will include
// FPU context size in the calculation.
- return sizeof(ArmV7mFaultRegisters) + sizeof(ArmV7mExtraRegisters);
+ return sizeof(CortexMExceptionRegisters) + sizeof(CortexMExtraRegisters);
}
- return CpuContextSize(cpu_state) + sizeof(ArmV7mExtraRegisters);
+ return CpuContextSize(cpu_state) + sizeof(CortexMExtraRegisters);
}
} // namespace
@@ -141,17 +145,18 @@
// Collect remaining CPU state (memory mapped registers), populate memory mapped
// registers, and call application exception handler.
-PW_USED void pw_PackageAndHandleCpuException(pw_CpuExceptionState* cpu_state) {
+PW_USED void pw_PackageAndHandleCpuException(
+ pw_cpu_exception_State* cpu_state) {
// Capture memory mapped registers.
- cpu_state->extended.cfsr = arm_v7m_cfsr;
- cpu_state->extended.mmfar = arm_v7m_mmfar;
- cpu_state->extended.bfar = arm_v7m_bfar;
- cpu_state->extended.icsr = arm_v7m_icsr;
- cpu_state->extended.hfsr = arm_v7m_hfsr;
- cpu_state->extended.shcsr = arm_v7m_shcsr;
+ cpu_state->extended.cfsr = cortex_m_cfsr;
+ cpu_state->extended.mmfar = cortex_m_mmfar;
+ cpu_state->extended.bfar = cortex_m_bfar;
+ cpu_state->extended.icsr = cortex_m_icsr;
+ cpu_state->extended.hfsr = cortex_m_hfsr;
+ cpu_state->extended.shcsr = cortex_m_shcsr;
// CPU may have automatically pushed state to the program stack. If it did,
- // the values can be copied into in the pw_CpuExceptionState struct that is
+ // the values can be copied into in the pw_cpu_exception_State struct that is
// passed to HandleCpuException(). The cpu_state passed to the handler is
// ALWAYS stored on the main stack (MSP).
if (PspWasActive(*cpu_state)) {
@@ -164,7 +169,7 @@
cpu_state->extended.msp += CalculateMspDelta(*cpu_state);
// Call application-level exception handler.
- pw_HandleCpuException(cpu_state);
+ pw_cpu_exception_HandleException(cpu_state);
// Restore program stack pointer so exception return can restore state if
// needed.
@@ -193,8 +198,9 @@
// Captures faulting CPU state on the main stack (MSP), then calls the exception
// handlers.
// This function should be called immediately after an exception.
-void pw_CpuExceptionEntry(void) {
+void pw_cpu_exception_Entry(void) {
asm volatile(
+ // clang-format off
// If PSP was in use at the time of exception, it's possible the CPU
// wasn't able to push CPU state. To be safe, this first captures scratch
// registers before moving forward.
@@ -205,8 +211,9 @@
// for more details)
// The following block of assembly is equivalent to:
// if (lr & (1 << 2)) {
- // msp -= sizeof(ArmV7mFaultRegisters);
- // ArmV7mFaultRegisters* state = (ArmV7mFaultRegisters*) msp;
+ // msp -= sizeof(CortexMExceptionRegisters);
+ // CortexMExceptionRegisters* state =
+ // (CortexMExceptionRegisters*) msp;
// state->r0 = r0;
// state->r1 = r1;
// state->r2 = r2;
@@ -269,10 +276,9 @@
// Exit exception.
" bx lr \n"
- // clang-format off
: /*output=*/
- : /*input=*/[base_state_size]"i"(sizeof(ArmV7mFaultRegisters)),
- [extra_state_size]"i"(sizeof(ArmV7mExtraRegisters))
+ : /*input=*/[base_state_size]"i"(sizeof(CortexMExceptionRegisters)),
+ [extra_state_size]"i"(sizeof(CortexMExtraRegisters))
// clang-format on
);
}
diff --git a/pw_cpu_exception_armv7m/exception_entry_test.cc b/pw_cpu_exception_cortex_m/exception_entry_test.cc
similarity index 89%
rename from pw_cpu_exception_armv7m/exception_entry_test.cc
rename to pw_cpu_exception_cortex_m/exception_entry_test.cc
index 7cf2226..842bcd4 100644
--- a/pw_cpu_exception_armv7m/exception_entry_test.cc
+++ b/pw_cpu_exception_cortex_m/exception_entry_test.cc
@@ -20,7 +20,7 @@
#include "pw_cpu_exception/entry.h"
#include "pw_cpu_exception/handler.h"
#include "pw_cpu_exception/support.h"
-#include "pw_cpu_exception_armv7m/cpu_state.h"
+#include "pw_cpu_exception_cortex_m/cpu_state.h"
namespace pw::cpu_exception {
namespace {
@@ -59,17 +59,17 @@
constexpr uint32_t kFpuEnableMask = (0xFu << 20);
// Memory mapped registers. (ARMv7-M Section B3.2.2, Table B3-4)
-volatile uint32_t& arm_v7m_vtor =
+volatile uint32_t& cortex_m_vtor =
*reinterpret_cast<volatile uint32_t*>(0xE000ED08u);
-volatile uint32_t& arm_v7m_ccr =
+volatile uint32_t& cortex_m_ccr =
*reinterpret_cast<volatile uint32_t*>(0xE000ED14u);
-volatile uint32_t& arm_v7m_shcsr =
+volatile uint32_t& cortex_m_shcsr =
*reinterpret_cast<volatile uint32_t*>(0xE000ED24u);
-volatile uint32_t& arm_v7m_cfsr =
+volatile uint32_t& cortex_m_cfsr =
*reinterpret_cast<volatile uint32_t*>(0xE000ED28u);
-volatile uint32_t& arm_v7m_hfsr =
+volatile uint32_t& cortex_m_hfsr =
*reinterpret_cast<volatile uint32_t*>(0xE000ED2Cu);
-volatile uint32_t& arm_v7m_cpacr =
+volatile uint32_t& cortex_m_cpacr =
*reinterpret_cast<volatile uint32_t*>(0xE000ED88u);
// Begin a critical section that must not be interrupted.
@@ -109,14 +109,14 @@
void EnableFpu() {
#if defined(PW_ARMV7M_ENABLE_FPU) && PW_ARMV7M_ENABLE_FPU == 1
// TODO(pwbug/17): Replace when Pigweed config system is added.
- arm_v7m_cpacr |= kFpuEnableMask;
+ cortex_m_cpacr |= kFpuEnableMask;
#endif // defined(PW_ARMV7M_ENABLE_FPU) && PW_ARMV7M_ENABLE_FPU == 1
}
void DisableFpu() {
#if defined(PW_ARMV7M_ENABLE_FPU) && PW_ARMV7M_ENABLE_FPU == 1
// TODO(pwbug/17): Replace when Pigweed config system is added.
- arm_v7m_cpacr &= ~kFpuEnableMask;
+ cortex_m_cpacr &= ~kFpuEnableMask;
#endif // defined(PW_ARMV7M_ENABLE_FPU) && PW_ARMV7M_ENABLE_FPU == 1
}
@@ -134,10 +134,10 @@
// Variable to prevent more than kMaxFaultDepth nested crashes.
size_t current_fault_depth = 0;
-// Faulting pw_CpuExceptionState is copied here so values can be validated after
-// exiting exception handler.
-pw_CpuExceptionState captured_states[kMaxFaultDepth] = {};
-pw_CpuExceptionState& captured_state = captured_states[0];
+// Faulting pw_cpu_exception_State is copied here so values can be validated
+// after exiting exception handler.
+pw_cpu_exception_State captured_states[kMaxFaultDepth] = {};
+pw_cpu_exception_State& captured_state = captured_states[0];
// Flag used to check if the contents of std::span matches the captured state.
bool span_matches = false;
@@ -150,7 +150,7 @@
volatile float float_test_value;
// Magic pattern to help identify if the exception handler's
-// pw_CpuExceptionState pointer was pointing to captured CPU state that was
+// pw_cpu_exception_State pointer was pointing to captured CPU state that was
// pushed onto the stack when the faulting context uses the VFP. Has to be
// computed at runtime because it uses values only available at link time.
const float kFloatTestPattern = 12.345f * 67.89f;
@@ -162,12 +162,12 @@
#define _PW_TEST_FPU_OPERATION (fpu_lhs_val * fpu_rhs_val)
// Magic pattern to help identify if the exception handler's
-// pw_CpuExceptionState pointer was pointing to captured CPU state that was
+// pw_cpu_exception_State pointer was pointing to captured CPU state that was
// pushed onto the stack.
constexpr uint32_t kMagicPattern = 0xDEADBEEF;
// This pattern serves a purpose similar to kMagicPattern, but is used for
-// testing a nested fault to ensure both pw_CpuExceptionState objects are
+// testing a nested fault to ensure both pw_cpu_exception_State objects are
// correctly captured.
constexpr uint32_t kNestedMagicPattern = 0x900DF00D;
@@ -180,12 +180,12 @@
InterruptVectorTable ram_vector_table;
// Forward declaration of the exception handler.
-void TestingExceptionHandler(pw_CpuExceptionState*);
+void TestingExceptionHandler(pw_cpu_exception_State*);
// Populate the device's registers with testable values, then trigger exception.
void BeginBaseFaultTest() {
// Make sure divide by zero causes a fault.
- arm_v7m_ccr |= kDivByZeroTrapEnableMask;
+ cortex_m_ccr |= kDivByZeroTrapEnableMask;
uint32_t magic = kMagicPattern;
asm volatile(
" mov r0, %[magic] \n"
@@ -208,7 +208,7 @@
// Populate the device's registers with testable values, then trigger exception.
void BeginNestedFaultTest() {
// Make sure divide by zero causes a fault.
- arm_v7m_ccr |= kUnalignedTrapEnableMask;
+ cortex_m_ccr |= kUnalignedTrapEnableMask;
volatile uint32_t magic = kNestedMagicPattern;
asm volatile(
" mov r0, %[magic] \n"
@@ -230,7 +230,7 @@
// the fault handlers correction for psp.
void BeginBaseFaultUnalignedStackTest() {
// Make sure divide by zero causes a fault.
- arm_v7m_ccr |= kDivByZeroTrapEnableMask;
+ cortex_m_ccr |= kDivByZeroTrapEnableMask;
uint32_t magic = kMagicPattern;
asm volatile(
// Push one register to cause $sp to be no longer 8-byte aligned,
@@ -260,7 +260,7 @@
// exception.
void BeginExtendedFaultTest() {
// Make sure divide by zero causes a fault.
- arm_v7m_ccr |= kDivByZeroTrapEnableMask;
+ cortex_m_ccr |= kDivByZeroTrapEnableMask;
uint32_t magic = kMagicPattern;
volatile uint32_t local_msp = 0;
volatile uint32_t local_psp = 0;
@@ -294,7 +294,7 @@
// the fault handlers correction for psp.
void BeginExtendedFaultUnalignedStackTest() {
// Make sure divide by zero causes a fault.
- arm_v7m_ccr |= kDivByZeroTrapEnableMask;
+ cortex_m_ccr |= kDivByZeroTrapEnableMask;
uint32_t magic = kMagicPattern;
volatile uint32_t local_msp = 0;
volatile uint32_t local_psp = 0;
@@ -331,36 +331,36 @@
void InstallVectorTableEntries() {
uint32_t prev_state = BeginCriticalSection();
// If vector table is installed already, this is done.
- if (arm_v7m_vtor == reinterpret_cast<uint32_t>(&ram_vector_table)) {
+ if (cortex_m_vtor == reinterpret_cast<uint32_t>(&ram_vector_table)) {
EndCriticalSection(prev_state);
return;
}
// Copy table to new location since it's not guaranteed that we can write to
// the original one.
std::memcpy(&ram_vector_table,
- reinterpret_cast<uint32_t*>(arm_v7m_vtor),
+ reinterpret_cast<uint32_t*>(cortex_m_vtor),
sizeof(ram_vector_table));
// Override exception handling vector table entries.
uint32_t* exception_entry_addr =
- reinterpret_cast<uint32_t*>(pw_CpuExceptionEntry);
+ reinterpret_cast<uint32_t*>(pw_cpu_exception_Entry);
uint32_t** interrupts = reinterpret_cast<uint32_t**>(&ram_vector_table);
interrupts[kHardFaultIsrNum] = exception_entry_addr;
interrupts[kMemFaultIsrNum] = exception_entry_addr;
interrupts[kBusFaultIsrNum] = exception_entry_addr;
interrupts[kUsageFaultIsrNum] = exception_entry_addr;
- uint32_t old_vector_table = arm_v7m_vtor;
+ uint32_t old_vector_table = cortex_m_vtor;
// Dismiss unused variable warning for non-debug builds.
PW_UNUSED(old_vector_table);
// Update Vector Table Offset Register (VTOR) to point to new vector table.
- arm_v7m_vtor = reinterpret_cast<uint32_t>(&ram_vector_table);
+ cortex_m_vtor = reinterpret_cast<uint32_t>(&ram_vector_table);
EndCriticalSection(prev_state);
}
void EnableAllFaultHandlers() {
- arm_v7m_shcsr |=
+ cortex_m_shcsr |=
kMemFaultEnableMask | kBusFaultEnableMask | kUsageFaultEnableMask;
}
@@ -370,7 +370,7 @@
} else {
DisableFpu();
}
- pw_CpuExceptionSetHandler(TestingExceptionHandler);
+ pw_cpu_exception_SetHandler(TestingExceptionHandler);
EnableAllFaultHandlers();
InstallVectorTableEntries();
exceptions_handled = 0;
@@ -417,7 +417,7 @@
BeginExtendedFaultTest();
ASSERT_EQ(exceptions_handled, 1u);
ASSERT_TRUE(span_matches);
- const ArmV7mExtraRegisters& extended_registers = captured_state.extended;
+ const CortexMExtraRegisters& extended_registers = captured_state.extended;
// captured_state values must be cast since they're in a packed struct.
EXPECT_EQ(static_cast<uint32_t>(extended_registers.r4), kMagicPattern);
EXPECT_EQ(static_cast<uint32_t>(extended_registers.r5), 0u);
@@ -434,7 +434,7 @@
BeginExtendedFaultUnalignedStackTest();
ASSERT_EQ(exceptions_handled, 1u);
ASSERT_TRUE(span_matches);
- const ArmV7mExtraRegisters& extended_registers = captured_state.extended;
+ const CortexMExtraRegisters& extended_registers = captured_state.extended;
// captured_state values must be cast since they're in a packed struct.
EXPECT_EQ(static_cast<uint32_t>(extended_registers.r4), kMagicPattern);
EXPECT_EQ(static_cast<uint32_t>(extended_registers.r5), 0u);
@@ -510,7 +510,7 @@
Setup(/*use_fpu=*/true);
BeginExtendedFaultFloatTest();
ASSERT_EQ(exceptions_handled, 1u);
- const ArmV7mExtraRegisters& extended_registers = captured_state.extended;
+ const CortexMExtraRegisters& extended_registers = captured_state.extended;
// captured_state values must be cast since they're in a packed struct.
EXPECT_EQ(static_cast<uint32_t>(extended_registers.r4), kMagicPattern);
EXPECT_EQ(static_cast<uint32_t>(extended_registers.r5), 0u);
@@ -533,7 +533,7 @@
BeginExtendedFaultUnalignedStackFloatTest();
ASSERT_EQ(exceptions_handled, 1u);
ASSERT_TRUE(span_matches);
- const ArmV7mExtraRegisters& extended_registers = captured_state.extended;
+ const CortexMExtraRegisters& extended_registers = captured_state.extended;
// captured_state values must be cast since they're in a packed struct.
EXPECT_EQ(static_cast<uint32_t>(extended_registers.r4), kMagicPattern);
EXPECT_EQ(static_cast<uint32_t>(extended_registers.r5), 0u);
@@ -553,7 +553,7 @@
#endif // defined(PW_ARMV7M_ENABLE_FPU) && PW_ARMV7M_ENABLE_FPU == 1
-void TestingExceptionHandler(pw_CpuExceptionState* state) {
+void TestingExceptionHandler(pw_cpu_exception_State* state) {
if (++current_fault_depth > kMaxFaultDepth) {
volatile bool loop = true;
while (loop) {
@@ -570,31 +570,31 @@
// Clear HFSR forced (nested) hard fault mask if set. This will only be
// set by the nested fault test.
- EXPECT_EQ(state->extended.hfsr, arm_v7m_hfsr);
- if (arm_v7m_hfsr & kForcedHardfaultMask) {
- arm_v7m_hfsr = kForcedHardfaultMask;
+ EXPECT_EQ(state->extended.hfsr, cortex_m_hfsr);
+ if (cortex_m_hfsr & kForcedHardfaultMask) {
+ cortex_m_hfsr = kForcedHardfaultMask;
}
- if (arm_v7m_cfsr & kUnalignedFaultMask) {
+ if (cortex_m_cfsr & kUnalignedFaultMask) {
// Copy captured state to check later.
std::memcpy(&captured_states[exceptions_handled],
state,
- sizeof(pw_CpuExceptionState));
+ sizeof(pw_cpu_exception_State));
// Disable unaligned read/write trapping to "handle" exception.
- arm_v7m_ccr &= ~kUnalignedTrapEnableMask;
- arm_v7m_cfsr = kUnalignedFaultMask;
+ cortex_m_ccr &= ~kUnalignedTrapEnableMask;
+ cortex_m_cfsr = kUnalignedFaultMask;
exceptions_handled++;
return;
- } else if (arm_v7m_cfsr & kDivByZeroFaultMask) {
+ } else if (cortex_m_cfsr & kDivByZeroFaultMask) {
// Copy captured state to check later.
std::memcpy(&captured_states[exceptions_handled],
state,
- sizeof(pw_CpuExceptionState));
+ sizeof(pw_cpu_exception_State));
// Ensure std::span compares to be the same.
std::span<const uint8_t> state_span = RawFaultingCpuState(*state);
- EXPECT_EQ(state_span.size(), sizeof(pw_CpuExceptionState));
+ EXPECT_EQ(state_span.size(), sizeof(pw_cpu_exception_State));
if (std::memcmp(state, state_span.data(), state_span.size()) == 0) {
span_matches = true;
} else {
@@ -602,13 +602,13 @@
}
// Disable divide-by-zero trapping to "handle" exception.
- arm_v7m_ccr &= ~kDivByZeroTrapEnableMask;
- arm_v7m_cfsr = kDivByZeroFaultMask;
+ cortex_m_ccr &= ~kDivByZeroTrapEnableMask;
+ cortex_m_cfsr = kDivByZeroFaultMask;
exceptions_handled++;
return;
}
- EXPECT_EQ(state->extended.shcsr, arm_v7m_shcsr);
+ EXPECT_EQ(state->extended.shcsr, cortex_m_shcsr);
// If an unexpected exception occurred, just enter an infinite loop.
while (true) {
diff --git a/pw_cpu_exception_armv7m/proto_dump.cc b/pw_cpu_exception_cortex_m/proto_dump.cc
similarity index 90%
rename from pw_cpu_exception_armv7m/proto_dump.cc
rename to pw_cpu_exception_cortex_m/proto_dump.cc
index cc71733..0faec5a 100644
--- a/pw_cpu_exception_armv7m/proto_dump.cc
+++ b/pw_cpu_exception_cortex_m/proto_dump.cc
@@ -11,16 +11,16 @@
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations under
// the License.
-#include "pw_cpu_exception_armv7m/cpu_state.h"
-#include "pw_cpu_exception_armv7m_protos/cpu_state.pwpb.h"
+#include "pw_cpu_exception_cortex_m/cpu_state.h"
+#include "pw_cpu_exception_cortex_m_protos/cpu_state.pwpb.h"
#include "pw_preprocessor/compiler.h"
#include "pw_protobuf/encoder.h"
namespace pw::cpu_exception {
Status DumpCpuStateProto(protobuf::Encoder& dest,
- const pw_CpuExceptionState& cpu_state) {
- armv7m::ArmV7mCpuState::Encoder state_encoder(&dest);
+ const pw_cpu_exception_State& cpu_state) {
+ cortex_m::ArmV7mCpuState::Encoder state_encoder(&dest);
// Special and mem-mapped registers.
state_encoder.WritePc(cpu_state.base.pc);
diff --git a/pw_cpu_exception_cortex_m/public/pw_cpu_exception_cortex_m/cpu_state.h b/pw_cpu_exception_cortex_m/public/pw_cpu_exception_cortex_m/cpu_state.h
new file mode 100644
index 0000000..8d79633
--- /dev/null
+++ b/pw_cpu_exception_cortex_m/public/pw_cpu_exception_cortex_m/cpu_state.h
@@ -0,0 +1,100 @@
+// Copyright 2019 The Pigweed Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License"); you may not
+// use this file except in compliance with the License. You may obtain a copy of
+// the License at
+//
+// https://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+// License for the specific language governing permissions and limitations under
+// the License.
+#pragma once
+
+#include <cstdint>
+
+#include "pw_preprocessor/compiler.h"
+
+namespace pw::cpu_exception {
+
+// This is dictated by ARMv7-M architecture. Do not change.
+PW_PACKED(struct) CortexMExceptionRegisters {
+ uint32_t r0;
+ uint32_t r1;
+ uint32_t r2;
+ uint32_t r3;
+ uint32_t r12;
+ uint32_t lr; // Link register.
+ uint32_t pc; // Program counter.
+ uint32_t psr; // Program status register.
+};
+
+// This is dictated by ARMv7-M architecture. Do not change.
+PW_PACKED(struct) CortexMExceptionRegistersFpu {
+ uint32_t s0;
+ uint32_t s1;
+ uint32_t s2;
+ uint32_t s3;
+ uint32_t s4;
+ uint32_t s5;
+ uint32_t s6;
+ uint32_t s7;
+ uint32_t s8;
+ uint32_t s9;
+ uint32_t s10;
+ uint32_t s11;
+ uint32_t s12;
+ uint32_t s13;
+ uint32_t s14;
+ uint32_t s15;
+ uint32_t fpscr;
+ uint32_t reserved;
+};
+
+// Bit in the PSR that indicates CPU added an extra word on the stack to
+// align it during context save for an exception.
+inline constexpr uint32_t kPsrExtraStackAlignBit = (1 << 9);
+
+// This is dictated by this module, and shouldn't change often.
+// Note that the order of entries in this struct is very important (as the
+// values are populated in assembly).
+//
+// NOTE: Memory mapped registers are NOT restored upon fault return!
+PW_PACKED(struct) CortexMExtraRegisters {
+ // Memory mapped registers.
+ uint32_t cfsr;
+ uint32_t mmfar;
+ uint32_t bfar;
+ uint32_t icsr;
+ uint32_t hfsr;
+ uint32_t shcsr;
+ // Special registers.
+ uint32_t exc_return;
+ uint32_t msp;
+ uint32_t psp;
+ uint32_t control;
+ // General purpose registers.
+ uint32_t r4;
+ uint32_t r5;
+ uint32_t r6;
+ uint32_t r7;
+ uint32_t r8;
+ uint32_t r9;
+ uint32_t r10;
+ uint32_t r11;
+};
+
+} // namespace pw::cpu_exception
+
+PW_PACKED(struct) pw_cpu_exception_State {
+ pw::cpu_exception::CortexMExtraRegisters extended;
+ pw::cpu_exception::CortexMExceptionRegisters base;
+ // TODO(amontanez): FPU registers may or may not be here as well. Make the
+ // availability of the FPU registers a compile-time configuration when FPU
+ // register support is added.
+};
+
+// TODO(pwbug/311): Deprecated naming.
+typedef pw_cpu_exception_State pw_CpuExceptionState;
diff --git a/pw_cpu_exception_cortex_m/public/pw_cpu_exception_cortex_m/proto_dump.h b/pw_cpu_exception_cortex_m/public/pw_cpu_exception_cortex_m/proto_dump.h
new file mode 100644
index 0000000..8a8d5ba
--- /dev/null
+++ b/pw_cpu_exception_cortex_m/public/pw_cpu_exception_cortex_m/proto_dump.h
@@ -0,0 +1,33 @@
+// Copyright 2020 The Pigweed Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License"); you may not
+// use this file except in compliance with the License. You may obtain a copy of
+// the License at
+//
+// https://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+// License for the specific language governing permissions and limitations under
+// the License.
+#pragma once
+
+#include "pw_cpu_exception_cortex_m/cpu_state.h"
+#include "pw_protobuf/encoder.h"
+#include "pw_status/status.h"
+
+namespace pw::cpu_exception {
+
+// Dumps the cpu state struct as a proto (defined in
+// pw_cpu_exception_cortex_m_protos/cpu_state.proto). The final proto is up to
+// 144 bytes in size, so ensure your encoder is properly sized.
+//
+// Returns:
+// OK - Entire proto was written to the encoder.
+// RESOURCE_EXHAUSTED - Insufficient space to encode proto.
+// UNKNOWN - Some other proto encoding error occurred.
+Status DumpCpuStateProto(protobuf::Encoder& dest,
+ const pw_cpu_exception_State& cpu_state);
+
+} // namespace pw::cpu_exception
diff --git a/pw_cpu_exception_armv7m/pw_cpu_exception_armv7m_private/cortex_m_constants.h b/pw_cpu_exception_cortex_m/pw_cpu_exception_cortex_m_private/cortex_m_constants.h
similarity index 92%
rename from pw_cpu_exception_armv7m/pw_cpu_exception_armv7m_private/cortex_m_constants.h
rename to pw_cpu_exception_cortex_m/pw_cpu_exception_cortex_m_private/cortex_m_constants.h
index c1ee60c..f384187 100644
--- a/pw_cpu_exception_armv7m/pw_cpu_exception_armv7m_private/cortex_m_constants.h
+++ b/pw_cpu_exception_cortex_m/pw_cpu_exception_cortex_m_private/cortex_m_constants.h
@@ -73,17 +73,18 @@
constexpr uint32_t kExcReturnBasicFrameMask = 0x1u << 4;
// Memory mapped registers. (ARMv7-M Section B3.2.2, Table B3-4)
-inline volatile uint32_t& arm_v7m_cfsr =
+// TODO(pwbug/316): Only some of these are supported on ARMv6-M.
+inline volatile uint32_t& cortex_m_cfsr =
*reinterpret_cast<volatile uint32_t*>(0xE000ED28u);
-inline volatile uint32_t& arm_v7m_mmfar =
+inline volatile uint32_t& cortex_m_mmfar =
*reinterpret_cast<volatile uint32_t*>(0xE000ED34u);
-inline volatile uint32_t& arm_v7m_bfar =
+inline volatile uint32_t& cortex_m_bfar =
*reinterpret_cast<volatile uint32_t*>(0xE000ED38u);
-inline volatile uint32_t& arm_v7m_icsr =
+inline volatile uint32_t& cortex_m_icsr =
*reinterpret_cast<volatile uint32_t*>(0xE000ED04u);
-inline volatile uint32_t& arm_v7m_hfsr =
+inline volatile uint32_t& cortex_m_hfsr =
*reinterpret_cast<volatile uint32_t*>(0xE000ED2Cu);
-inline volatile uint32_t& arm_v7m_shcsr =
+inline volatile uint32_t& cortex_m_shcsr =
*reinterpret_cast<volatile uint32_t*>(0xE000ED24u);
} // namespace pw::cpu_exception
diff --git a/pw_cpu_exception_armv7m/pw_cpu_exception_armv7m_protos/cpu_state.proto b/pw_cpu_exception_cortex_m/pw_cpu_exception_cortex_m_protos/cpu_state.proto
similarity index 97%
rename from pw_cpu_exception_armv7m/pw_cpu_exception_armv7m_protos/cpu_state.proto
rename to pw_cpu_exception_cortex_m/pw_cpu_exception_cortex_m_protos/cpu_state.proto
index a557d0e..ad1a054 100644
--- a/pw_cpu_exception_armv7m/pw_cpu_exception_armv7m_protos/cpu_state.proto
+++ b/pw_cpu_exception_cortex_m/pw_cpu_exception_cortex_m_protos/cpu_state.proto
@@ -13,7 +13,7 @@
// the License.
syntax = "proto2";
-package pw.cpu_exception.armv7m;
+package pw.cpu_exception.cortex_m;
message ArmV7mCpuState {
optional uint32 pc = 1;
diff --git a/pw_cpu_exception_cortex_m/py/exception_analyzer_test.py b/pw_cpu_exception_cortex_m/py/exception_analyzer_test.py
index eed73e4..8566c5b 100644
--- a/pw_cpu_exception_cortex_m/py/exception_analyzer_test.py
+++ b/pw_cpu_exception_cortex_m/py/exception_analyzer_test.py
@@ -23,8 +23,8 @@
CPU_STATE_PROTO_PATH = os.path.join(
env.pigweed_environment().PW_ROOT, #pylint: disable=no-member
- 'pw_cpu_exception_armv7m',
- 'pw_cpu_exception_armv7m_protos',
+ 'pw_cpu_exception_cortex_m',
+ 'pw_cpu_exception_cortex_m_protos',
'cpu_state.proto')
cpu_state_pb2 = python_protos.compile_and_import_file(CPU_STATE_PROTO_PATH)
diff --git a/targets/lm3s6965evb-qemu/target_toolchains.gni b/targets/lm3s6965evb-qemu/target_toolchains.gni
index c9ff4ed..b66ccd0 100644
--- a/targets/lm3s6965evb-qemu/target_toolchains.gni
+++ b/targets/lm3s6965evb-qemu/target_toolchains.gni
@@ -45,7 +45,8 @@
# appear the divide-by-zero traps as expected when enabled, which prevents the
# module from triggering a recoverable exception. Since pw_cpu_exception is
# not fully set up on this target, disable it for now.
- # pw_cpu_exception_ENTRY_BACKEND = dir_pw_cpu_exception_armv7m
+ # pw_cpu_exception_ENTRY_BACKEND =
+ # "$dir_pw_cpu_exception_cortex_m:cpu_exception_armv7m
pw_boot_armv7m_LINK_CONFIG_DEFINES = [
"PW_BOOT_FLASH_BEGIN=0x00000200",
diff --git a/targets/stm32f429i-disc1/target_toolchains.gni b/targets/stm32f429i-disc1/target_toolchains.gni
index 06f8d1c..6efc896 100644
--- a/targets/stm32f429i-disc1/target_toolchains.gni
+++ b/targets/stm32f429i-disc1/target_toolchains.gni
@@ -45,9 +45,11 @@
# Facade backends
pw_assert_BACKEND = dir_pw_assert_basic
pw_boot_BACKEND = dir_pw_boot_armv7m
- pw_cpu_exception_ENTRY_BACKEND = dir_pw_cpu_exception_armv7m
+ pw_cpu_exception_ENTRY_BACKEND =
+ "$dir_pw_cpu_exception_cortex_m:cpu_exception_armv7m"
pw_cpu_exception_HANDLER_BACKEND = "$dir_pw_cpu_exception:basic_handler"
- pw_cpu_exception_SUPPORT_BACKEND = "$dir_pw_cpu_exception_armv7m:support"
+ pw_cpu_exception_SUPPORT_BACKEND =
+ "$dir_pw_cpu_exception_cortex_m:support_armv7m"
pw_sync_SPIN_LOCK_BACKEND = "$dir_pw_sync_baremetal:spin_lock_backend"
pw_log_BACKEND = dir_pw_log_basic
pw_sys_io_BACKEND = dir_pw_sys_io_baremetal_stm32f429
