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| <title>Zynq PS configuration detail</title> | |
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| <script type="text/javascript" language="JavaScript">function ChangeSilRegLink(id) { var ver=document.getElementById(id).value; if (ver == "Silicon3.0") { document.getElementById("MIO_Registers").href="#psu_mio_init_data_3_0"; document.getElementById("PLL_Registers").href="#psu_pll_init_data_3_0"; document.getElementById("Clock_Registers").href="#psu_clock_init_data_3_0"; document.getElementById("DDR_Registers").href="#psu_ddr_init_data_3_0"; document.getElementById("Peri_Registers").href="#psu_peripherals_init_data_3_0"; window.location = '#psu_mio_init_data_3_0'; } else if (ver == "Silicon2.0") { document.getElementById("MIO_Registers").href="#psu_mio_init_data_2_0"; document.getElementById("PLL_Registers").href="#psu_pll_init_data_2_0"; document.getElementById("Clock_Registers").href="#psu_clock_init_data_2_0"; document.getElementById("DDR_Registers").href="#psu_ddr_init_data_2_0"; document.getElementById("Peri_Registers").href="#psu_peripherals_init_data_2_0"; window.location = '#psu_mio_init_data_2_0'; } else { document.getElementById("MIO_Registers").href="#psu_mio_init_data_1_0"; document.getElementById("PLL_Registers").href="#psu_pll_init_data_1_0"; document.getElementById("Clock_Registers").href="#psu_clock_init_data_1_0"; document.getElementById("DDR_Registers").href="#psu_ddr_init_data_1_0"; document.getElementById("Peri_Registers").href="#psu_peripherals_init_data_1_0"; window.location = '#psu_mio_init_data_1_0'; }}</script> | |
| <body> | |
| <DIV class="navbar"> | |
| <DIV class="navlink_container"> | |
| <A id="Summary" href="#"> | |
| <li> | |
| <DIV class="navlink">Zynq PS Register Summary Viewer | |
| </DIV> | |
| </li> | |
| </A> | |
| </DIV> | |
| </DIV> | |
| <DIV class="action_tray"> | |
| <A id="Report" href="#"> | |
| <DIV class="sitename">Zynq PS7 Summary Report | |
| </DIV> | |
| </A> | |
| <DIV class="viewButtons">User Configurations | |
| </DIV> | |
| <DIV class="viewButtons"> | |
| <A id="MIO_Configurations" href="#ZynqPerTab"> | |
| <DIV class="viewButtonHalf">MIO Configurations | |
| </DIV> | |
| </A> | |
| <HR class="action_separator"> | |
| <A id="CLK_Configurations" href="#ClockInfoTab"> | |
| <DIV class="viewButtonHalf">CLK Configurations | |
| </DIV> | |
| </A> | |
| <HR class="action_separator"> | |
| <A id="DDR_Configurations" href="#DDRInfoTab"> | |
| <DIV class="viewButtonHalf">DDR Configurations | |
| </DIV> | |
| </A> | |
| <HR class="action_separator"> | |
| <A id="SMC_Configurations" href="#SMCInfoTab"> | |
| <DIV class="viewButtonHalf">SMC Configurations | |
| </DIV> | |
| </A> | |
| </DIV> | |
| <DIV class="db_selector"> | |
| <DIV class="db_selector_title">Select Version: | |
| <select id="db_selection" class="db_selection" onChange="ChangeSilRegLink(this.id)" width="210" style="width: 210px"> | |
| <option value="Silicon3.0">Silicon 3.0</option> | |
| <option value="Silicon2.0">Silicon 2.0</option> | |
| <option value="Silicon1.0">Silicon 1.0</option> | |
| </select> | |
| </DIV> | |
| </DIV> | |
| <DIV class="viewButtons">Zynq Register View | |
| </DIV> | |
| <DIV class="action_container"> | |
| <A id="MIO_Registers" href="#psu_mio_init_data"> | |
| <DIV class="action">MIO Registers | |
| </DIV> | |
| </A> | |
| <A id="PLL_Registers" href="#psu_pll_init_data"> | |
| <DIV class="action">PLL Registers | |
| </DIV> | |
| </A> | |
| <A id="Clock_Registers" href="#psu_clock_init_data"> | |
| <DIV class="action">Clock Registers | |
| </DIV> | |
| </A> | |
| <A id="DDR_Registers" href="#psu_ddr_init_data"> | |
| <DIV class="action">DDR Registers | |
| </DIV> | |
| </A> | |
| <A id="Peri_Registers" href="#psu_peripherals_init_data"> | |
| <DIV class="action">Peripherals Registers | |
| </DIV> | |
| </A> | |
| </DIV> | |
| <DIV class="content_container">This design is targeted for7vx485tboard (part number: ) | |
| <br> | |
| <H1>Zynq Design Summary</H1> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=20% BGCOLOR=#C0C0FF> | |
| <B>Device</B> | |
| </TD> | |
| <TD width=80% BGCOLOR=#E6E6E6> | |
| 7vx485t | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=20% BGCOLOR=#C0C0FF> | |
| <B>SpeedGrade</B> | |
| </TD> | |
| <TD width=80% BGCOLOR=#E6E6E6> | |
| 7vx485t | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=20% BGCOLOR=#C0C0FF> | |
| <B>Part</B> | |
| </TD> | |
| <TD width=80% BGCOLOR=#E6E6E6> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=20% BGCOLOR=#C0C0FF> | |
| <B>Description</B> | |
| </TD> | |
| <TD width=80% BGCOLOR=#E6E6E6> | |
| Zynq PS Configuration Report with register details | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=20% BGCOLOR=#C0C0FF> | |
| <B>Vendor</B> | |
| </TD> | |
| <TD width=80% BGCOLOR=#E6E6E6> | |
| Xilinx | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <H2><a name="ZynqPerTab">MIO Table View</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#C0C0FF> | |
| <B>MIO Pin</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0FF> | |
| <B>Peripheral</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0FF> | |
| <B>Signal</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0FF> | |
| <B>IO Type</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0FF> | |
| <B>Speed</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0FF> | |
| <B>Pullup</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0FF> | |
| <B>Direction</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| Single Quad SPI (4bit) | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| sclk_out | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| out | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| Single Quad SPI (4bit) | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| so_mo1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| Single Quad SPI (4bit) | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| mo2 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| Single Quad SPI (4bit) | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| mo3 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| Single Quad SPI (4bit) | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| si_mi0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| Single Quad SPI (4bit) | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| n_ss_out | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| out | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 6</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| GPIO0 MIO | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| gpio0[6] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| GPIO0 MIO | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| gpio0[7] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| GPIO0 MIO | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| gpio0[8] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 9</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| GPIO0 MIO | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| gpio0[9] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 10</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| NAND | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| nfc_rb_n[0] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| in | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 11</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| NAND | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| nfc_rb_n[1] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| in | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 12</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| GPIO0 MIO | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| gpio0[12] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 13</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| NAND | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| nfc_ce[0] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| out | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 14</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| NAND | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| nfc_cle | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| out | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 15</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| NAND | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| nfc_ale | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| out | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| NAND | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| nfc_dq_out[0] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 17</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| NAND | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| nfc_dq_out[1] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| NAND | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| nfc_dq_out[2] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 19</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| NAND | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| nfc_dq_out[3] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 20</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| NAND | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| nfc_dq_out[4] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 21</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| NAND | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| nfc_dq_out[5] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 22</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| NAND | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| nfc_we_b | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| out | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 23</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| NAND | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| nfc_dq_out[6] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| NAND | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| nfc_dq_out[7] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 25</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| NAND | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| nfc_re_n | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| out | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 26</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| NAND | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| nfc_ce[1] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| out | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 27</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| GPIO1 MIO | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| gpio1[27] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 28</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| GPIO1 MIO | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| gpio1[28] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 29</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| SPI 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| n_ss_out[0] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| GPIO1 MIO | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| gpio1[30] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| GPIO1 MIO | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| gpio1[31] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| NAND | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| nfc_dqs_out | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 33</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| GPIO1 MIO | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| gpio1[33] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 34</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| GPIO1 MIO | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| gpio1[34] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 35</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| SPI 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| n_ss_out[0] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 36</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| GPIO1 MIO | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| gpio1[36] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 37</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| GPIO1 MIO | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| gpio1[37] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 38</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| GPIO1 MIO | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| gpio1[38] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 39</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| SD 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| sdio1_data_out[4] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 40</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| SD 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| sdio1_data_out[5] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 41</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| SD 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| sdio1_data_out[6] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 42</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| SD 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| sdio1_data_out[7] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 43</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| SD 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| sdio1_bus_pow | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| out | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 44</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| GPIO1 MIO | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| gpio1[44] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 45</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| GPIO1 MIO | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| gpio1[45] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 46</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| SD 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| sdio1_data_out[0] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 47</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| SD 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| sdio1_data_out[1] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 48</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| SD 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| sdio1_data_out[2] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 49</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| SD 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| sdio1_data_out[3] | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 50</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| SD 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| sdio1_cmd_out | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| inout | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 51</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| SD 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| sdio1_clk_out | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| out | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 52</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| USB 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| ulpi_clk_in | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| in | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>MIO 53</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| USB 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| ulpi_dir | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 0 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| 1 | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| in | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <H2><a name="psu_pll_init_data">psu_pll_init_data</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFC0FF> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_RPLL_CTRL"> | |
| PSU_CRL_APB_RPLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0030</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_RPLL_CTRL"> | |
| PSU_CRL_APB_RPLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0030</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_RPLL_CTRL"> | |
| PSU_CRL_APB_RPLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0030</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_RPLL_CTRL"> | |
| PSU_CRL_APB_RPLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0030</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_RPLL_CTRL"> | |
| PSU_CRL_APB_RPLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0030</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_RPLL_TO_FPD_CTRL"> | |
| PSU_CRL_APB_RPLL_TO_FPD_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0048</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_IOPLL_CTRL"> | |
| PSU_CRL_APB_IOPLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_IOPLL_CTRL"> | |
| PSU_CRL_APB_IOPLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_IOPLL_CTRL"> | |
| PSU_CRL_APB_IOPLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_IOPLL_CTRL"> | |
| PSU_CRL_APB_IOPLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_IOPLL_CTRL"> | |
| PSU_CRL_APB_IOPLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_IOPLL_TO_FPD_CTRL"> | |
| PSU_CRL_APB_IOPLL_TO_FPD_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0044</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_APLL_CTRL"> | |
| PSU_CRF_APB_APLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_APLL_CTRL"> | |
| PSU_CRF_APB_APLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_APLL_CTRL"> | |
| PSU_CRF_APB_APLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_APLL_CTRL"> | |
| PSU_CRF_APB_APLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_APLL_CTRL"> | |
| PSU_CRF_APB_APLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_APLL_TO_LPD_CTRL"> | |
| PSU_CRF_APB_APLL_TO_LPD_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0048</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_DPLL_CTRL"> | |
| PSU_CRF_APB_DPLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A002C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_DPLL_CTRL"> | |
| PSU_CRF_APB_DPLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A002C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_DPLL_CTRL"> | |
| PSU_CRF_APB_DPLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A002C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_DPLL_CTRL"> | |
| PSU_CRF_APB_DPLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A002C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_DPLL_CTRL"> | |
| PSU_CRF_APB_DPLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A002C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_DPLL_TO_LPD_CTRL"> | |
| PSU_CRF_APB_DPLL_TO_LPD_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A004C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_VPLL_CTRL"> | |
| PSU_CRF_APB_VPLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0038</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_VPLL_CTRL"> | |
| PSU_CRF_APB_VPLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0038</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_VPLL_CTRL"> | |
| PSU_CRF_APB_VPLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0038</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_VPLL_CTRL"> | |
| PSU_CRF_APB_VPLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0038</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_VPLL_CTRL"> | |
| PSU_CRF_APB_VPLL_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0038</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_VPLL_TO_LPD_CTRL"> | |
| PSU_CRF_APB_VPLL_TO_LPD_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0050</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="psu_pll_init_data">psu_pll_init_data</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFC0FF> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <H1>RPLL INIT</H1> | |
| <H1>UPDATE FB_DIV</H1> | |
| <H2><a name="RPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)RPLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>RPLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0030</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RPLL_CTRL_FBDIV</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>14:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>30</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>The integer portion of the feedback divider to the PLL</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RPLL_CTRL_DIV2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>16:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>10000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_RPLL_CTRL@0XFF5E0030</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>17f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>13000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>BY PASS PLL</H1> | |
| <H2><a name="RPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)RPLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>RPLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0030</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RPLL_CTRL_BYPASS</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_RPLL_CTRL@0XFF5E0030</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>ASSERT RESET</H1> | |
| <H2><a name="RPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)RPLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>RPLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0030</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RPLL_CTRL_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Asserts Reset to the PLL</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_RPLL_CTRL@0XFF5E0030</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>DEASSERT RESET</H1> | |
| <H2><a name="RPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)RPLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>RPLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0030</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RPLL_CTRL_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Asserts Reset to the PLL</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_RPLL_CTRL@0XFF5E0030</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>CHECK PLL STATUS</H1> | |
| <H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PLL_STATUS</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0040</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_PLL_STATUS_RPLL_LOCK</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>RPLL is locked</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_PLL_STATUS@0XFF5E0040</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>tobe</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>REMOVE PLL BY PASS</H1> | |
| <H2><a name="RPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)RPLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>RPLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0030</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RPLL_CTRL_BYPASS</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_RPLL_CTRL@0XFF5E0030</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="RPLL_TO_FPD_CTRL">Register (<A href=#mod___slcr> slcr </A>)RPLL_TO_FPD_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>RPLL_TO_FPD_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0048</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>300</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Divisor value for this clock.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_RPLL_TO_FPD_CTRL@0XFF5E0048</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>300</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>RPLL FRAC CFG</H1> | |
| <H1>IOPLL INIT</H1> | |
| <H1>UPDATE FB_DIV</H1> | |
| <H2><a name="IOPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IOPLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>IOPLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_IOPLL_CTRL_FBDIV</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>14:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3c</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3c00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>The integer portion of the feedback divider to the PLL</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_IOPLL_CTRL_DIV2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>16:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>10000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_IOPLL_CTRL@0XFF5E0020</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>17f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>13c00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>BY PASS PLL</H1> | |
| <H2><a name="IOPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IOPLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>IOPLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_IOPLL_CTRL_BYPASS</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_IOPLL_CTRL@0XFF5E0020</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>ASSERT RESET</H1> | |
| <H2><a name="IOPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IOPLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>IOPLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_IOPLL_CTRL_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Asserts Reset to the PLL</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_IOPLL_CTRL@0XFF5E0020</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>DEASSERT RESET</H1> | |
| <H2><a name="IOPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IOPLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>IOPLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_IOPLL_CTRL_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Asserts Reset to the PLL</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_IOPLL_CTRL@0XFF5E0020</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>CHECK PLL STATUS</H1> | |
| <H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PLL_STATUS</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0040</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>IOPLL is locked</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_PLL_STATUS@0XFF5E0040</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>tobe</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>REMOVE PLL BY PASS</H1> | |
| <H2><a name="IOPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IOPLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>IOPLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_IOPLL_CTRL_BYPASS</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_IOPLL_CTRL@0XFF5E0020</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="IOPLL_TO_FPD_CTRL">Register (<A href=#mod___slcr> slcr </A>)IOPLL_TO_FPD_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>IOPLL_TO_FPD_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0044</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>400</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Divisor value for this clock.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_IOPLL_TO_FPD_CTRL@0XFF5E0044</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>400</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>IOPLL FRAC CFG</H1> | |
| <H1>APU_PLL INIT</H1> | |
| <H1>UPDATE FB_DIV</H1> | |
| <H2><a name="APLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)APLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>APLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_APLL_CTRL_FBDIV</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>14:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3c</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3c00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>The integer portion of the feedback divider to the PLL</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_APLL_CTRL_DIV2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>16:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>10000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_APLL_CTRL@0XFD1A0020</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>17f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>13c00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>BY PASS PLL</H1> | |
| <H2><a name="APLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)APLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>APLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_APLL_CTRL_BYPASS</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_APLL_CTRL@0XFD1A0020</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>ASSERT RESET</H1> | |
| <H2><a name="APLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)APLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>APLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_APLL_CTRL_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Asserts Reset to the PLL</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_APLL_CTRL@0XFD1A0020</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>DEASSERT RESET</H1> | |
| <H2><a name="APLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)APLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>APLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_APLL_CTRL_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Asserts Reset to the PLL</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_APLL_CTRL@0XFD1A0020</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>CHECK PLL STATUS</H1> | |
| <H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PLL_STATUS</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0044</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_PLL_STATUS_APLL_LOCK</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>APLL is locked</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_PLL_STATUS@0XFD1A0044</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>tobe</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>REMOVE PLL BY PASS</H1> | |
| <H2><a name="APLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)APLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>APLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_APLL_CTRL_BYPASS</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_APLL_CTRL@0XFD1A0020</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="APLL_TO_LPD_CTRL">Register (<A href=#mod___slcr> slcr </A>)APLL_TO_LPD_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>APLL_TO_LPD_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0048</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>400</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Divisor value for this clock.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_APLL_TO_LPD_CTRL@0XFD1A0048</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>400</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>APLL FRAC CFG</H1> | |
| <H1>DDR_PLL INIT</H1> | |
| <H1>UPDATE FB_DIV</H1> | |
| <H2><a name="DPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DPLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>DPLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A002C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DPLL_CTRL_FBDIV</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>14:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3c</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3c00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>The integer portion of the feedback divider to the PLL</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DPLL_CTRL_DIV2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>16:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>10000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_DPLL_CTRL@0XFD1A002C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>17f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>13c00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>BY PASS PLL</H1> | |
| <H2><a name="DPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DPLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>DPLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A002C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DPLL_CTRL_BYPASS</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_DPLL_CTRL@0XFD1A002C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>ASSERT RESET</H1> | |
| <H2><a name="DPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DPLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>DPLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A002C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DPLL_CTRL_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Asserts Reset to the PLL</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_DPLL_CTRL@0XFD1A002C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>DEASSERT RESET</H1> | |
| <H2><a name="DPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DPLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>DPLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A002C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DPLL_CTRL_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Asserts Reset to the PLL</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_DPLL_CTRL@0XFD1A002C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>CHECK PLL STATUS</H1> | |
| <H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PLL_STATUS</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0044</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_PLL_STATUS_DPLL_LOCK</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>DPLL is locked</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_PLL_STATUS@0XFD1A0044</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>tobe</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>REMOVE PLL BY PASS</H1> | |
| <H2><a name="DPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DPLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>DPLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A002C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DPLL_CTRL_BYPASS</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_DPLL_CTRL@0XFD1A002C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="DPLL_TO_LPD_CTRL">Register (<A href=#mod___slcr> slcr </A>)DPLL_TO_LPD_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>DPLL_TO_LPD_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A004C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>400</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Divisor value for this clock.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_DPLL_TO_LPD_CTRL@0XFD1A004C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>400</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>DPLL FRAC CFG</H1> | |
| <H1>VIDEO_PLL INIT</H1> | |
| <H1>UPDATE FB_DIV</H1> | |
| <H2><a name="VPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)VPLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>VPLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0038</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_VPLL_CTRL_FBDIV</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>14:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>The integer portion of the feedback divider to the PLL</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_VPLL_CTRL_DIV2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>16:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>10000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_VPLL_CTRL@0XFD1A0038</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>17f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>13f00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>BY PASS PLL</H1> | |
| <H2><a name="VPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)VPLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>VPLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0038</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_VPLL_CTRL_BYPASS</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_VPLL_CTRL@0XFD1A0038</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>ASSERT RESET</H1> | |
| <H2><a name="VPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)VPLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>VPLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0038</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_VPLL_CTRL_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Asserts Reset to the PLL</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_VPLL_CTRL@0XFD1A0038</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>DEASSERT RESET</H1> | |
| <H2><a name="VPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)VPLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>VPLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0038</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_VPLL_CTRL_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Asserts Reset to the PLL</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_VPLL_CTRL@0XFD1A0038</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>CHECK PLL STATUS</H1> | |
| <H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PLL_STATUS</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0044</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_PLL_STATUS_VPLL_LOCK</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>VPLL is locked</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_PLL_STATUS@0XFD1A0044</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>tobe</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>REMOVE PLL BY PASS</H1> | |
| <H2><a name="VPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)VPLL_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>VPLL_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0038</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_VPLL_CTRL_BYPASS</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_VPLL_CTRL@0XFD1A0038</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>PLL Basic Control</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="VPLL_TO_LPD_CTRL">Register (<A href=#mod___slcr> slcr </A>)VPLL_TO_LPD_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>VPLL_TO_LPD_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0050</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>400</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Divisor value for this clock.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_VPLL_TO_LPD_CTRL@0XFD1A0050</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>400</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>VIDEO FRAC CFG</H1> | |
| </TABLE> | |
| <P> | |
| <H2><a name="psu_clock_init_data">psu_clock_init_data</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFC0FF> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_GEM0_REF_CTRL"> | |
| PSU_CRL_APB_GEM0_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0050</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_GEM1_REF_CTRL"> | |
| PSU_CRL_APB_GEM1_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0054</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_GEM2_REF_CTRL"> | |
| PSU_CRL_APB_GEM2_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0058</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_GEM3_REF_CTRL"> | |
| PSU_CRL_APB_GEM3_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E005C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_USB0_BUS_REF_CTRL"> | |
| PSU_CRL_APB_USB0_BUS_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0060</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_USB3_DUAL_REF_CTRL"> | |
| PSU_CRL_APB_USB3_DUAL_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E004C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_QSPI_REF_CTRL"> | |
| PSU_CRL_APB_QSPI_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0068</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_SDIO0_REF_CTRL"> | |
| PSU_CRL_APB_SDIO0_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E006C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_SDIO1_REF_CTRL"> | |
| PSU_CRL_APB_SDIO1_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0070</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_UART0_REF_CTRL"> | |
| PSU_CRL_APB_UART0_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0074</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_UART1_REF_CTRL"> | |
| PSU_CRL_APB_UART1_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0078</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_I2C0_REF_CTRL"> | |
| PSU_CRL_APB_I2C0_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0120</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_I2C1_REF_CTRL"> | |
| PSU_CRL_APB_I2C1_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0124</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_SPI0_REF_CTRL"> | |
| PSU_CRL_APB_SPI0_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E007C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_SPI1_REF_CTRL"> | |
| PSU_CRL_APB_SPI1_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0080</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_CAN0_REF_CTRL"> | |
| PSU_CRL_APB_CAN0_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0084</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_CAN1_REF_CTRL"> | |
| PSU_CRL_APB_CAN1_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0088</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_CPU_R5_CTRL"> | |
| PSU_CRL_APB_CPU_R5_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0090</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_IOU_SWITCH_CTRL"> | |
| PSU_CRL_APB_IOU_SWITCH_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E009C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_PCAP_CTRL"> | |
| PSU_CRL_APB_PCAP_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E00A4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_LPD_SWITCH_CTRL"> | |
| PSU_CRL_APB_LPD_SWITCH_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E00A8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_LPD_LSBUS_CTRL"> | |
| PSU_CRL_APB_LPD_LSBUS_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E00AC</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_DBG_LPD_CTRL"> | |
| PSU_CRL_APB_DBG_LPD_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E00B0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_NAND_REF_CTRL"> | |
| PSU_CRL_APB_NAND_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E00B4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_ADMA_REF_CTRL"> | |
| PSU_CRL_APB_ADMA_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E00B8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_AMS_REF_CTRL"> | |
| PSU_CRL_APB_AMS_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0108</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_DLL_REF_CTRL"> | |
| PSU_CRL_APB_DLL_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0104</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_TIMESTAMP_REF_CTRL"> | |
| PSU_CRL_APB_TIMESTAMP_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0128</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_PCIE_REF_CTRL"> | |
| PSU_CRF_APB_PCIE_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A00B4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_DP_VIDEO_REF_CTRL"> | |
| PSU_CRF_APB_DP_VIDEO_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0070</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_DP_AUDIO_REF_CTRL"> | |
| PSU_CRF_APB_DP_AUDIO_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0074</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_DP_STC_REF_CTRL"> | |
| PSU_CRF_APB_DP_STC_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A007C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_ACPU_CTRL"> | |
| PSU_CRF_APB_ACPU_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0060</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_DBG_TRACE_CTRL"> | |
| PSU_CRF_APB_DBG_TRACE_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0064</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_DBG_FPD_CTRL"> | |
| PSU_CRF_APB_DBG_FPD_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0068</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_DDR_CTRL"> | |
| PSU_CRF_APB_DDR_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0080</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_GPU_REF_CTRL"> | |
| PSU_CRF_APB_GPU_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0084</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_GDMA_REF_CTRL"> | |
| PSU_CRF_APB_GDMA_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A00B8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_DPDMA_REF_CTRL"> | |
| PSU_CRF_APB_DPDMA_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A00BC</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_TOPSW_MAIN_CTRL"> | |
| PSU_CRF_APB_TOPSW_MAIN_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A00C0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_TOPSW_LSBUS_CTRL"> | |
| PSU_CRF_APB_TOPSW_LSBUS_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A00C4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_GTGREF0_REF_CTRL"> | |
| PSU_CRF_APB_GTGREF0_REF_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A00C8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRF_APB_DBG_TSTMP_CTRL"> | |
| PSU_CRF_APB_DBG_TSTMP_CTRL | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A00F8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="psu_clock_init_data">psu_clock_init_data</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFC0FF> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <H1>CLOCK CONTROL SLCR REGISTER</H1> | |
| <H2><a name="GEM0_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM0_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>GEM0_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0050</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_GEM0_REF_CTRL_RX_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>26:26</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active for the RX channel</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_GEM0_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:25</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>20000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>28</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_GEM0_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_GEM0_REF_CTRL@0XFF5E0050</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>63f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>6022800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="GEM1_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM1_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>GEM1_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0054</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_GEM1_REF_CTRL_RX_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>26:26</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active for the RX channel</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_GEM1_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:25</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>20000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>28</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_GEM1_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_GEM1_REF_CTRL@0XFF5E0054</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>63f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>6022800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="GEM2_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM2_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>GEM2_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0058</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_GEM2_REF_CTRL_RX_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>26:26</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active for the RX channel</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_GEM2_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:25</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>20000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>28</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_GEM2_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_GEM2_REF_CTRL@0XFF5E0058</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>63f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>6022800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="GEM3_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM3_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>GEM3_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E005C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>26:26</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active for the RX channel</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_GEM3_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:25</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>20000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>28</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_GEM3_REF_CTRL@0XFF5E005C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>63f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>6022800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="USB0_BUS_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)USB0_BUS_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>USB0_BUS_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0060</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:25</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3200</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_USB0_BUS_REF_CTRL@0XFF5E0060</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>23f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>2013200</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="USB3_DUAL_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)USB3_DUAL_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>USB3_DUAL_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E004C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:25</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_USB3_DUAL_REF_CTRL@0XFF5E004C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>23f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>2010800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="QSPI_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)QSPI_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>QSPI_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0068</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_QSPI_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>20000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3200</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_QSPI_REF_CTRL@0XFF5E0068</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>13f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1023200</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="SDIO0_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)SDIO0_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>SDIO0_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E006C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_SDIO0_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>20000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3200</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_SDIO0_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_SDIO0_REF_CTRL@0XFF5E006C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>13f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1023200</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="SDIO1_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)SDIO1_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>SDIO1_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0070</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>20000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3200</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_SDIO1_REF_CTRL@0XFF5E0070</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>13f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1023200</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="UART0_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)UART0_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>UART0_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0074</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_UART0_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>20000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>28</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_UART0_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_UART0_REF_CTRL@0XFF5E0074</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>13f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1022800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="UART1_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)UART1_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>UART1_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0078</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_UART1_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>20000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>28</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_UART1_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_UART1_REF_CTRL@0XFF5E0078</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>13f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1022800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="I2C0_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)I2C0_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>I2C0_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0120</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_I2C0_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>20000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>28</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_I2C0_REF_CTRL@0XFF5E0120</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>13f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1022800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="I2C1_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)I2C1_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>I2C1_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0124</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_I2C1_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>a</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>a0000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3200</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_I2C1_REF_CTRL@0XFF5E0124</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>13f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>10a3200</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="SPI0_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)SPI0_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>SPI0_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E007C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_SPI0_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>20000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>28</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_SPI0_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_SPI0_REF_CTRL@0XFF5E007C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>13f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1022800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="SPI1_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)SPI1_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>SPI1_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0080</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_SPI1_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>a</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>a0000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3200</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_SPI1_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_SPI1_REF_CTRL@0XFF5E0080</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>13f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>10a3200</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="CAN0_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)CAN0_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>CAN0_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0084</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_CAN0_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>20000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>28</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_CAN0_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_CAN0_REF_CTRL@0XFF5E0084</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>13f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1022800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="CAN1_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)CAN1_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>CAN1_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0088</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_CAN1_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>20000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>28</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_CAN1_REF_CTRL@0XFF5E0088</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>13f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1022800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="CPU_R5_CTRL">Register (<A href=#mod___slcr> slcr </A>)CPU_R5_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>CPU_R5_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0090</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_CPU_R5_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_CPU_R5_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_CPU_R5_CTRL@0XFF5E0090</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1003f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1003f02</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="IOU_SWITCH_CTRL">Register (<A href=#mod___slcr> slcr </A>)IOU_SWITCH_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>IOU_SWITCH_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E009C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>6</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>600</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_IOU_SWITCH_CTRL@0XFF5E009C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1003f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1000600</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="PCAP_CTRL">Register (<A href=#mod___slcr> slcr </A>)PCAP_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PCAP_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E00A4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_PCAP_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_PCAP_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_PCAP_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_PCAP_CTRL@0XFF5E00A4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1003f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1000800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="LPD_SWITCH_CTRL">Register (<A href=#mod___slcr> slcr </A>)LPD_SWITCH_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>LPD_SWITCH_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E00A8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>400</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_LPD_SWITCH_CTRL@0XFF5E00A8</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1003f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1000402</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="LPD_LSBUS_CTRL">Register (<A href=#mod___slcr> slcr </A>)LPD_LSBUS_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>LPD_LSBUS_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E00AC</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>14</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1400</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_LPD_LSBUS_CTRL@0XFF5E00AC</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1003f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1001402</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="DBG_LPD_CTRL">Register (<A href=#mod___slcr> slcr </A>)DBG_LPD_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>DBG_LPD_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E00B0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_DBG_LPD_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_DBG_LPD_CTRL@0XFF5E00B0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1003f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1003f00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="NAND_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)NAND_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>NAND_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E00B4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_NAND_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_NAND_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>20000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_NAND_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3200</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_NAND_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_NAND_REF_CTRL@0XFF5E00B4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>13f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1023200</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="ADMA_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)ADMA_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>ADMA_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E00B8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_ADMA_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>400</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_ADMA_REF_CTRL@0XFF5E00B8</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1003f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1000402</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="AMS_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)AMS_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>AMS_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0108</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>28</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_AMS_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_AMS_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_AMS_REF_CTRL@0XFF5E0108</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>13f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1012800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="DLL_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)DLL_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>DLL_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0104</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_DLL_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_DLL_REF_CTRL@0XFF5E0104</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="TIMESTAMP_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)TIMESTAMP_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>TIMESTAMP_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0128</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>14</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1400</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>1XX = pss_ref_clk; 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_TIMESTAMP_REF_CTRL@0XFF5E0128</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1003f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1001402</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="PCIE_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)PCIE_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PCIE_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A00B4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_PCIE_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_PCIE_REF_CTRL@0XFD1A00B4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1003f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1003f00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="DP_VIDEO_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)DP_VIDEO_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>DP_VIDEO_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0070</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>15</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>150000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3200</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = VPLL; 010 = DPLL; 011 = RPLL - might be using extra mux; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_DP_VIDEO_REF_CTRL@0XFD1A0070</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>13f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1153200</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="DP_AUDIO_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)DP_AUDIO_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>DP_AUDIO_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0074</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>20000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2a</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2a00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = VPLL; 010 = DPLL; 011 = RPLL - might be using extra mux; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_DP_AUDIO_REF_CTRL@0XFD1A0074</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>13f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1022a00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="DP_STC_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)DP_STC_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>DP_STC_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A007C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>20000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2a</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2a00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = VPLL; 010 = DPLL; 011 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_DP_STC_REF_CTRL@0XFD1A007C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>13f3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1022a00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="ACPU_CTRL">Register (<A href=#mod___slcr> slcr </A>)ACPU_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>ACPU_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0060</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_ACPU_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_ACPU_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:25</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed clock to the entire APU</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_ACPU_CTRL@0XFD1A0060</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>3003f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>3003f00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="DBG_TRACE_CTRL">Register (<A href=#mod___slcr> slcr </A>)DBG_TRACE_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>DBG_TRACE_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0064</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DBG_TRACE_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DBG_TRACE_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DBG_TRACE_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_DBG_TRACE_CTRL@0XFD1A0064</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1003f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1003f02</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="DBG_FPD_CTRL">Register (<A href=#mod___slcr> slcr </A>)DBG_FPD_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>DBG_FPD_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0068</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DBG_FPD_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_DBG_FPD_CTRL@0XFD1A0068</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1003f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1003f02</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="DDR_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>DDR_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0080</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DDR_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>a</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>a00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DDR_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_DDR_CTRL@0XFD1A0080</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>a00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="GPU_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)GPU_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>GPU_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A0084</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_GPU_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_GPU_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock. Will stop clock for both Pixel Processors below</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:25</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal for Pixel Processor. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>26:26</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal for Pixel Processor. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_GPU_REF_CTRL@0XFD1A0084</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>7003f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>7003f02</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="GDMA_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)GDMA_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>GDMA_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A00B8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>300</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_GDMA_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_GDMA_REF_CTRL@0XFD1A00B8</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1003f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1000303</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="DPDMA_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)DPDMA_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>DPDMA_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A00BC</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>300</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_DPDMA_REF_CTRL@0XFD1A00BC</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1003f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1000303</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="TOPSW_MAIN_CTRL">Register (<A href=#mod___slcr> slcr </A>)TOPSW_MAIN_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>TOPSW_MAIN_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A00C0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>300</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_TOPSW_MAIN_CTRL@0XFD1A00C0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1003f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1000303</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="TOPSW_LSBUS_CTRL">Register (<A href=#mod___slcr> slcr </A>)TOPSW_LSBUS_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>TOPSW_LSBUS_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A00C4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>14</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1400</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = APLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_TOPSW_LSBUS_CTRL@0XFD1A00C4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1003f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1001400</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="GTGREF0_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)GTGREF0_REF_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>GTGREF0_REF_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A00C8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_GTGREF0_REF_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>11</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1100</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_GTGREF0_REF_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = IOPLL; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_GTGREF0_REF_CTRL_CLKACT</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock active signal. Switch to 0 to disable the clock</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_GTGREF0_REF_CTRL@0XFD1A00C8</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1003f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1001102</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="DBG_TSTMP_CTRL">Register (<A href=#mod___slcr> slcr </A>)DBG_TSTMP_CTRL</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>DBG_TSTMP_CTRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFD1A00F8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3f00</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>6 bit divider</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRF_APB_DBG_TSTMP_CTRL@0XFD1A00F8</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>3f07</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>802</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>This register controls this reference clock</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| </TABLE> | |
| <P> | |
| <H2><a name="psu_ddr_init_data_3_0">psu_ddr_init_data_3_0</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFC0FF> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="psu_ddr_init_data_3_0">psu_ddr_init_data_3_0</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFC0FF> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="psu_mio_init_data">psu_mio_init_data</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFC0FF> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_0"> | |
| PSU_IOU_SLCR_MIO_PIN_0 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 0 peripheral interface mapping. S</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_1"> | |
| PSU_IOU_SLCR_MIO_PIN_1 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180004</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 1 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_2"> | |
| PSU_IOU_SLCR_MIO_PIN_2 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180008</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 2 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_3"> | |
| PSU_IOU_SLCR_MIO_PIN_3 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18000C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 3 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_4"> | |
| PSU_IOU_SLCR_MIO_PIN_4 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180010</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 4 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_5"> | |
| PSU_IOU_SLCR_MIO_PIN_5 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180014</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 5 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_6"> | |
| PSU_IOU_SLCR_MIO_PIN_6 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180018</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 6 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_7"> | |
| PSU_IOU_SLCR_MIO_PIN_7 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18001C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 7 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_8"> | |
| PSU_IOU_SLCR_MIO_PIN_8 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 8 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_9"> | |
| PSU_IOU_SLCR_MIO_PIN_9 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180024</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 9 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_10"> | |
| PSU_IOU_SLCR_MIO_PIN_10 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180028</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 10 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_11"> | |
| PSU_IOU_SLCR_MIO_PIN_11 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18002C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 11 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_12"> | |
| PSU_IOU_SLCR_MIO_PIN_12 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180030</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 12 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_13"> | |
| PSU_IOU_SLCR_MIO_PIN_13 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180034</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 13 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_14"> | |
| PSU_IOU_SLCR_MIO_PIN_14 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180038</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 14 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_15"> | |
| PSU_IOU_SLCR_MIO_PIN_15 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18003C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 15 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_16"> | |
| PSU_IOU_SLCR_MIO_PIN_16 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180040</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 16 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_17"> | |
| PSU_IOU_SLCR_MIO_PIN_17 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180044</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 17 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_18"> | |
| PSU_IOU_SLCR_MIO_PIN_18 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180048</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 18 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_19"> | |
| PSU_IOU_SLCR_MIO_PIN_19 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18004C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 19 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_20"> | |
| PSU_IOU_SLCR_MIO_PIN_20 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180050</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 20 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_21"> | |
| PSU_IOU_SLCR_MIO_PIN_21 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180054</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 21 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_22"> | |
| PSU_IOU_SLCR_MIO_PIN_22 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180058</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 22 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_23"> | |
| PSU_IOU_SLCR_MIO_PIN_23 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18005C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 23 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_24"> | |
| PSU_IOU_SLCR_MIO_PIN_24 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180060</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 24 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_25"> | |
| PSU_IOU_SLCR_MIO_PIN_25 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180064</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 25 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_26"> | |
| PSU_IOU_SLCR_MIO_PIN_26 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180068</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 26 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_27"> | |
| PSU_IOU_SLCR_MIO_PIN_27 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18006C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 27 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_28"> | |
| PSU_IOU_SLCR_MIO_PIN_28 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180070</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 28 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_29"> | |
| PSU_IOU_SLCR_MIO_PIN_29 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180074</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 29 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_30"> | |
| PSU_IOU_SLCR_MIO_PIN_30 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180078</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 30 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_31"> | |
| PSU_IOU_SLCR_MIO_PIN_31 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18007C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 31 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_32"> | |
| PSU_IOU_SLCR_MIO_PIN_32 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180080</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 32 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_33"> | |
| PSU_IOU_SLCR_MIO_PIN_33 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180084</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 33 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_34"> | |
| PSU_IOU_SLCR_MIO_PIN_34 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180088</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 34 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_35"> | |
| PSU_IOU_SLCR_MIO_PIN_35 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18008C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 35 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_36"> | |
| PSU_IOU_SLCR_MIO_PIN_36 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180090</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 36 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_37"> | |
| PSU_IOU_SLCR_MIO_PIN_37 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180094</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 37 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_38"> | |
| PSU_IOU_SLCR_MIO_PIN_38 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180098</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 38 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_39"> | |
| PSU_IOU_SLCR_MIO_PIN_39 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18009C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 39 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_40"> | |
| PSU_IOU_SLCR_MIO_PIN_40 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800A0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 40 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_41"> | |
| PSU_IOU_SLCR_MIO_PIN_41 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800A4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 41 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_42"> | |
| PSU_IOU_SLCR_MIO_PIN_42 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800A8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 42 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_43"> | |
| PSU_IOU_SLCR_MIO_PIN_43 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800AC</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 43 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_44"> | |
| PSU_IOU_SLCR_MIO_PIN_44 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800B0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 44 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_45"> | |
| PSU_IOU_SLCR_MIO_PIN_45 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800B4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 45 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_46"> | |
| PSU_IOU_SLCR_MIO_PIN_46 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800B8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 46 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_47"> | |
| PSU_IOU_SLCR_MIO_PIN_47 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800BC</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 47 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_48"> | |
| PSU_IOU_SLCR_MIO_PIN_48 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800C0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 48 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_49"> | |
| PSU_IOU_SLCR_MIO_PIN_49 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800C4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 49 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_50"> | |
| PSU_IOU_SLCR_MIO_PIN_50 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800C8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 50 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_51"> | |
| PSU_IOU_SLCR_MIO_PIN_51 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800CC</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 51 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_52"> | |
| PSU_IOU_SLCR_MIO_PIN_52 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800D0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 52 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_53"> | |
| PSU_IOU_SLCR_MIO_PIN_53 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800D4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 53 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_54"> | |
| PSU_IOU_SLCR_MIO_PIN_54 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800D8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 54 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_55"> | |
| PSU_IOU_SLCR_MIO_PIN_55 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800DC</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 55 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_56"> | |
| PSU_IOU_SLCR_MIO_PIN_56 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800E0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 56 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_57"> | |
| PSU_IOU_SLCR_MIO_PIN_57 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800E4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 57 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_58"> | |
| PSU_IOU_SLCR_MIO_PIN_58 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800E8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 58 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_59"> | |
| PSU_IOU_SLCR_MIO_PIN_59 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800EC</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 59 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_60"> | |
| PSU_IOU_SLCR_MIO_PIN_60 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800F0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 60 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_61"> | |
| PSU_IOU_SLCR_MIO_PIN_61 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800F4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 61 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_62"> | |
| PSU_IOU_SLCR_MIO_PIN_62 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800F8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 62 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_63"> | |
| PSU_IOU_SLCR_MIO_PIN_63 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800FC</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 63 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_64"> | |
| PSU_IOU_SLCR_MIO_PIN_64 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180100</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 64 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_65"> | |
| PSU_IOU_SLCR_MIO_PIN_65 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180104</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 65 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_66"> | |
| PSU_IOU_SLCR_MIO_PIN_66 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180108</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 66 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_67"> | |
| PSU_IOU_SLCR_MIO_PIN_67 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18010C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 67 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_68"> | |
| PSU_IOU_SLCR_MIO_PIN_68 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180110</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 68 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_69"> | |
| PSU_IOU_SLCR_MIO_PIN_69 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180114</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 69 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_70"> | |
| PSU_IOU_SLCR_MIO_PIN_70 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180118</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 70 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_71"> | |
| PSU_IOU_SLCR_MIO_PIN_71 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18011C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 71 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_72"> | |
| PSU_IOU_SLCR_MIO_PIN_72 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180120</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 72 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_73"> | |
| PSU_IOU_SLCR_MIO_PIN_73 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180124</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 73 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_74"> | |
| PSU_IOU_SLCR_MIO_PIN_74 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180128</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 74 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_75"> | |
| PSU_IOU_SLCR_MIO_PIN_75 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18012C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 75 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_76"> | |
| PSU_IOU_SLCR_MIO_PIN_76 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180130</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 76 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_PIN_77"> | |
| PSU_IOU_SLCR_MIO_PIN_77 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180134</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Configures MIO Pin 77 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_MST_TRI0"> | |
| PSU_IOU_SLCR_MIO_MST_TRI0 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180204</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>MIO pin Tri-state Enables, 31:0</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_MST_TRI1"> | |
| PSU_IOU_SLCR_MIO_MST_TRI1 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180208</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>MIO pin Tri-state Enables, 63:32</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_MST_TRI2"> | |
| PSU_IOU_SLCR_MIO_MST_TRI2 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18020C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>MIO pin Tri-state Enables, 77:64</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_MIO_LOOPBACK"> | |
| PSU_IOU_SLCR_MIO_LOOPBACK | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180200</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Loopback function within MIO</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="psu_mio_init_data">psu_mio_init_data</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFC0FF> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <H1>MIO PROGRAMMING</H1> | |
| <H2><a name="MIO_PIN_0">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_0</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_0_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_0_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_0_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0]- (Test Scan Port) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_0_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_clk- (Trace Port Clock)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_0@0XFF180000</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 0 peripheral interface mapping. S</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_1">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_1</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180004</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_1_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_1_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_1_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1]- (Test Scan Port) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_1_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control Signal)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_1@0XFF180004</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 1 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_2">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_2</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180008</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_2_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_2_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_2_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2]- (Test Scan Port) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_2_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_2@0XFF180008</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 2 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_3">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_3</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_3</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18000C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_3_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_3_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_3_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3]- (Test Scan Port) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_3_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[1]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_3@0XFF18000C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 3 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_4">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_4</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180010</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_4_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_4_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_4_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4]- (Test Scan Port) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_4_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[2]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_4@0XFF180010</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 4 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_5">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_5</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_5</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180014</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_5_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_5_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_5_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5]- (Test Scan Port) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_5_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[3]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_5@0XFF180014</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 5 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_6">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_6</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_6</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180018</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_6_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_6_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_6_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6]- (Test Scan Port) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_6_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_6@0XFF180018</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 6 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_7">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_7</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_7</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18001C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_7_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_7_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_7_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7]- (Test Scan Port) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_7_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_7@0XFF18001C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 7 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_8">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_8</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_8</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180020</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_8_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_8_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_8_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8]- (Test Scan Port) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_8_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_8@0XFF180020</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 8 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_9">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_9</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_9</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180024</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_9_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_9_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_9_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9]- (Test Scan Port) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_9_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_9@0XFF180024</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 9 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_10">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_10</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_10</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180028</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_10_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_10_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_10_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[10]- (Test Scan Port) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_10_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[8]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_10@0XFF180028</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 10 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_11">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_11</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_11</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18002C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_11_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_11_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_11_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[11]- (Test Scan Port) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_11_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[9]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_11@0XFF18002C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 11 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_12">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_12</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_12</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180030</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_12_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_12_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_12_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[12]- (Test Scan Port) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_12_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[10]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_12@0XFF180030</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 12 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_13">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_13</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_13</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180034</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_13_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_13_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_13_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_13_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_13@0XFF180034</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 13 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_14">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_14</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_14</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180038</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_14_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_14_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_14_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_14_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_14@0XFF180038</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 14 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_15">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_15</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_15</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18003C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_15_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_15_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_15_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_15_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_15@0XFF18003C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 15 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_16">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_16</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_16</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180040</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_16_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_16_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_16_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_16_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[14]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_16@0XFF180040</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 16 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_17">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_17</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_17</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180044</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_17_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_17_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_17_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_17_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[15]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_17@0XFF180044</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 17 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_18">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_18</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_18</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180048</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_18_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_18_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_18_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_18_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_18@0XFF180048</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 18 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_19">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_19</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_19</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18004C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_19_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_19_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_19_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_19_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_19@0XFF18004C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 19 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_20">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_20</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_20</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180050</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_20_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_20_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_20_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_20_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_20@0XFF180050</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 20 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_21">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_21</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_21</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180054</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_21_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_21_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_21_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_21_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_21@0XFF180054</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 21 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_22">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_22</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_22</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180058</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_22_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_22_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_22_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_22_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_22@0XFF180058</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 22 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_23">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_23</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_23</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18005C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_23_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_23_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_23_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_23_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_23@0XFF18005C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 23 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_24">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_24</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_24</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180060</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_24_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_24_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_24_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_24_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_24@0XFF180060</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 24 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_25">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_25</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_25</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180064</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_25_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_25_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_25_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input, test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_25_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_25@0XFF180064</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 25 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_26">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_26</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_26</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180068</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_26_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_26_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_26_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_26_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_26@0XFF180068</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 26 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_27">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_27</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_27</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18006C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_27_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_27_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_27_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_27_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_27@0XFF18006C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 27 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_28">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_28</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_28</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180070</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_28_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_28_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_28_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_28_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_28@0XFF180070</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 28 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_29">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_29</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_29</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180074</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_29_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_29_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_29_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_29_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>80</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_29@0XFF180074</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>80</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 29 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_30">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_30</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_30</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180078</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_30_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_30_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_30_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_30_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[8]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_30@0XFF180078</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 30 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_31">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_31</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_31</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18007C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_31_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_31_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_31_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_31_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[9]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_31@0XFF18007C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 31 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_32">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_32</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_32</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180080</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_32_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_32_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_32_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_32_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[10]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_32@0XFF180080</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 32 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_33">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_33</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_33</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180084</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_33_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_33_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_33_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_33_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_33@0XFF180084</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 33 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_34">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_34</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_34</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180088</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_34_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_34_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_34_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test Scan Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_34_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_34@0XFF180088</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 34 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_35">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_35</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_35</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18008C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_35_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_35_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_35_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test Scan Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_35_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>80</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_35@0XFF18008C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>80</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 35 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_36">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_36</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_36</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180090</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_36_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_36_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_36_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test Scan Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_36_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[14]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_36@0XFF180090</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 36 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_37">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_37</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_37</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180094</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_37_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_37_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_37_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test Scan Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_37_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[15]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_37@0XFF180094</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 37 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_38">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_38</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_38</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180098</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_38_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_38_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_38_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_38_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- (Trace Port Clock)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_38@0XFF180098</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 38 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_39">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_39</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_39</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18009C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_39_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_39_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_39_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_39_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port Control Signal)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_39@0XFF18009C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 39 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_40">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_40</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_40</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800A0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_40_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_40_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_40_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_40_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_40@0XFF1800A0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 40 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_41">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_41</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_41</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800A4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_41_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_41_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_41_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_41_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[1]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_41@0XFF1800A4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 41 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_42">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_42</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_42</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800A8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_42_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_42_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_42_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_42_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[2]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_42@0XFF1800A8</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 42 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_43">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_43</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_43</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800AC</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_43_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_43_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_43_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_43_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[3]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_43@0XFF1800AC</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 43 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_44">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_44</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_44</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800B0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_44_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_44_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_44_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_44_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_44@0XFF1800B0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 44 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_45">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_45</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_45</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800B4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_45_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_45_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_45_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_45_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_45@0XFF1800B4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 45 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_46">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_46</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_46</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800B8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_46_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_46_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_46_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_46_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_46@0XFF1800B8</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 46 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_47">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_47</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_47</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800BC</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_47_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_47_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_47_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_47_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_47@0XFF1800BC</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 47 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_48">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_48</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_48</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800C0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_48_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_48_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_48_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_48_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_48@0XFF1800C0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 48 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_49">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_49</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_49</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800C4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_49_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_49_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_49_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_49_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_49@0XFF1800C4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 49 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_50">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_50</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_50</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800C8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_50_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_50_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_50_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_50_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_50@0XFF1800C8</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 50 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_51">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_51</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_51</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800CC</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_51_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_51_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_51_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_51_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_51@0XFF1800CC</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 51 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_52">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_52</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_52</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800D0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_52_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_52_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_52_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_52_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_clk- (Trace Port Clock)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_52@0XFF1800D0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 52 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_53">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_53</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_53</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800D4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_53_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_53_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_53_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_53_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control Signal)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_53@0XFF1800D4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 53 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_54">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_54</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_54</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800D8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_54_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_54_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_54_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_54_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_54@0XFF1800D8</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 54 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_55">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_55</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_55</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800DC</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_55_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_55_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_55_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_55_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[1]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_55@0XFF1800DC</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 55 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_56">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_56</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_56</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800E0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_56_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_56_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_56_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_56_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[2]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_56@0XFF1800E0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 56 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_57">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_57</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_57</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800E4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_57_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_57_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_57_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_57_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[3]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_57@0XFF1800E4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 57 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_58">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_58</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_58</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800E8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_58_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_58_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_58_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_58_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_58@0XFF1800E8</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 58 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_59">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_59</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_59</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800EC</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_59_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_59_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_59_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_59_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_59@0XFF1800EC</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 59 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_60">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_60</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_60</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800F0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_60_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_60_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_60_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_60_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_60@0XFF1800F0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 60 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_61">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_61</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_61</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800F4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_61_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_61_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_61_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_61_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_61@0XFF1800F4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 61 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_62">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_62</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_62</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800F8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_62_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_62_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_62_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_62_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[8]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_62@0XFF1800F8</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 62 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_63">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_63</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_63</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF1800FC</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_63_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_63_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_63_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_63_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[9]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_63@0XFF1800FC</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 63 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_64">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_64</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_64</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180100</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_64_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_64_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_64_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_64_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[10]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_64@0XFF180100</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 64 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_65">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_65</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_65</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180104</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_65_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_65_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_65_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_65_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_65@0XFF180104</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 65 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_66">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_66</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_66</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180108</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_66_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_66_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_66_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not Used 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_66_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_66@0XFF180108</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 66 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_67">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_67</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_67</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18010C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_67_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_67_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_67_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= Not Used 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_67_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_67@0XFF18010C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 67 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_68">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_68</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_68</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180110</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_68_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_68_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_68_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= Not Used 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_68_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[14]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_68@0XFF180110</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 68 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_69">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_69</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_69</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180114</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_69_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_69_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_69_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_69_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[15]- (Trace Port Databus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_69@0XFF180114</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 69 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_70">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_70</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_70</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180118</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_70_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_70_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_70_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_70_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_70@0XFF180118</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 70 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_71">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_71</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_71</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18011C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_71_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_71_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_71_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_71_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_71@0XFF18011C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 71 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_72">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_72</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_72</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180120</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_72_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_72_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_72_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_72_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_72@0XFF180120</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 72 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_73">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_73</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_73</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180124</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_73_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_73_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_73_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_73_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_73@0XFF180124</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 73 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_74">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_74</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_74</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180128</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_74_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_74_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_74_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_74_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_74@0XFF180128</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 74 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_75">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_75</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_75</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18012C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_75_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_75_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_75_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_75_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_75@0XFF18012C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 75 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_76">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_76</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_76</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180130</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_76_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_76_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_76_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_76_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_76@0XFF180130</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>8</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 76 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_PIN_77">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_77</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_PIN_77</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180134</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_77_L0_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_77_L1_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_77_L2_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_PIN_77_L3_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>e0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_out- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_PIN_77@0XFF180134</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>fe</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Configures MIO Pin 77 peripheral interface mapping</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_MST_TRI0">Register (<A href=#mod___slcr> slcr </A>)MIO_MST_TRI0</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_MST_TRI0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180204</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 0, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 1, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 2, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 3, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>10</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 4, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>5:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>20</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 5, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>6:6</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 6, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 7, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>100</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 8, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:9</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>200</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 9, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10:10</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>400</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>400</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 10, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>11:11</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>800</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>800</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 11, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>12:12</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 12, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:13</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 13, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>14:14</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 14, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>15:15</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 15, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>16:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>10000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 16, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>17:17</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>20000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 17, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>18:18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 18, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>19:19</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 19, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>20:20</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>100000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 20, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:21</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>200000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 21, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>22:22</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>400000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 22, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>23:23</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>800000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 23, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 24, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:25</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 25, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>26:26</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 26, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>27:27</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 27, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>28:28</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>10000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 28, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>29:29</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>20000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 29, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 30, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 31, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI0@0XFF180204</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>ffffffff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>c00</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>MIO pin Tri-state Enables, 31:0</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_MST_TRI1">Register (<A href=#mod___slcr> slcr </A>)MIO_MST_TRI1</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_MST_TRI1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180208</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 32, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 33, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 34, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 35, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>10</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 36, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>5:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>20</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 37, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>6:6</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 38, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 39, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>100</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 40, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:9</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>200</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 41, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10:10</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>400</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 42, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>11:11</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>800</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 43, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>12:12</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 44, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:13</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 45, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>14:14</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 46, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>15:15</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 47, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>16:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>10000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 48, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>17:17</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>20000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 49, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>18:18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 50, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>19:19</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 51, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>20:20</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>100000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>100000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 52, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>21:21</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>200000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>200000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 53, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>22:22</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>400000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 54, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>23:23</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>800000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>800000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 55, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 56, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:25</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 57, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>26:26</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 58, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>27:27</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 59, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>28:28</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>10000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 60, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>29:29</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>20000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 61, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 62, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 63, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI1@0XFF180208</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>ffffffff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>b00000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>MIO pin Tri-state Enables, 63:32</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MIO_MST_TRI2">Register (<A href=#mod___slcr> slcr </A>)MIO_MST_TRI2</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_MST_TRI2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF18020C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 64, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 65, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 66, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 67, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>10</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 68, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>5:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>20</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 69, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>6:6</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 70, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 71, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>100</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 72, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:9</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>200</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 73, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10:10</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>400</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 74, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>11:11</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>800</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 75, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>12:12</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 76, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:13</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master Tri-state Enable for pin 77, active high</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_MST_TRI2@0XFF18020C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>3fff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>1002</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>MIO pin Tri-state Enables, 77:64</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>LOOPBACK</H1> | |
| <H2><a name="MIO_LOOPBACK">Register (<A href=#mod___slcr> slcr </A>)MIO_LOOPBACK</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MIO_LOOPBACK</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180200</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_MIO_LOOPBACK@0XFF180200</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>f</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Loopback function within MIO</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| </TABLE> | |
| <P> | |
| <H2><a name="psu_peripherals_init_data_3_0">psu_peripherals_init_data_3_0</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFC0FF> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_RST_LPD_IOU0"> | |
| PSU_CRL_APB_RST_LPD_IOU0 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0230</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Software controlled reset for the GEMs</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_RST_LPD_IOU2"> | |
| PSU_CRL_APB_RST_LPD_IOU2 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0238</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_RST_LPD_IOU2"> | |
| PSU_CRL_APB_RST_LPD_IOU2 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0238</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_RST_LPD_TOP"> | |
| PSU_CRL_APB_RST_LPD_TOP | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E023C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Software control register for the LPD block.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_RST_LPD_IOU2"> | |
| PSU_CRL_APB_RST_LPD_IOU2 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0238</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_CTRL_REG_SD"> | |
| PSU_IOU_SLCR_CTRL_REG_SD | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180310</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>SD eMMC selection</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_IOU_SLCR_SD_CONFIG_REG2"> | |
| PSU_IOU_SLCR_SD_CONFIG_REG2 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180320</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>SD Config Register 2</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_RST_LPD_IOU2"> | |
| PSU_CRL_APB_RST_LPD_IOU2 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0238</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_RST_LPD_IOU2"> | |
| PSU_CRL_APB_RST_LPD_IOU2 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0238</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_RST_LPD_IOU2"> | |
| PSU_CRL_APB_RST_LPD_IOU2 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0238</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_RST_LPD_IOU2"> | |
| PSU_CRL_APB_RST_LPD_IOU2 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0238</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CRL_APB_RST_LPD_IOU2"> | |
| PSU_CRL_APB_RST_LPD_IOU2 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0238</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_UART0_BAUD_RATE_DIVIDER_REG0"> | |
| PSU_UART0_BAUD_RATE_DIVIDER_REG0 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF000034</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Baud Rate Divider Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_UART0_BAUD_RATE_GEN_REG0"> | |
| PSU_UART0_BAUD_RATE_GEN_REG0 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF000018</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Baud Rate Generator Register.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_UART0_CONTROL_REG0"> | |
| PSU_UART0_CONTROL_REG0 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>UART Control Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_UART0_MODE_REG0"> | |
| PSU_UART0_MODE_REG0 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF000004</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>UART Mode Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_UART1_BAUD_RATE_DIVIDER_REG0"> | |
| PSU_UART1_BAUD_RATE_DIVIDER_REG0 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF010034</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Baud Rate Divider Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_UART1_BAUD_RATE_GEN_REG0"> | |
| PSU_UART1_BAUD_RATE_GEN_REG0 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF010018</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Baud Rate Generator Register.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_UART1_CONTROL_REG0"> | |
| PSU_UART1_CONTROL_REG0 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF010000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>UART Control Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_UART1_MODE_REG0"> | |
| PSU_UART1_MODE_REG0 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF010004</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>UART Mode Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_LPD_SLCR_SECURE_SLCR_ADMA"> | |
| PSU_LPD_SLCR_SECURE_SLCR_ADMA | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF4B0024</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>RPU TrustZone settings</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_CSU_TAMPER_STATUS"> | |
| PSU_CSU_TAMPER_STATUS | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFFCA5000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Tamper Response Status</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="psu_peripherals_init_data_3_0">psu_peripherals_init_data_3_0</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFC0FF> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <H1>ENET</H1> | |
| <H2><a name="RST_LPD_IOU0">Register (<A href=#mod___slcr> slcr </A>)RST_LPD_IOU0</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>RST_LPD_IOU0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0230</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_IOU0_GEM0_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>GEM 0 reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_IOU0_GEM1_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>GEM 1 reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_IOU0_GEM2_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>GEM 2 reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>GEM 3 reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_RST_LPD_IOU0@0XFF5E0230</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>f</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Software controlled reset for the GEMs</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>QSPI</H1> | |
| <H2><a name="RST_LPD_IOU2">Register (<A href=#mod___slcr> slcr </A>)RST_LPD_IOU2</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>RST_LPD_IOU2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0238</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Block level reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>NAND</H1> | |
| <H2><a name="RST_LPD_IOU2">Register (<A href=#mod___slcr> slcr </A>)RST_LPD_IOU2</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>RST_LPD_IOU2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0238</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2_NAND_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>16:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>10000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Block level reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>10000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>USB</H1> | |
| <H2><a name="RST_LPD_TOP">Register (<A href=#mod___slcr> slcr </A>)RST_LPD_TOP</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>RST_LPD_TOP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E023C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10:10</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>400</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>USB 0 reset for control registers</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>100</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>USB 0 sleep circuit reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>6:6</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>USB 0 reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_RST_LPD_TOP@0XFF5E023C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>540</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Software control register for the LPD block.</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>SD</H1> | |
| <H2><a name="RST_LPD_IOU2">Register (<A href=#mod___slcr> slcr </A>)RST_LPD_IOU2</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>RST_LPD_IOU2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0238</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2_SDIO0_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>5:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>20</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Block level reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>6:6</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Block level reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>60</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="CTRL_REG_SD">Register (<A href=#mod___slcr> slcr </A>)CTRL_REG_SD</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>CTRL_REG_SD</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180310</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>SD or eMMC selection on SDIO0 0: SD enabled 1: eMMC enabled</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>15:15</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_CTRL_REG_SD@0XFF180310</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>8001</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>SD eMMC selection</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="SD_CONFIG_REG2">Register (<A href=#mod___slcr> slcr </A>)SD_CONFIG_REG2</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>SD_CONFIG_REG2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF180320</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:12</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>29:28</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>30000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:9</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>200</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>200</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>1.8V Support 1: 1.8V supported 0: 1.8V not supported support</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>100</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>3.0V Support 1: 3.0V supported 0: 3.0V not supported support</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>80</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>3.3V Support 1: 3.3V supported 0: 3.3V not supported support</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:25</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>1.8V Support 1: 1.8V supported 0: 1.8V not supported support</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>24:24</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>3.0V Support 1: 3.0V supported 0: 3.0V not supported support</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>23:23</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>800000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>800000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>3.3V Support 1: 3.3V supported 0: 3.3V not supported support</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_IOU_SLCR_SD_CONFIG_REG2@0XFF180320</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>33803380</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>2800280</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>SD Config Register 2</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>CAN</H1> | |
| <H2><a name="RST_LPD_IOU2">Register (<A href=#mod___slcr> slcr </A>)RST_LPD_IOU2</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>RST_LPD_IOU2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0238</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2_CAN0_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Block level reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>100</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Block level reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>180</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>I2C</H1> | |
| <H2><a name="RST_LPD_IOU2">Register (<A href=#mod___slcr> slcr </A>)RST_LPD_IOU2</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>RST_LPD_IOU2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0238</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:9</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>200</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Block level reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10:10</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>400</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Block level reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>600</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>SWDT</H1> | |
| <H1>SPI</H1> | |
| <H2><a name="RST_LPD_IOU2">Register (<A href=#mod___slcr> slcr </A>)RST_LPD_IOU2</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>RST_LPD_IOU2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0238</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2_SPI0_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Block level reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2_SPI1_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>10</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Block level reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>18</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>TTC</H1> | |
| <H2><a name="RST_LPD_IOU2">Register (<A href=#mod___slcr> slcr </A>)RST_LPD_IOU2</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>RST_LPD_IOU2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0238</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>11:11</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>800</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Block level reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>12:12</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Block level reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>13:13</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Block level reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>14:14</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Block level reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>7800</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>UART</H1> | |
| <H2><a name="RST_LPD_IOU2">Register (<A href=#mod___slcr> slcr </A>)RST_LPD_IOU2</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>RST_LPD_IOU2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF5E0238</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Block level reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Block level reset</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>6</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="Baud_rate_divider_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_divider_reg0</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>Baud_rate_divider_reg0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF000034</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_UART0_BAUD_RATE_DIVIDER_REG0@0XFF000034</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Baud Rate Divider Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="Baud_rate_gen_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_gen_reg0</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>Baud_rate_gen_reg0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF000018</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART0_BAUD_RATE_GEN_REG0_CD</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>15:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>ffff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_UART0_BAUD_RATE_GEN_REG0@0XFF000018</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>ffff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Baud Rate Generator Register.</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="Control_reg0">Register (<A href=#mod___slcr> slcr </A>)Control_reg0</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>Control_reg0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART0_CONTROL_REG0_STPBRK</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>100</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART0_CONTROL_REG0_STTBRK</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART0_CONTROL_REG0_RSTTO</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>6:6</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART0_CONTROL_REG0_TXDIS</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>5:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>20</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Transmit disable: 0: enable transmitter 1: disable transmitter</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART0_CONTROL_REG0_TXEN</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>10</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART0_CONTROL_REG0_RXDIS</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Receive disable: 0: enable 1: disable, regardless of the value of RXEN</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART0_CONTROL_REG0_RXEN</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART0_CONTROL_REG0_TXRES</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART0_CONTROL_REG0_RXRES</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_UART0_CONTROL_REG0@0XFF000000</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>17</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>UART Control Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="mode_reg0">Register (<A href=#mod___slcr> slcr </A>)mode_reg0</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>mode_reg0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF000004</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART0_MODE_REG0_CHMODE</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>300</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART0_MODE_REG0_NBSTOP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:6</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>c0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART0_MODE_REG0_PAR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>5:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>38</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>20</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART0_MODE_REG0_CHRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>6</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART0_MODE_REG0_CLKS</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_UART0_MODE_REG0@0XFF000004</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>20</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>UART Mode Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="Baud_rate_divider_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_divider_reg0</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>Baud_rate_divider_reg0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF010034</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_UART1_BAUD_RATE_DIVIDER_REG0@0XFF010034</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Baud Rate Divider Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="Baud_rate_gen_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_gen_reg0</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>Baud_rate_gen_reg0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF010018</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART1_BAUD_RATE_GEN_REG0_CD</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>15:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>ffff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_UART1_BAUD_RATE_GEN_REG0@0XFF010018</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>ffff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Baud Rate Generator Register.</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="Control_reg0">Register (<A href=#mod___slcr> slcr </A>)Control_reg0</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>Control_reg0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF010000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART1_CONTROL_REG0_STPBRK</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>100</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART1_CONTROL_REG0_STTBRK</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART1_CONTROL_REG0_RSTTO</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>6:6</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART1_CONTROL_REG0_TXDIS</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>5:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>20</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Transmit disable: 0: enable transmitter 1: disable transmitter</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART1_CONTROL_REG0_TXEN</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>10</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART1_CONTROL_REG0_RXDIS</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Receive disable: 0: enable 1: disable, regardless of the value of RXEN</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART1_CONTROL_REG0_RXEN</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART1_CONTROL_REG0_TXRES</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART1_CONTROL_REG0_RXRES</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed.</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_UART1_CONTROL_REG0@0XFF010000</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>17</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>UART Control Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="mode_reg0">Register (<A href=#mod___slcr> slcr </A>)mode_reg0</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>mode_reg0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF010004</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART1_MODE_REG0_CHMODE</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>300</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART1_MODE_REG0_NBSTOP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:6</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>c0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART1_MODE_REG0_PAR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>5:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>38</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>20</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART1_MODE_REG0_CHRL</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>6</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_UART1_MODE_REG0_CLKS</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_UART1_MODE_REG0@0XFF010004</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>20</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>UART Mode Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>GPIO</H1> | |
| <H1>ADMA TZ</H1> | |
| <H2><a name="slcr_adma">Register (<A href=#mod___slcr> slcr </A>)slcr_adma</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>slcr_adma</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF4B0024</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>ff</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>ff</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>TrustZone Classification for ADMA</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_LPD_SLCR_SECURE_SLCR_ADMA@0XFF4B0024</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>ff</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>RPU TrustZone settings</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>CSU TAMPERING</H1> | |
| <H1>CSU TAMPER STATUS</H1> | |
| <H2><a name="tamper_status">Register (<A href=#mod___slcr> slcr </A>)tamper_status</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>tamper_status</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFFCA5000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CSU_TAMPER_STATUS_TAMPER_0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>CSU regsiter</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CSU_TAMPER_STATUS_TAMPER_1</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>1:1</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>External MIO</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CSU_TAMPER_STATUS_TAMPER_2</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>2:2</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>JTAG toggle detect</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CSU_TAMPER_STATUS_TAMPER_3</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>3:3</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>PL SEU error</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CSU_TAMPER_STATUS_TAMPER_4</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>4:4</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>10</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>AMS over temperature alarm for LPD</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CSU_TAMPER_STATUS_TAMPER_5</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>5:5</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>20</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>AMS over temperature alarm for APU</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CSU_TAMPER_STATUS_TAMPER_6</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>6:6</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>AMS voltage alarm for VCCPINT_FPD</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CSU_TAMPER_STATUS_TAMPER_7</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>7:7</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>AMS voltage alarm for VCCPINT_LPD</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CSU_TAMPER_STATUS_TAMPER_8</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>8:8</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>100</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>AMS voltage alarm for VCCPAUX</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CSU_TAMPER_STATUS_TAMPER_9</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:9</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>200</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>AMS voltage alarm for DDRPHY</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CSU_TAMPER_STATUS_TAMPER_10</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>10:10</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>400</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>AMS voltage alarm for PSIO bank 0/1/2</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CSU_TAMPER_STATUS_TAMPER_11</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>11:11</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>800</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>AMS voltage alarm for PSIO bank 3 (dedicated pins)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_CSU_TAMPER_STATUS_TAMPER_12</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>12:12</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>1000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>AMS voltaage alarm for GT</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_CSU_TAMPER_STATUS@0XFFCA5000</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>1fff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Tamper Response Status</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>CSU TAMPER RESPONSE</H1> | |
| </TABLE> | |
| <P> | |
| <H2><a name="psu_post_config">psu_post_config</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFC0FF> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="psu_post_config">psu_post_config</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFC0FF> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="psu_peripherals_powerdwn_data_3_0">psu_peripherals_powerdwn_data_3_0</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFC0FF> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="psu_peripherals_powerdwn_data_3_0">psu_peripherals_powerdwn_data_3_0</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFC0FF> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <H1>POWER DOWN REQUEST INTERRUPT ENABLE</H1> | |
| <H1>POWER DOWN TRIGGER</H1> | |
| </TABLE> | |
| <P> | |
| <H2><a name="psu_security_data_3_0">psu_security_data_3_0</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFC0FF> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_LPD_XPPU_CFG_MASTER_ID00"> | |
| PSU_LPD_XPPU_CFG_MASTER_ID00 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980100</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master ID 00 Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_LPD_XPPU_CFG_MASTER_ID01"> | |
| PSU_LPD_XPPU_CFG_MASTER_ID01 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980104</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master ID 01 Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_LPD_XPPU_CFG_MASTER_ID02"> | |
| PSU_LPD_XPPU_CFG_MASTER_ID02 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980108</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master ID 02 Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_LPD_XPPU_CFG_MASTER_ID03"> | |
| PSU_LPD_XPPU_CFG_MASTER_ID03 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF98010C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master ID 03 Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_LPD_XPPU_CFG_MASTER_ID04"> | |
| PSU_LPD_XPPU_CFG_MASTER_ID04 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980110</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master ID 04 Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_LPD_XPPU_CFG_MASTER_ID05"> | |
| PSU_LPD_XPPU_CFG_MASTER_ID05 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980114</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master ID 05 Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_LPD_XPPU_CFG_MASTER_ID06"> | |
| PSU_LPD_XPPU_CFG_MASTER_ID06 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980118</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master ID 06 Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_LPD_XPPU_CFG_MASTER_ID07"> | |
| PSU_LPD_XPPU_CFG_MASTER_ID07 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF98011C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master ID 07 Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_LPD_XPPU_CFG_MASTER_ID08"> | |
| PSU_LPD_XPPU_CFG_MASTER_ID08 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980120</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master ID 08 Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_LPD_XPPU_CFG_MASTER_ID09"> | |
| PSU_LPD_XPPU_CFG_MASTER_ID09 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980124</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master ID 09 Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_LPD_XPPU_CFG_MASTER_ID10"> | |
| PSU_LPD_XPPU_CFG_MASTER_ID10 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980128</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master ID 10 Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_LPD_XPPU_CFG_MASTER_ID11"> | |
| PSU_LPD_XPPU_CFG_MASTER_ID11 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF98012C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master ID 11 Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_LPD_XPPU_CFG_MASTER_ID12"> | |
| PSU_LPD_XPPU_CFG_MASTER_ID12 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980130</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master ID 12 Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_LPD_XPPU_CFG_MASTER_ID13"> | |
| PSU_LPD_XPPU_CFG_MASTER_ID13 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980134</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master ID 13 Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_LPD_XPPU_CFG_MASTER_ID14"> | |
| PSU_LPD_XPPU_CFG_MASTER_ID14 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980138</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master ID 14 Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_LPD_XPPU_CFG_MASTER_ID15"> | |
| PSU_LPD_XPPU_CFG_MASTER_ID15 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF98013C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master ID 15 Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_LPD_XPPU_CFG_MASTER_ID16"> | |
| PSU_LPD_XPPU_CFG_MASTER_ID16 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980140</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master ID 16 Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_LPD_XPPU_CFG_MASTER_ID17"> | |
| PSU_LPD_XPPU_CFG_MASTER_ID17 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980144</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master ID 17 Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_LPD_XPPU_CFG_MASTER_ID18"> | |
| PSU_LPD_XPPU_CFG_MASTER_ID18 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980148</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master ID 18 Register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <A href="#PSU_LPD_XPPU_CFG_MASTER_ID19"> | |
| PSU_LPD_XPPU_CFG_MASTER_ID19 | |
| </A> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF98014C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>RW</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Master ID 19 Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="psu_security_data_3_0">psu_security_data_3_0</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFC0FF> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFC0FF> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFC0FF> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <H1>DDR XMPU0</H1> | |
| <H1>DDR XMPU1</H1> | |
| <H1>DDR XMPU2</H1> | |
| <H1>DDR XMPU3</H1> | |
| <H1>DDR XMPU4</H1> | |
| <H1>DDR XMPU5</H1> | |
| <H1>FPD XMPU</H1> | |
| <H1>OCM XMPU</H1> | |
| <H1>XPPU</H1> | |
| <H1>MASTER ID LIST</H1> | |
| <H2><a name="MASTER_ID00">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID00</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MASTER_ID00</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980100</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID00_MIDP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID00_MIDR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>If set, only read transactions are allowed for the masters matching this register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID00_MIDM</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Mask to be applied before comparing</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID00_MID</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Predefined Master ID for PMU</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID00@0XFF980100</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>c3ff03ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Master ID 00 Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MASTER_ID01">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID01</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MASTER_ID01</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980104</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID01_MIDP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID01_MIDR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>If set, only read transactions are allowed for the masters matching this register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID01_MIDM</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Mask to be applied before comparing</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID01_MID</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Predefined Master ID for RPU0</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID01@0XFF980104</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>c3ff03ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Master ID 01 Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MASTER_ID02">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID02</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MASTER_ID02</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980108</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID02_MIDP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID02_MIDR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>If set, only read transactions are allowed for the masters matching this register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID02_MIDM</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Mask to be applied before comparing</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID02_MID</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Predefined Master ID for RPU1</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID02@0XFF980108</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>c3ff03ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Master ID 02 Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MASTER_ID03">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID03</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MASTER_ID03</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF98010C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID03_MIDP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID03_MIDR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>If set, only read transactions are allowed for the masters matching this register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID03_MIDM</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Mask to be applied before comparing</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID03_MID</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Predefined Master ID for APU</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID03@0XFF98010C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>c3ff03ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Master ID 03 Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MASTER_ID04">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID04</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MASTER_ID04</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980110</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID04_MIDP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID04_MIDR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>If set, only read transactions are allowed for the masters matching this register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID04_MIDM</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Mask to be applied before comparing</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID04_MID</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Predefined Master ID for A53 Core 0</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID04@0XFF980110</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>c3ff03ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Master ID 04 Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MASTER_ID05">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID05</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MASTER_ID05</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980114</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID05_MIDP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID05_MIDR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>If set, only read transactions are allowed for the masters matching this register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID05_MIDM</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Mask to be applied before comparing</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID05_MID</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Predefined Master ID for A53 Core 1</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID05@0XFF980114</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>c3ff03ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Master ID 05 Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MASTER_ID06">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID06</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MASTER_ID06</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980118</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID06_MIDP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID06_MIDR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>If set, only read transactions are allowed for the masters matching this register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID06_MIDM</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Mask to be applied before comparing</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID06_MID</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Predefined Master ID for A53 Core 2</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID06@0XFF980118</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>c3ff03ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Master ID 06 Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MASTER_ID07">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID07</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MASTER_ID07</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF98011C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID07_MIDP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID07_MIDR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>If set, only read transactions are allowed for the masters matching this register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID07_MIDM</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Mask to be applied before comparing</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID07_MID</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Predefined Master ID for A53 Core 3</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID07@0XFF98011C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>c3ff03ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Master ID 07 Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MASTER_ID08">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID08</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MASTER_ID08</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980120</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID08_MIDP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID08_MIDR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>If set, only read transactions are allowed for the masters matching this register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID08_MIDM</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Mask to be applied before comparing</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID08_MID</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Programmable Master ID</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID08@0XFF980120</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>c3ff03ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Master ID 08 Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MASTER_ID09">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID09</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MASTER_ID09</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980124</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID09_MIDP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID09_MIDR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>If set, only read transactions are allowed for the masters matching this register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID09_MIDM</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Mask to be applied before comparing</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID09_MID</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Programmable Master ID</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID09@0XFF980124</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>c3ff03ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Master ID 09 Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MASTER_ID10">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID10</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MASTER_ID10</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980128</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID10_MIDP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID10_MIDR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>If set, only read transactions are allowed for the masters matching this register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID10_MIDM</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Mask to be applied before comparing</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID10_MID</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Programmable Master ID</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID10@0XFF980128</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>c3ff03ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Master ID 10 Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MASTER_ID11">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID11</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MASTER_ID11</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF98012C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID11_MIDP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID11_MIDR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>If set, only read transactions are allowed for the masters matching this register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID11_MIDM</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Mask to be applied before comparing</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID11_MID</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Programmable Master ID</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID11@0XFF98012C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>c3ff03ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Master ID 11 Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MASTER_ID12">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID12</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MASTER_ID12</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980130</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID12_MIDP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID12_MIDR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>If set, only read transactions are allowed for the masters matching this register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID12_MIDM</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Mask to be applied before comparing</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID12_MID</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Programmable Master ID</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID12@0XFF980130</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>c3ff03ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Master ID 12 Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MASTER_ID13">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID13</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MASTER_ID13</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980134</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID13_MIDP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID13_MIDR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>If set, only read transactions are allowed for the masters matching this register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID13_MIDM</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Mask to be applied before comparing</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID13_MID</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Programmable Master ID</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID13@0XFF980134</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>c3ff03ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Master ID 13 Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MASTER_ID14">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID14</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MASTER_ID14</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980138</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID14_MIDP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID14_MIDR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>If set, only read transactions are allowed for the masters matching this register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID14_MIDM</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Mask to be applied before comparing</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID14_MID</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Programmable Master ID</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID14@0XFF980138</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>c3ff03ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Master ID 14 Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MASTER_ID15">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID15</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MASTER_ID15</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF98013C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID15_MIDP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID15_MIDR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>If set, only read transactions are allowed for the masters matching this register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID15_MIDM</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Mask to be applied before comparing</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID15_MID</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Programmable Master ID</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID15@0XFF98013C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>c3ff03ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Master ID 15 Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MASTER_ID16">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID16</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MASTER_ID16</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980140</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID16_MIDP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID16_MIDR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>If set, only read transactions are allowed for the masters matching this register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID16_MIDM</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Mask to be applied before comparing</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID16_MID</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Programmable Master ID</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID16@0XFF980140</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>c3ff03ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Master ID 16 Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MASTER_ID17">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID17</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MASTER_ID17</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980144</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID17_MIDP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID17_MIDR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>If set, only read transactions are allowed for the masters matching this register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID17_MIDM</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Mask to be applied before comparing</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID17_MID</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Programmable Master ID</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID17@0XFF980144</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>c3ff03ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Master ID 17 Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MASTER_ID18">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID18</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MASTER_ID18</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF980148</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID18_MIDP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID18_MIDR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>If set, only read transactions are allowed for the masters matching this register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID18_MIDM</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Mask to be applied before comparing</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID18_MID</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Programmable Master ID</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID18@0XFF980148</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>c3ff03ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Master ID 18 Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H2><a name="MASTER_ID19">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID19</a></H2> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Register Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Address</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Width</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FFFF00> | |
| <B>Type</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FFFF00> | |
| <B>Reset Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FFFF00> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>MASTER_ID19</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0XFF98014C</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>32</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>rw</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0x00000000</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>--</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%"> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Field Name</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Bits</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Mask</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0FFC0> | |
| <B>Value</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0FFC0> | |
| <B>Shifted Value</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0FFC0> | |
| <B>Description</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID19_MIDP</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>31:31</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>80000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID19_MIDR</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>30:30</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>40000000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>If set, only read transactions are allowed for the masters matching this register</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID19_MIDM</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>25:16</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff0000</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Mask to be applied before comparing</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID19_MID</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>9:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>3ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#FBF5EF> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#FBF5EF> | |
| <B>Programmable Master ID</B> | |
| </TD> | |
| </TR> | |
| <TR valign="top"> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>PSU_LPD_XPPU_CFG_MASTER_ID19@0XFF98014C</B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>31:0</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B>c3ff03ff</B> | |
| </TD> | |
| <TD width=10% BGCOLOR=#C0C0C0> | |
| <B></B> | |
| </TD> | |
| <TD width=15% BGCOLOR=#C0C0C0> | |
| <B>0</B> | |
| </TD> | |
| <TD width=35% BGCOLOR=#C0C0C0> | |
| <B>Master ID 19 Register</B> | |
| </TD> | |
| </TR> | |
| </TABLE> | |
| <P> | |
| <H1>APERTURE PERMISIION LIST</H1> | |
| </TABLE> | |
| <P> | |
| </body> | |
| </head> | |
| </body> | |
| </html> |