/* | |
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. | |
All rights reserved | |
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. | |
This file is part of the FreeRTOS distribution. | |
FreeRTOS is free software; you can redistribute it and/or modify it under | |
the terms of the GNU General Public License (version 2) as published by the | |
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. | |
*************************************************************************** | |
>>! NOTE: The modification to the GPL is included to allow you to !<< | |
>>! distribute a combined work that includes FreeRTOS without being !<< | |
>>! obliged to provide the source code for proprietary components !<< | |
>>! outside of the FreeRTOS kernel. !<< | |
*************************************************************************** | |
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY | |
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS | |
FOR A PARTICULAR PURPOSE. Full license text is available on the following | |
link: http://www.freertos.org/a00114.html | |
*************************************************************************** | |
* * | |
* FreeRTOS provides completely free yet professionally developed, * | |
* robust, strictly quality controlled, supported, and cross * | |
* platform software that is more than just the market leader, it * | |
* is the industry's de facto standard. * | |
* * | |
* Help yourself get started quickly while simultaneously helping * | |
* to support the FreeRTOS project by purchasing a FreeRTOS * | |
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* http://www.FreeRTOS.org/Documentation * | |
* * | |
*************************************************************************** | |
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading | |
the FAQ page "My application does not run, what could be wrong?". Have you | |
defined configASSERT()? | |
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participating in the support forum. | |
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Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. | |
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mission critical applications that require provable dependability. | |
1 tab == 4 spaces! | |
*/ | |
/* | |
* This file contains the non-portable and therefore RX62N specific parts of | |
* the IntQueue standard demo task - namely the configuration of the timers | |
* that generate the interrupts and the interrupt entry points. | |
*/ | |
/* Scheduler includes. */ | |
#include "FreeRTOS.h" | |
#include "task.h" | |
/* Demo includes. */ | |
#include "IntQueueTimer.h" | |
#include "IntQueue.h" | |
/* Hardware specifics. */ | |
#include "iodefine.h" | |
#define tmrTIMER_0_1_FREQUENCY ( 2000UL ) | |
#define tmrTIMER_2_3_FREQUENCY ( 2407UL ) | |
void vInitialiseTimerForIntQueueTest( void ) | |
{ | |
/* Ensure interrupts do not start until full configuration is complete. */ | |
portENTER_CRITICAL(); | |
{ | |
/* Give write access. */ | |
SYSTEM.PRCR.WORD = 0xa502; | |
/* Cascade two 8bit timer channels to generate the interrupts. | |
8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are | |
utilised for this test. */ | |
/* Enable the timers. */ | |
SYSTEM.MSTPCRA.BIT.MSTPA5 = 0; | |
SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; | |
/* Enable compare match A interrupt request. */ | |
TMR0.TCR.BIT.CMIEA = 1; | |
TMR2.TCR.BIT.CMIEA = 1; | |
/* Clear the timer on compare match A. */ | |
TMR0.TCR.BIT.CCLR = 1; | |
TMR2.TCR.BIT.CCLR = 1; | |
/* Set the compare match value. */ | |
TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); | |
TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); | |
/* 16 bit operation ( count from timer 1,2 ). */ | |
TMR0.TCCR.BIT.CSS = 3; | |
TMR2.TCCR.BIT.CSS = 3; | |
/* Use PCLK as the input. */ | |
TMR1.TCCR.BIT.CSS = 1; | |
TMR3.TCCR.BIT.CSS = 1; | |
/* Divide PCLK by 8. */ | |
TMR1.TCCR.BIT.CKS = 2; | |
TMR3.TCCR.BIT.CKS = 2; | |
/* Enable TMR 0, 2 interrupts. */ | |
TMR0.TCR.BIT.CMIEA = 1; | |
TMR2.TCR.BIT.CMIEA = 1; | |
/* Set interrupt priority and enable. */ | |
IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; | |
IR( TMR0, CMIA0 ) = 0U; | |
IEN( TMR0, CMIA0 ) = 1U; | |
/* Do the same for TMR2, but to vector 129. */ | |
IPR( TMR2, CMIA2 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2; | |
IR( TMR2, CMIA2 ) = 0U; | |
IEN( TMR2, CMIA2 ) = 1U; | |
} | |
portEXIT_CRITICAL(); | |
} | |
/*-----------------------------------------------------------*/ | |
#pragma interrupt r_tmr_cmia0_interrupt(vect=VECT(TMR0,CMIA0)) | |
void r_tmr_cmia0_interrupt( void ) | |
{ | |
portYIELD_FROM_ISR( xFirstTimerHandler() ); | |
} | |
/*-----------------------------------------------------------*/ | |
#pragma interrupt r_tmr_cmia2_interrupt(vect=VECT(TMR2,CMIA2)) | |
void r_tmr_cmia2_interrupt( void ) | |
{ | |
portYIELD_FROM_ISR( xSecondTimerHandler() ); | |
} | |