riscv: refine vector context layout on stack (#1329)
Vector general register layout:
Before:
+--------------+ <-- High Address
| v7 |
+--------------+
| v6 |
+--------------+
| ... |
+--------------+
| v0 |
+--------------+ <-- v0 - v7
| v15 |
+--------------+
| v14 |
+--------------+
| ... |
+--------------+
| v8 |
+--------------+ <-- v8 - v15
| ... |
+--------------+
| v24 |
+--------------+ <-- Low address
After:
+--------------+ <-- High Address
| v31 |
+--------------+
| v30 |
+--------------+
| ... |
+--------------+
| v1 |
+--------------+
| v0 |
+--------------+ <-- Low Address
Signed-off-by: wangfei_chen <wangfei_chen@realsil.com.cn>
Co-authored-by: wangfei_chen <wangfei_chen@realsil.com.cn>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
diff --git a/portable/GCC/RISC-V/portContext.h b/portable/GCC/RISC-V/portContext.h
index 012965c..0869a82 100644
--- a/portable/GCC/RISC-V/portContext.h
+++ b/portable/GCC/RISC-V/portContext.h
@@ -214,13 +214,13 @@
/* Store the vector registers in group of 8. */
add sp, sp, t0
-vs8r.v v0, (sp) /* Store v0-v7. */
-add sp, sp, t0
-vs8r.v v8, (sp) /* Store v8-v15. */
+vs8r.v v24, (sp) /* Store v24-v31. */
add sp, sp, t0
vs8r.v v16, (sp) /* Store v16-v23. */
add sp, sp, t0
-vs8r.v v24, (sp) /* Store v24-v31. */
+vs8r.v v8, (sp) /* Store v8-v15. */
+add sp, sp, t0
+vs8r.v v0, (sp) /* Store v0-v7. */
/* Store the VPU CSRs. */
addi sp, sp, -( 4 * portWORD_SIZE )
@@ -256,13 +256,13 @@
slli t0, t0, 3 /* t0 = vlenb * 8. t0 now contains the space required to store 8 vector registers. */
/* Restore the vector registers. */
-vl8r.v v24, (sp)
+vl8r.v v0, (sp) /* Restore v0-v7. */
add sp, sp, t0
-vl8r.v v16, (sp)
+vl8r.v v8, (sp) /* Restore v8-v15. */
add sp, sp, t0
-vl8r.v v8, (sp)
+vl8r.v v16, (sp) /* Restore v16-v23. */
add sp, sp, t0
-vl8r.v v0, (sp)
+vl8r.v v24, (sp) /* Restore v23-v31. */
add sp, sp, t0
/* Re-reserve the space for mstatus and epc. */
