Second phase of changing the directory that starts Cortex, with one that starts CORTEX.
diff --git a/Demo/_Cortex_STM32L152_IAR/FreeRTOSConfig.h b/Demo/_Cortex_STM32L152_IAR/FreeRTOSConfig.h
deleted file mode 100644
index 74acd46..0000000
--- a/Demo/_Cortex_STM32L152_IAR/FreeRTOSConfig.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- FreeRTOS V6.1.0 - Copyright (C) 2010 Real Time Engineers Ltd.
-
- ***************************************************************************
- * *
- * If you are: *
- * *
- * + New to FreeRTOS, *
- * + Wanting to learn FreeRTOS or multitasking in general quickly *
- * + Looking for basic training, *
- * + Wanting to improve your FreeRTOS skills and productivity *
- * *
- * then take a look at the FreeRTOS books - available as PDF or paperback *
- * *
- * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
- * http://www.FreeRTOS.org/Documentation *
- * *
- * A pdf reference manual is also available. Both are usually delivered *
- * to your inbox within 20 minutes to two hours when purchased between 8am *
- * and 8pm GMT (although please allow up to 24 hours in case of *
- * exceptional circumstances). Thank you for your support! *
- * *
- ***************************************************************************
-
- This file is part of the FreeRTOS distribution.
-
- FreeRTOS is free software; you can redistribute it and/or modify it under
- the terms of the GNU General Public License (version 2) as published by the
- Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
- ***NOTE*** The exception to the GPL is included to allow you to distribute
- a combined work that includes FreeRTOS without being obliged to provide the
- source code for proprietary components outside of the FreeRTOS kernel.
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- more details. You should have received a copy of the GNU General Public
- License and the FreeRTOS license exception along with FreeRTOS; if not it
- can be viewed here: http://www.freertos.org/a00114.html and also obtained
- by writing to Richard Barry, contact details for whom are available on the
- FreeRTOS WEB site.
-
- 1 tab == 4 spaces!
-
- http://www.FreeRTOS.org - Documentation, latest information, license and
- contact details.
-
- http://www.SafeRTOS.com - A version that is certified for use in safety
- critical systems.
-
- http://www.OpenRTOS.com - Commercial support, development, porting,
- licensing and training services.
-*/
-
-#ifndef FREERTOS_CONFIG_H
-#define FREERTOS_CONFIG_H
-
-/*-----------------------------------------------------------
- * Application specific definitions.
- *
- * These definitions should be adjusted for your particular hardware and
- * application requirements.
- *
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
- *
- * See http://www.freertos.org/a00110.html.
- *----------------------------------------------------------*/
-
-#define configUSE_PREEMPTION 1
-#define configUSE_IDLE_HOOK 1
-#define configUSE_TICK_HOOK 1
-#define configCPU_CLOCK_HZ ( 32000000UL )
-#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
-#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
-#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 70 )
-#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 10 * 1024 ) )
-#define configMAX_TASK_NAME_LEN ( 16 )
-#define configUSE_TRACE_FACILITY 0
-#define configUSE_16_BIT_TICKS 0
-#define configIDLE_SHOULD_YIELD 1
-#define configUSE_MUTEXES 1
-#define configQUEUE_REGISTRY_SIZE 5
-#define configGENERATE_RUN_TIME_STATS 1
-#define configCHECK_FOR_STACK_OVERFLOW 2
-#define configUSE_RECURSIVE_MUTEXES 0
-#define configUSE_MALLOC_FAILED_HOOK 1
-#define configUSE_APPLICATION_TASK_TAG 0
-
-/* Co-routine definitions. */
-#define configUSE_CO_ROUTINES 0
-#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
-
-/* Set the following definitions to 1 to include the API function, or zero
-to exclude the API function. */
-
-#define INCLUDE_vTaskPrioritySet 1
-#define INCLUDE_uxTaskPriorityGet 1
-#define INCLUDE_vTaskDelete 1
-#define INCLUDE_vTaskCleanUpResources 0
-#define INCLUDE_vTaskSuspend 1
-#define INCLUDE_vTaskDelayUntil 1
-#define INCLUDE_vTaskDelay 1
-
-/* Use the system definition, if there is one */
-#ifdef __NVIC_PRIO_BITS
- #define configPRIO_BITS __NVIC_PRIO_BITS
-#else
- #define configPRIO_BITS 4 /* 15 priority levels */
-#endif
-
-#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15
-#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
-
-/* The lowest priority. */
-#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-/* Priority 5, or 160 as only the top three bits are implemented. */
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-
-/* Prevent the following definitions being included when FreeRTOSConfig.h
-is included from an asm file. */
-#ifdef __ICCARM__
- #include "stm32l1xx_tim.h"
- extern void vConfigureTimerForRunTimeStats( void );
- extern unsigned long ulTIM6_OverflowCount;
-#endif /* __ICCARM__ */
-
-#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats()
-#define portALT_GET_RUN_TIME_COUNTER_VALUE( ulCountValue ) \
- { \
- TIM_Cmd( TIM6, DISABLE ); \
- ulCountValue = ( ( ulTIM6_OverflowCount << 16UL ) | ( unsigned long ) TIM6->CNT ); \
- TIM_Cmd( TIM6, ENABLE ); \
- }
-
-#endif /* FREERTOS_CONFIG_H */
-
diff --git a/Demo/_Cortex_STM32L152_IAR/ParTest.c b/Demo/_Cortex_STM32L152_IAR/ParTest.c
deleted file mode 100644
index 53353d6..0000000
--- a/Demo/_Cortex_STM32L152_IAR/ParTest.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- FreeRTOS V6.1.0 - Copyright (C) 2010 Real Time Engineers Ltd.
-
- ***************************************************************************
- * *
- * If you are: *
- * *
- * + New to FreeRTOS, *
- * + Wanting to learn FreeRTOS or multitasking in general quickly *
- * + Looking for basic training, *
- * + Wanting to improve your FreeRTOS skills and productivity *
- * *
- * then take a look at the FreeRTOS books - available as PDF or paperback *
- * *
- * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
- * http://www.FreeRTOS.org/Documentation *
- * *
- * A pdf reference manual is also available. Both are usually delivered *
- * to your inbox within 20 minutes to two hours when purchased between 8am *
- * and 8pm GMT (although please allow up to 24 hours in case of *
- * exceptional circumstances). Thank you for your support! *
- * *
- ***************************************************************************
-
- This file is part of the FreeRTOS distribution.
-
- FreeRTOS is free software; you can redistribute it and/or modify it under
- the terms of the GNU General Public License (version 2) as published by the
- Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
- ***NOTE*** The exception to the GPL is included to allow you to distribute
- a combined work that includes FreeRTOS without being obliged to provide the
- source code for proprietary components outside of the FreeRTOS kernel.
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- more details. You should have received a copy of the GNU General Public
- License and the FreeRTOS license exception along with FreeRTOS; if not it
- can be viewed here: http://www.freertos.org/a00114.html and also obtained
- by writing to Richard Barry, contact details for whom are available on the
- FreeRTOS WEB site.
-
- 1 tab == 4 spaces!
-
- http://www.FreeRTOS.org - Documentation, latest information, license and
- contact details.
-
- http://www.SafeRTOS.com - A version that is certified for use in safety
- critical systems.
-
- http://www.OpenRTOS.com - Commercial support, development, porting,
- licensing and training services.
-*/
-
-/*-----------------------------------------------------------
- * Simple parallel port IO routines.
- *-----------------------------------------------------------*/
-
-/* Kernel includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* ST library functions. */
-#include "stm32l152_eval.h"
-
-#define partstMAX_OUTPUT_LED 4
-
-/*-----------------------------------------------------------*/
-
-void vParTestInitialise( void )
-{
- /* Configure the output LEDs. Note that JP18 and JP19 must be closed on
- the Eval board for LED3 and LED4 to work. */
- STM_EVAL_LEDInit( LED1 );
- STM_EVAL_LEDInit( LED2 );
- STM_EVAL_LEDInit( LED3 );
- STM_EVAL_LEDInit( LED4 );
- STM_EVAL_LEDOff( LED1 );
- STM_EVAL_LEDOff( LED2 );
- STM_EVAL_LEDOff( LED3 );
- STM_EVAL_LEDOff( LED4 );
-}
-/*-----------------------------------------------------------*/
-
-void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
-{
- vTaskSuspendAll();
- {
- if( xValue != pdFALSE )
- {
- switch( uxLED )
- {
- case 0: STM_EVAL_LEDOn( LED1 );
- break;
-
- case 1: STM_EVAL_LEDOn( LED2 );
- break;
-
- case 2: STM_EVAL_LEDOn( LED3 );
- break;
-
- case 3: STM_EVAL_LEDOn( LED4 );
- break;
- }
- }
- else
- {
- switch( uxLED )
- {
- case 0: STM_EVAL_LEDOff( LED1 );
- break;
-
- case 1: STM_EVAL_LEDOff( LED2 );
- break;
-
- case 2: STM_EVAL_LEDOff( LED3 );
- break;
-
- case 3: STM_EVAL_LEDOff( LED4 );
- break;
- }
- }
- }
- xTaskResumeAll();
-}
-/*-----------------------------------------------------------*/
-
-void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
-{
- vTaskSuspendAll();
- {
- switch( uxLED )
- {
- case 0: STM_EVAL_LEDToggle( LED1 );
- break;
-
- case 1: STM_EVAL_LEDToggle( LED2 );
- break;
-
- case 2: STM_EVAL_LEDToggle( LED3 );
- break;
-
- case 3: STM_EVAL_LEDToggle( LED4 );
- break;
- }
- }
- xTaskResumeAll();
-}
-/*-----------------------------------------------------------*/
-
diff --git a/Demo/_Cortex_STM32L152_IAR/RTOSDemo.ewd b/Demo/_Cortex_STM32L152_IAR/RTOSDemo.ewd
deleted file mode 100644
index 9155522..0000000
--- a/Demo/_Cortex_STM32L152_IAR/RTOSDemo.ewd
+++ /dev/null
@@ -1,1683 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
- <fileVersion>2</fileVersion>
- <configuration>
- <name>Debug</name>
- <toolchain>
- <name>ARM</name>
- </toolchain>
- <debug>1</debug>
- <settings>
- <name>C-SPY</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>22</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>CInput</name>
- <state>1</state>
- </option>
- <option>
- <name>CEndian</name>
- <state>1</state>
- </option>
- <option>
- <name>CProcessor</name>
- <state>1</state>
- </option>
- <option>
- <name>OCVariant</name>
- <state>0</state>
- </option>
- <option>
- <name>MacOverride</name>
- <state>0</state>
- </option>
- <option>
- <name>MacFile</name>
- <state></state>
- </option>
- <option>
- <name>MemOverride</name>
- <state>0</state>
- </option>
- <option>
- <name>MemFile</name>
- <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\iostm32l152xx.ddf</state>
- </option>
- <option>
- <name>RunToEnable</name>
- <state>1</state>
- </option>
- <option>
- <name>RunToName</name>
- <state>main</state>
- </option>
- <option>
- <name>CExtraOptionsCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>CExtraOptions</name>
- <state></state>
- </option>
- <option>
- <name>CFpuProcessor</name>
- <state>1</state>
- </option>
- <option>
- <name>OCDDFArgumentProducer</name>
- <state></state>
- </option>
- <option>
- <name>OCDownloadSuppressDownload</name>
- <state>0</state>
- </option>
- <option>
- <name>OCDownloadVerifyAll</name>
- <state>0</state>
- </option>
- <option>
- <name>OCProductVersion</name>
- <state>6.10.1.52170</state>
- </option>
- <option>
- <name>OCDynDriverList</name>
- <state>JLINK_ID</state>
- </option>
- <option>
- <name>OCLastSavedByProductVersion</name>
- <state>6.10.1.52170</state>
- </option>
- <option>
- <name>OCDownloadAttachToProgram</name>
- <state>0</state>
- </option>
- <option>
- <name>UseFlashLoader</name>
- <state>1</state>
- </option>
- <option>
- <name>CLowLevel</name>
- <state>1</state>
- </option>
- <option>
- <name>OCBE8Slave</name>
- <state>1</state>
- </option>
- <option>
- <name>MacFile2</name>
- <state></state>
- </option>
- <option>
- <name>CDevice</name>
- <state>1</state>
- </option>
- <option>
- <name>FlashLoadersV3</name>
- <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32L15xxB.board</state>
- </option>
- <option>
- <name>OCImagesSuppressCheck1</name>
- <state>0</state>
- </option>
- <option>
- <name>OCImagesPath1</name>
- <state></state>
- </option>
- <option>
- <name>OCImagesSuppressCheck2</name>
- <state>0</state>
- </option>
- <option>
- <name>OCImagesPath2</name>
- <state></state>
- </option>
- <option>
- <name>OCImagesSuppressCheck3</name>
- <state>0</state>
- </option>
- <option>
- <name>OCImagesPath3</name>
- <state></state>
- </option>
- <option>
- <name>OverrideDefFlashBoard</name>
- <state>0</state>
- </option>
- <option>
- <name>OCImagesOffset1</name>
- <state></state>
- </option>
- <option>
- <name>OCImagesOffset2</name>
- <state></state>
- </option>
- <option>
- <name>OCImagesOffset3</name>
- <state></state>
- </option>
- <option>
- <name>OCImagesUse1</name>
- <state>0</state>
- </option>
- <option>
- <name>OCImagesUse2</name>
- <state>0</state>
- </option>
- <option>
- <name>OCImagesUse3</name>
- <state>0</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>ARMSIM_ID</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>1</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>OCSimDriverInfo</name>
- <state>1</state>
- </option>
- <option>
- <name>OCSimEnablePSP</name>
- <state>0</state>
- </option>
- <option>
- <name>OCSimPspOverrideConfig</name>
- <state>0</state>
- </option>
- <option>
- <name>OCSimPspConfigFile</name>
- <state></state>
- </option>
- </data>
- </settings>
- <settings>
- <name>ANGEL_ID</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>0</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>CCAngelHeartbeat</name>
- <state>1</state>
- </option>
- <option>
- <name>CAngelCommunication</name>
- <state>1</state>
- </option>
- <option>
- <name>CAngelCommBaud</name>
- <version>0</version>
- <state>3</state>
- </option>
- <option>
- <name>CAngelCommPort</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>ANGELTCPIP</name>
- <state>aaa.bbb.ccc.ddd</state>
- </option>
- <option>
- <name>DoAngelLogfile</name>
- <state>0</state>
- </option>
- <option>
- <name>AngelLogFile</name>
- <state>$PROJ_DIR$\cspycomm.log</state>
- </option>
- <option>
- <name>OCDriverInfo</name>
- <state>1</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>GDBSERVER_ID</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>0</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>OCDriverInfo</name>
- <state>1</state>
- </option>
- <option>
- <name>TCPIP</name>
- <state>aaa.bbb.ccc.ddd</state>
- </option>
- <option>
- <name>DoLogfile</name>
- <state>0</state>
- </option>
- <option>
- <name>LogFile</name>
- <state>$PROJ_DIR$\cspycomm.log</state>
- </option>
- <option>
- <name>CCJTagBreakpointRadio</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJTagDoUpdateBreakpoints</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJTagUpdateBreakpoints</name>
- <state>_call_main</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>IARROM_ID</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>1</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>CRomLogFileCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>CRomLogFileEditB</name>
- <state>$PROJ_DIR$\cspycomm.log</state>
- </option>
- <option>
- <name>CRomCommPort</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CRomCommBaud</name>
- <version>0</version>
- <state>7</state>
- </option>
- <option>
- <name>OCDriverInfo</name>
- <state>1</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>JLINK_ID</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>12</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>JLinkSpeed</name>
- <state>32</state>
- </option>
- <option>
- <name>CCJLinkDoLogfile</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJLinkLogFile</name>
- <state>$PROJ_DIR$\cspycomm.log</state>
- </option>
- <option>
- <name>CCJLinkHWResetDelay</name>
- <state>0</state>
- </option>
- <option>
- <name>OCDriverInfo</name>
- <state>1</state>
- </option>
- <option>
- <name>JLinkInitialSpeed</name>
- <state>32</state>
- </option>
- <option>
- <name>CCDoJlinkMultiTarget</name>
- <state>0</state>
- </option>
- <option>
- <name>CCScanChainNonARMDevices</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJLinkMultiTarget</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJLinkIRLength</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJLinkCommRadio</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJLinkTCPIP</name>
- <state>aaa.bbb.ccc.ddd</state>
- </option>
- <option>
- <name>CCJLinkSpeedRadioV2</name>
- <state>0</state>
- </option>
- <option>
- <name>CCUSBDevice</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CCRDICatchReset</name>
- <state>0</state>
- </option>
- <option>
- <name>CCRDICatchUndef</name>
- <state>0</state>
- </option>
- <option>
- <name>CCRDICatchSWI</name>
- <state>0</state>
- </option>
- <option>
- <name>CCRDICatchData</name>
- <state>0</state>
- </option>
- <option>
- <name>CCRDICatchPrefetch</name>
- <state>0</state>
- </option>
- <option>
- <name>CCRDICatchIRQ</name>
- <state>0</state>
- </option>
- <option>
- <name>CCRDICatchFIQ</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJLinkBreakpointRadio</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJLinkDoUpdateBreakpoints</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJLinkUpdateBreakpoints</name>
- <state>_call_main</state>
- </option>
- <option>
- <name>CCJLinkInterfaceRadio</name>
- <state>1</state>
- </option>
- <option>
- <name>OCJLinkAttachSlave</name>
- <state>1</state>
- </option>
- <option>
- <name>CCJLinkResetList</name>
- <version>4</version>
- <state>7</state>
- </option>
- <option>
- <name>CCJLinkInterfaceCmdLine</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCatchCORERESET</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCatchMMERR</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCatchNOCPERR</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCatchCHRERR</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCatchSTATERR</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCatchBUSERR</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCatchINTERR</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCatchHARDERR</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCatchDummy</name>
- <state>0</state>
- </option>
- <option>
- <name>OCJLinkScriptFile</name>
- <state>1</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>LMIFTDI_ID</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>2</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>OCDriverInfo</name>
- <state>1</state>
- </option>
- <option>
- <name>LmiftdiSpeed</name>
- <state>500</state>
- </option>
- <option>
- <name>CCLmiftdiDoLogfile</name>
- <state>0</state>
- </option>
- <option>
- <name>CCLmiftdiLogFile</name>
- <state>$PROJ_DIR$\cspycomm.log</state>
- </option>
- <option>
- <name>CCLmiFtdiInterfaceRadio</name>
- <state>0</state>
- </option>
- <option>
- <name>CCLmiFtdiInterfaceCmdLine</name>
- <state>0</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>MACRAIGOR_ID</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>3</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>jtag</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>EmuSpeed</name>
- <state>1</state>
- </option>
- <option>
- <name>TCPIP</name>
- <state>aaa.bbb.ccc.ddd</state>
- </option>
- <option>
- <name>DoLogfile</name>
- <state>0</state>
- </option>
- <option>
- <name>LogFile</name>
- <state>$PROJ_DIR$\cspycomm.log</state>
- </option>
- <option>
- <name>DoEmuMultiTarget</name>
- <state>0</state>
- </option>
- <option>
- <name>EmuMultiTarget</name>
- <state>0@ARM7TDMI</state>
- </option>
- <option>
- <name>EmuHWReset</name>
- <state>0</state>
- </option>
- <option>
- <name>CEmuCommBaud</name>
- <version>0</version>
- <state>4</state>
- </option>
- <option>
- <name>CEmuCommPort</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>jtago</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>OCDriverInfo</name>
- <state>1</state>
- </option>
- <option>
- <name>UnusedAddr</name>
- <state>0x00800000</state>
- </option>
- <option>
- <name>CCMacraigorHWResetDelay</name>
- <state></state>
- </option>
- <option>
- <name>CCJTagBreakpointRadio</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJTagDoUpdateBreakpoints</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJTagUpdateBreakpoints</name>
- <state>_call_main</state>
- </option>
- <option>
- <name>CCMacraigorInterfaceRadio</name>
- <state>0</state>
- </option>
- <option>
- <name>CCMacraigorInterfaceCmdLine</name>
- <state>0</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>PEMICRO_ID</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>0</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>OCDriverInfo</name>
- <state>1</state>
- </option>
- <option>
- <name>OCPEMicroAttachSlave</name>
- <state>1</state>
- </option>
- <option>
- <name>CCPEMicroInterfaceList</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CCPEMicroResetDelay</name>
- <state></state>
- </option>
- <option>
- <name>CCPEMicroJtagSpeed</name>
- <state>#UNINITIALIZED#</state>
- </option>
- <option>
- <name>CCJPEMicroShowSettings</name>
- <state>0</state>
- </option>
- <option>
- <name>DoLogfile</name>
- <state>0</state>
- </option>
- <option>
- <name>LogFile</name>
- <state>$PROJ_DIR$\cspycomm.log</state>
- </option>
- <option>
- <name>CCPEMicroUSBDevice</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CCPEMicroSerialPort</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CCJPEMicroTCPIPAutoScanNetwork</name>
- <state>1</state>
- </option>
- <option>
- <name>CCPEMicroTCPIP</name>
- <state>10.0.0.1</state>
- </option>
- <option>
- <name>CCPEMicroCommCmdLineProducer</name>
- <state>0</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>RDI_ID</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>1</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>CRDIDriverDll</name>
- <state>###Uninitialized###</state>
- </option>
- <option>
- <name>CRDILogFileCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>CRDILogFileEdit</name>
- <state>$PROJ_DIR$\cspycomm.log</state>
- </option>
- <option>
- <name>CCRDIHWReset</name>
- <state>0</state>
- </option>
- <option>
- <name>CCRDICatchReset</name>
- <state>0</state>
- </option>
- <option>
- <name>CCRDICatchUndef</name>
- <state>0</state>
- </option>
- <option>
- <name>CCRDICatchSWI</name>
- <state>0</state>
- </option>
- <option>
- <name>CCRDICatchData</name>
- <state>0</state>
- </option>
- <option>
- <name>CCRDICatchPrefetch</name>
- <state>0</state>
- </option>
- <option>
- <name>CCRDICatchIRQ</name>
- <state>0</state>
- </option>
- <option>
- <name>CCRDICatchFIQ</name>
- <state>0</state>
- </option>
- <option>
- <name>CCRDIUseETM</name>
- <state>0</state>
- </option>
- <option>
- <name>OCDriverInfo</name>
- <state>1</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>STLINK_ID</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>1</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>OCDriverInfo</name>
- <state>1</state>
- </option>
- <option>
- <name>CCSTLinkInterfaceRadio</name>
- <state>0</state>
- </option>
- <option>
- <name>CCSTLinkInterfaceCmdLine</name>
- <state>0</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>THIRDPARTY_ID</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>0</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>CThirdPartyDriverDll</name>
- <state>###Uninitialized###</state>
- </option>
- <option>
- <name>CThirdPartyLogFileCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>CThirdPartyLogFileEditB</name>
- <state>$PROJ_DIR$\cspycomm.log</state>
- </option>
- <option>
- <name>OCDriverInfo</name>
- <state>1</state>
- </option>
- </data>
- </settings>
- <debuggerPlugins>
- <plugin>
- <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
- <loadFlag>0</loadFlag>
- </plugin>
- <plugin>
- <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
- <loadFlag>0</loadFlag>
- </plugin>
- <plugin>
- <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
- <loadFlag>0</loadFlag>
- </plugin>
- <plugin>
- <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
- <loadFlag>0</loadFlag>
- </plugin>
- <plugin>
- <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
- <loadFlag>1</loadFlag>
- </plugin>
- <plugin>
- <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
- <loadFlag>0</loadFlag>
- </plugin>
- <plugin>
- <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
- <loadFlag>0</loadFlag>
- </plugin>
- <plugin>
- <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
- <loadFlag>0</loadFlag>
- </plugin>
- <plugin>
- <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
- <loadFlag>0</loadFlag>
- </plugin>
- <plugin>
- <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
- <loadFlag>0</loadFlag>
- </plugin>
- <plugin>
- <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
- <loadFlag>0</loadFlag>
- </plugin>
- <plugin>
- <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
- <loadFlag>1</loadFlag>
- </plugin>
- <plugin>
- <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>
- <loadFlag>0</loadFlag>
- </plugin>
- <plugin>
- <file>$EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
- <loadFlag>0</loadFlag>
- </plugin>
- <plugin>
- <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
- <loadFlag>0</loadFlag>
- </plugin>
- <plugin>
- <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>
- <loadFlag>1</loadFlag>
- </plugin>
- <plugin>
- <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>
- <loadFlag>1</loadFlag>
- </plugin>
- <plugin>
- <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
- <loadFlag>1</loadFlag>
- </plugin>
- </debuggerPlugins>
- </configuration>
- <configuration>
- <name>Release</name>
- <toolchain>
- <name>ARM</name>
- </toolchain>
- <debug>1</debug>
- <settings>
- <name>C-SPY</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>22</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>CInput</name>
- <state>1</state>
- </option>
- <option>
- <name>CEndian</name>
- <state>1</state>
- </option>
- <option>
- <name>CProcessor</name>
- <state>1</state>
- </option>
- <option>
- <name>OCVariant</name>
- <state>0</state>
- </option>
- <option>
- <name>MacOverride</name>
- <state>0</state>
- </option>
- <option>
- <name>MacFile</name>
- <state></state>
- </option>
- <option>
- <name>MemOverride</name>
- <state>0</state>
- </option>
- <option>
- <name>MemFile</name>
- <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\iostm32l152xx.ddf</state>
- </option>
- <option>
- <name>RunToEnable</name>
- <state>1</state>
- </option>
- <option>
- <name>RunToName</name>
- <state>main</state>
- </option>
- <option>
- <name>CExtraOptionsCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>CExtraOptions</name>
- <state></state>
- </option>
- <option>
- <name>CFpuProcessor</name>
- <state>1</state>
- </option>
- <option>
- <name>OCDDFArgumentProducer</name>
- <state></state>
- </option>
- <option>
- <name>OCDownloadSuppressDownload</name>
- <state>0</state>
- </option>
- <option>
- <name>OCDownloadVerifyAll</name>
- <state>0</state>
- </option>
- <option>
- <name>OCProductVersion</name>
- <state>6.10.1.52170</state>
- </option>
- <option>
- <name>OCDynDriverList</name>
- <state>JLINK_ID</state>
- </option>
- <option>
- <name>OCLastSavedByProductVersion</name>
- <state>6.10.1.52170</state>
- </option>
- <option>
- <name>OCDownloadAttachToProgram</name>
- <state>0</state>
- </option>
- <option>
- <name>UseFlashLoader</name>
- <state>1</state>
- </option>
- <option>
- <name>CLowLevel</name>
- <state>1</state>
- </option>
- <option>
- <name>OCBE8Slave</name>
- <state>1</state>
- </option>
- <option>
- <name>MacFile2</name>
- <state></state>
- </option>
- <option>
- <name>CDevice</name>
- <state>1</state>
- </option>
- <option>
- <name>FlashLoadersV3</name>
- <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32L15xxB.board</state>
- </option>
- <option>
- <name>OCImagesSuppressCheck1</name>
- <state>0</state>
- </option>
- <option>
- <name>OCImagesPath1</name>
- <state></state>
- </option>
- <option>
- <name>OCImagesSuppressCheck2</name>
- <state>0</state>
- </option>
- <option>
- <name>OCImagesPath2</name>
- <state></state>
- </option>
- <option>
- <name>OCImagesSuppressCheck3</name>
- <state>0</state>
- </option>
- <option>
- <name>OCImagesPath3</name>
- <state></state>
- </option>
- <option>
- <name>OverrideDefFlashBoard</name>
- <state>0</state>
- </option>
- <option>
- <name>OCImagesOffset1</name>
- <state></state>
- </option>
- <option>
- <name>OCImagesOffset2</name>
- <state></state>
- </option>
- <option>
- <name>OCImagesOffset3</name>
- <state></state>
- </option>
- <option>
- <name>OCImagesUse1</name>
- <state>0</state>
- </option>
- <option>
- <name>OCImagesUse2</name>
- <state>0</state>
- </option>
- <option>
- <name>OCImagesUse3</name>
- <state>0</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>ARMSIM_ID</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>1</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>OCSimDriverInfo</name>
- <state>1</state>
- </option>
- <option>
- <name>OCSimEnablePSP</name>
- <state>0</state>
- </option>
- <option>
- <name>OCSimPspOverrideConfig</name>
- <state>0</state>
- </option>
- <option>
- <name>OCSimPspConfigFile</name>
- <state></state>
- </option>
- </data>
- </settings>
- <settings>
- <name>ANGEL_ID</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>0</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>CCAngelHeartbeat</name>
- <state>1</state>
- </option>
- <option>
- <name>CAngelCommunication</name>
- <state>1</state>
- </option>
- <option>
- <name>CAngelCommBaud</name>
- <version>0</version>
- <state>3</state>
- </option>
- <option>
- <name>CAngelCommPort</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>ANGELTCPIP</name>
- <state>aaa.bbb.ccc.ddd</state>
- </option>
- <option>
- <name>DoAngelLogfile</name>
- <state>0</state>
- </option>
- <option>
- <name>AngelLogFile</name>
- <state>$PROJ_DIR$\cspycomm.log</state>
- </option>
- <option>
- <name>OCDriverInfo</name>
- <state>1</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>GDBSERVER_ID</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>0</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>OCDriverInfo</name>
- <state>1</state>
- </option>
- <option>
- <name>TCPIP</name>
- <state>aaa.bbb.ccc.ddd</state>
- </option>
- <option>
- <name>DoLogfile</name>
- <state>0</state>
- </option>
- <option>
- <name>LogFile</name>
- <state>$PROJ_DIR$\cspycomm.log</state>
- </option>
- <option>
- <name>CCJTagBreakpointRadio</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJTagDoUpdateBreakpoints</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJTagUpdateBreakpoints</name>
- <state>_call_main</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>IARROM_ID</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>1</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>CRomLogFileCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>CRomLogFileEditB</name>
- <state>$PROJ_DIR$\cspycomm.log</state>
- </option>
- <option>
- <name>CRomCommPort</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CRomCommBaud</name>
- <version>0</version>
- <state>7</state>
- </option>
- <option>
- <name>OCDriverInfo</name>
- <state>1</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>JLINK_ID</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>12</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>JLinkSpeed</name>
- <state>32</state>
- </option>
- <option>
- <name>CCJLinkDoLogfile</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJLinkLogFile</name>
- <state>$PROJ_DIR$\cspycomm.log</state>
- </option>
- <option>
- <name>CCJLinkHWResetDelay</name>
- <state>0</state>
- </option>
- <option>
- <name>OCDriverInfo</name>
- <state>1</state>
- </option>
- <option>
- <name>JLinkInitialSpeed</name>
- <state>32</state>
- </option>
- <option>
- <name>CCDoJlinkMultiTarget</name>
- <state>0</state>
- </option>
- <option>
- <name>CCScanChainNonARMDevices</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJLinkMultiTarget</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJLinkIRLength</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJLinkCommRadio</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJLinkTCPIP</name>
- <state>aaa.bbb.ccc.ddd</state>
- </option>
- <option>
- <name>CCJLinkSpeedRadioV2</name>
- <state>0</state>
- </option>
- <option>
- <name>CCUSBDevice</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CCRDICatchReset</name>
- <state>0</state>
- </option>
- <option>
- <name>CCRDICatchUndef</name>
- <state>0</state>
- </option>
- <option>
- <name>CCRDICatchSWI</name>
- <state>0</state>
- </option>
- <option>
- <name>CCRDICatchData</name>
- <state>0</state>
- </option>
- <option>
- <name>CCRDICatchPrefetch</name>
- <state>0</state>
- </option>
- <option>
- <name>CCRDICatchIRQ</name>
- <state>0</state>
- </option>
- <option>
- <name>CCRDICatchFIQ</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJLinkBreakpointRadio</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJLinkDoUpdateBreakpoints</name>
- <state>0</state>
- </option>
- <option>
- <name>CCJLinkUpdateBreakpoints</name>
- <state>_call_main</state>
- </option>
- <option>
- <name>CCJLinkInterfaceRadio</name>
- <state>1</state>
- </option>
- <option>
- <name>OCJLinkAttachSlave</name>
- <state>1</state>
- </option>
- <option>
- <name>CCJLinkResetList</name>
- <version>4</version>
- <state>7</state>
- </option>
- <option>
- <name>CCJLinkInterfaceCmdLine</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCatchCORERESET</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCatchMMERR</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCatchNOCPERR</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCatchCHRERR</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCatchSTATERR</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCatchBUSERR</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCatchINTERR</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCatchHARDERR</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCatchDummy</name>
- <state>0</state>
- </option>
- <option>
- <name>OCJLinkScriptFile</name>
- <state>1</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>LMIFTDI_ID</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>2</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>OCDriverInfo</name>
- <state>1</state>
- </option>
- <option>
- <name>LmiftdiSpeed</name>
- <state>500</state>
- </option>
- <option>
- <name>CCLmiftdiDoLogfile</name>
- <state>0</state>
- </option>
- <option>
- <name>CCLmiftdiLogFile</name>
- <state>$PROJ_DIR$\cspycomm.log</state>
- </option>
- <option>
- <name>CCLmiFtdiInterfaceRadio</name>
- <state>0</state>
- </option>
- <option>
- <name>CCLmiFtdiInterfaceCmdLine</name>
- <state>0</state>
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- <settings>
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- <option>
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- <name>CCJTagDoUpdateBreakpoints</name>
- <state>0</state>
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- <option>
- <name>CCJTagUpdateBreakpoints</name>
- <state>_call_main</state>
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- <version>0</version>
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- <option>
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- <option>
- <name>OCPEMicroAttachSlave</name>
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- <name>CCPEMicroJtagSpeed</name>
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- <name>CCPEMicroCommCmdLineProducer</name>
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- <name>CCSTLinkInterfaceRadio</name>
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- <name>CCSTLinkInterfaceCmdLine</name>
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- </option>
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- <settings>
- <name>THIRDPARTY_ID</name>
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- <version>0</version>
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- <name>CThirdPartyDriverDll</name>
- <state>###Uninitialized###</state>
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- <name>CThirdPartyLogFileCheck</name>
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- <name>CThirdPartyLogFileEditB</name>
- <state>$PROJ_DIR$\cspycomm.log</state>
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- </option>
- </data>
- </settings>
- <debuggerPlugins>
- <plugin>
- <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
- <loadFlag>0</loadFlag>
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- <plugin>
- <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
- <loadFlag>0</loadFlag>
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- <plugin>
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- <loadFlag>0</loadFlag>
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- <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
- <loadFlag>1</loadFlag>
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- <loadFlag>0</loadFlag>
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- <loadFlag>0</loadFlag>
- </plugin>
- <plugin>
- <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
- <loadFlag>0</loadFlag>
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- <plugin>
- <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
- <loadFlag>1</loadFlag>
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- <plugin>
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- <plugin>
- <file>$EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
- <loadFlag>0</loadFlag>
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- <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
- <loadFlag>0</loadFlag>
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- <plugin>
- <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>
- <loadFlag>1</loadFlag>
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- <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>
- <loadFlag>1</loadFlag>
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- <plugin>
- <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
- <loadFlag>1</loadFlag>
- </plugin>
- </debuggerPlugins>
- </configuration>
-</project>
-
-
diff --git a/Demo/_Cortex_STM32L152_IAR/RTOSDemo.ewp b/Demo/_Cortex_STM32L152_IAR/RTOSDemo.ewp
deleted file mode 100644
index b875274..0000000
--- a/Demo/_Cortex_STM32L152_IAR/RTOSDemo.ewp
+++ /dev/null
@@ -1,1838 +0,0 @@
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- <option>
- <name>AUserIncludes</name>
- <state>$PROJ_DIR$</state>
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- <option>
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- <name>IlinkExtraOptions</name>
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- <name>IlinkAdditionalLibs</name>
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- <name>IlinkProgramEntryLabel</name>
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- <state>0x0</state>
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- <option>
- <name>IlinkBE8Slave</name>
- <state>1</state>
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- <option>
- <name>IlinkBufferedTerminalOutput</name>
- <state>1</state>
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- <option>
- <name>IlinkStdoutInterfaceSlave</name>
- <state>1</state>
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- <option>
- <name>CrcFullSize</name>
- <state>0</state>
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- <option>
- <name>IlinkIElfToolPostProcess</name>
- <state>0</state>
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- <option>
- <name>IlinkLogAutoLibSelect</name>
- <state>0</state>
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- <option>
- <name>IlinkLogRedirSymbols</name>
- <state>0</state>
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- <option>
- <name>IlinkLogUnusedFragments</name>
- <state>0</state>
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- <option>
- <name>IlinkCrcReverseByteOrder</name>
- <state>0</state>
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- <option>
- <name>IlinkCrcUseAsInput</name>
- <state>1</state>
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- <name>IlinkOptInline</name>
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- <option>
- <name>IlinkOptExceptionsAllow</name>
- <state>1</state>
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- <name>IlinkOptExceptionsForce</name>
- <state>0</state>
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- <name>IarchiveInputs</name>
- <state></state>
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- <state>0</state>
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- <name>IarchiveOutput</name>
- <state>###Unitialized###</state>
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- <name>ARM</name>
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- <name>ExePath</name>
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- <name>ObjPath</name>
- <state>Release\Obj</state>
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- <name>ListPath</name>
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- <version>17</version>
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- <state>0</state>
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- <name>Input variant</name>
- <version>1</version>
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- <option>
- <name>Input description</name>
- <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>
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- <option>
- <name>Output variant</name>
- <version>0</version>
- <state>3</state>
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- <option>
- <name>Output description</name>
- <state>No specifier a, A, no specifier n, no float nor long long, no flags.</state>
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- <name>GOutputBinary</name>
- <state>0</state>
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- <name>FPU</name>
- <version>1</version>
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- <name>OGCoreOrChip</name>
- <state>1</state>
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- <option>
- <name>GRuntimeLibSelect</name>
- <version>0</version>
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- <name>GRuntimeLibSelectSlave</name>
- <version>0</version>
- <state>1</state>
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- <name>RTDescription</name>
- <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
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- <name>GeneralMisraVerbose</name>
- <state>0</state>
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- <option>
- <name>OGChipSelectEditMenu</name>
- <state>STM32L152xB ST STM32L152xB</state>
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- <name>GenLowLevelInterface</name>
- <state>1</state>
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- <name>GEndianModeBE</name>
- <state>1</state>
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- <name>OGBufferedTerminalOutput</name>
- <state>1</state>
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- <name>GenStdoutInterface</name>
- <state>1</state>
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- <name>GeneralMisraRules98</name>
- <version>0</version>
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- <name>GeneralMisraVer</name>
- <state>0</state>
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- <version>0</version>
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- <name>RTConfigPath2</name>
- <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
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- <name>ICCARM</name>
- <archiveVersion>2</archiveVersion>
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- <version>26</version>
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- <option>
- <name>CCDefines</name>
- <state>USE_STM32L152_EVAL</state>
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- <state>0</state>
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- <state>0</state>
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- <name>CCPreprocLine</name>
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- <name>CCListCFile</name>
- <state>0</state>
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- <name>CCListCMnemonics</name>
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- <name>CCListCMessages</name>
- <state>0</state>
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- <name>CCListAssFile</name>
- <state>0</state>
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- <name>CCListAssSource</name>
- <state>0</state>
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- <name>CCEnableRemarks</name>
- <state>0</state>
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- <name>CCDiagSuppress</name>
- <state>Pa082</state>
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- <option>
- <name>CCDiagRemark</name>
- <state></state>
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- <name>CCDiagWarning</name>
- <state></state>
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- <name>CCDiagError</name>
- <state></state>
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- <name>CCObjPrefix</name>
- <state>1</state>
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- <version>1</version>
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- <name>CCDebugInfo</name>
- <state>1</state>
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- <state>1</state>
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- <name>IProcessor</name>
- <state>1</state>
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- <name>IExtraOptionsCheck</name>
- <state>0</state>
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- <name>IExtraOptions</name>
- <state></state>
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- <state>0</state>
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- <state>1</state>
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- <state>0</state>
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- <state>0</state>
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- <name>CCDiagWarnAreErr</name>
- <state>0</state>
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- <state>0</state>
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- <state>1</state>
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- <name>OutputFile</name>
- <state>$FILE_BNAME$.o</state>
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- <name>CCLibConfigHeader</name>
- <state>1</state>
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- <name>PreInclude</name>
- <state></state>
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- <state>0</state>
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- <name>CCIncludePath2</name>
- <state>$PROJ_DIR$\system_and_ST_code</state>
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- <name>CCCodeSection</name>
- <state>.text</state>
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- <name>CCOptLevel</name>
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- <name>CCOptStrategy</name>
- <version>0</version>
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- <name>CCOptLevelSlave</name>
- <state>3</state>
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- <name>CompilerMisraRules98</name>
- <version>0</version>
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- <version>0</version>
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- <state>0</state>
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- <name>CCPosIndRwpi</name>
- <state>0</state>
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- <option>
- <name>CCPosIndNoDynInit</name>
- <state>0</state>
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- <name>IccLang</name>
- <state>0</state>
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- <option>
- <name>IccCDialect</name>
- <state>1</state>
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- <option>
- <name>IccAllowVLA</name>
- <state>0</state>
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- <name>IccCppDialect</name>
- <state>1</state>
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- <option>
- <name>IccExceptions</name>
- <state>1</state>
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- <option>
- <name>IccRTTI</name>
- <state>1</state>
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- <option>
- <name>IccStaticDestr</name>
- <state>1</state>
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- <option>
- <name>IccRelaxedFpPrecision</name>
- <state>0</state>
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- <option>
- <name>IccCppInlineSemantics</name>
- <state>0</state>
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- <version>8</version>
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- <option>
- <name>AObjPrefix</name>
- <state>1</state>
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- <option>
- <name>AEndian</name>
- <state>1</state>
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- <state>1</state>
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- <name>AWarnWhat</name>
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- <name>AWarnOne</name>
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- <name>AWarnRange1</name>
- <state></state>
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- <state>0</state>
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- <state>1</state>
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- <name>AListing</name>
- <state>1</state>
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- <state>0</state>
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- <state>0</state>
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- <name>MacExps</name>
- <state>1</state>
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- <name>MacExec</name>
- <state>0</state>
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- <state>0</state>
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- </file>
- <file>
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- <file>
- <name>$PROJ_DIR$\serial.c</name>
- </file>
-</project>
-
-
diff --git a/Demo/_Cortex_STM32L152_IAR/RTOSDemo.eww b/Demo/_Cortex_STM32L152_IAR/RTOSDemo.eww
deleted file mode 100644
index 239a938..0000000
--- a/Demo/_Cortex_STM32L152_IAR/RTOSDemo.eww
+++ /dev/null
@@ -1,10 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<workspace>
- <project>
- <path>$WS_DIR$\RTOSDemo.ewp</path>
- </project>
- <batchBuild/>
-</workspace>
-
-
diff --git a/Demo/_Cortex_STM32L152_IAR/main.c b/Demo/_Cortex_STM32L152_IAR/main.c
deleted file mode 100644
index 694a8c3..0000000
--- a/Demo/_Cortex_STM32L152_IAR/main.c
+++ /dev/null
@@ -1,599 +0,0 @@
-/*
- FreeRTOS V6.1.0 - Copyright (C) 2010 Real Time Engineers Ltd.
-
- ***************************************************************************
- * *
- * If you are: *
- * *
- * + New to FreeRTOS, *
- * + Wanting to learn FreeRTOS or multitasking in general quickly *
- * + Looking for basic training, *
- * + Wanting to improve your FreeRTOS skills and productivity *
- * *
- * then take a look at the FreeRTOS books - available as PDF or paperback *
- * *
- * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
- * http://www.FreeRTOS.org/Documentation *
- * *
- * A pdf reference manual is also available. Both are usually delivered *
- * to your inbox within 20 minutes to two hours when purchased between 8am *
- * and 8pm GMT (although please allow up to 24 hours in case of *
- * exceptional circumstances). Thank you for your support! *
- * *
- ***************************************************************************
-
- This file is part of the FreeRTOS distribution.
-
- FreeRTOS is free software; you can redistribute it and/or modify it under
- the terms of the GNU General Public License (version 2) as published by the
- Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
- ***NOTE*** The exception to the GPL is included to allow you to distribute
- a combined work that includes FreeRTOS without being obliged to provide the
- source code for proprietary components outside of the FreeRTOS kernel.
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- more details. You should have received a copy of the GNU General Public
- License and the FreeRTOS license exception along with FreeRTOS; if not it
- can be viewed here: http://www.freertos.org/a00114.html and also obtained
- by writing to Richard Barry, contact details for whom are available on the
- FreeRTOS WEB site.
-
- 1 tab == 4 spaces!
-
- http://www.FreeRTOS.org - Documentation, latest information, license and
- contact details.
-
- http://www.SafeRTOS.com - A version that is certified for use in safety
- critical systems.
-
- http://www.OpenRTOS.com - Commercial support, development, porting,
- licensing and training services.
-*/
-
-/*
- * The documentation page for this demo available on http://www.FreeRTOS.org
- * documents the hardware configuration required to run this demo. It also
- * provides more information on the expected demo application behaviour.
- *
- * main() creates all the demo application tasks, then starts the scheduler.
- * A lot of the created tasks are from the pool of "standard demo" tasks. The
- * web documentation provides more details of the standard demo tasks, which
- * provide no particular functionality but do provide good examples of how to
- * use the FreeRTOS API.
- *
- * In addition to the standard demo tasks, the following tasks, interrupts and
- * tests are defined and/or created within this file:
- *
- * "LCD" task - The LCD task is a 'gatekeeper' task. It is the only task that
- * is permitted to access the LCD and therefore ensures access to the LCD is
- * always serialised and there are no mutual exclusion issues. When a task or
- * an interrupt wants to write to the LCD, it does not access the LCD directly
- * but instead sends the message to the LCD task. The LCD task then performs
- * the actual LCD output. This mechanism also allows interrupts to, in effect,
- * write to the LCD by sending messages to the LCD task.
- *
- * The LCD task is also a demonstration of a 'controller' task design pattern.
- * Some tasks do not actually send a string to the LCD task directly, but
- * instead send a command that is interpreted by the LCD task. In a normal
- * application these commands can be control values or set points, in this
- * simple example the commands just result in messages being displayed on the
- * LCD.
- *
- * "Button Poll" task - This task polls the state of the 'up' key on the
- * joystick input device. It uses the vTaskDelay() API function to control
- * the poll rate to ensure debouncing is not necessary and that the task does
- * not use all the available CPU processing time.
- *
- * Button Interrupt and run time stats display - The select button on the
- * joystick input device is configured to generate an external interrupt. The
- * handler for this interrupt sends a message to LCD task, which interprets the
- * message to mean, firstly write a message to the LCD, and secondly, generate
- * a table of run time statistics. The run time statistics are displayed as a
- * table that contains information on how much processing time each task has
- * been allocated since the application started to execute. This information
- * is provided both as an absolute time, and as a percentage of the total run
- * time. The information is displayed in the terminal IO window of the IAR
- * embedded workbench. The online documentation for this demo shows a screen
- * shot demonstrating where the run time stats can be viewed.
- *
- * Idle Hook - The idle hook is a function that is called on each iteration of
- * the idle task. In this case it is used to place the processor into a low
- * power mode. Note however that this application is implemented using standard
- * components, and is therefore not optimised for low power operation. Lower
- * power consumption would be achieved by converting polling tasks into event
- * driven tasks, and slowing the tick interrupt frequency.
- *
- * "Check" function called from the tick hook - The tick hook is called during
- * each tick interrupt. It is called from an interrupt context so must execute
- * quickly, not attempt to block, and not call any FreeRTOS API functions that
- * do not end in "FromISR". In this case the tick hook executes a 'check'
- * function. This only executes every five seconds. Its main function is to
- * check that all the standard demo tasks are still operational. Each time it
- * executes it sends a status code to the LCD task. The LCD task interprets the
- * code and displays an appropriate message - which will be PASS if no tasks
- * have reported any errors, or a message stating which task has reported an
- * error.
-*/
-
-/* Standard includes. */
-#include <stdio.h>
-
-/* Kernel includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "queue.h"
-
-/* Demo application includes. */
-#include "partest.h"
-#include "flash.h"
-#include "dynamic.h"
-#include "comtest2.h"
-#include "GenQTest.h"
-
-/* Eval board includes. */
-#include "stm32_eval.h"
-#include "stm32l152_eval_lcd.h"
-
-/* The priorities assigned to the tasks. */
-#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
-#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
-#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
-#define mainGENERIC_QUEUE_TEST_PRIORITY ( tskIDLE_PRIORITY )
-
-/* The length of the queue (the number of items the queue can hold) that is used
-to send messages from tasks and interrupts the the LCD task. */
-#define mainQUEUE_LENGTH ( 5 )
-
-/* Codes sent within messages to the LCD task so the LCD task can interpret
-exactly what the message it just received was. These are sent in the
-cMessageID member of the message structure (defined below). */
-#define mainMESSAGE_BUTTON_UP ( 1 )
-#define mainMESSAGE_BUTTON_SEL ( 2 )
-#define mainMESSAGE_STATUS ( 3 )
-
-/* When the cMessageID member of the message sent to the LCD task is
-mainMESSAGE_STATUS then these definitions are sent in the lMessageValue member
-of the same message and indicate what the status actually is. */
-#define mainERROR_DYNAMIC_TASKS ( pdPASS + 1 )
-#define mainERROR_COM_TEST ( pdPASS + 2 )
-#define mainERROR_GEN_QUEUE_TEST ( pdPASS + 3 )
-
-/* Baud rate used by the comtest tasks. */
-#define mainCOM_TEST_BAUD_RATE ( 115200 )
-
-/* The LED used by the comtest tasks. See the comtest.c file for more
-information. */
-#define mainCOM_TEST_LED ( 3 )
-
-/* The LCD task uses printf() so requires more stack than most of the other
-tasks. */
-#define mainLCD_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 )
-
-/*-----------------------------------------------------------*/
-
-/*
- * System configuration is performed prior to main() being called, this function
- * configures the peripherals used by the demo application.
- */
-static void prvSetupHardware( void );
-
-/*
- * Definition of the LCD/controller task described in the comments at the top
- * of this file.
- */
-static void prvLCDTask( void *pvParameters );
-
-/*
- * Definition of the button poll task described in the comments at the top of
- * this file.
- */
-static void prvButtonPollTask( void *pvParameters );
-
-/*
- * Converts a status message value into an appropriate string for display on
- * the LCD. The string is written to pcBuffer.
- */
-static void prvGenerateStatusMessage( char *pcBuffer, long lStatusValue );
-
-/*-----------------------------------------------------------*/
-
-/* The time base for the run time stats is generated by the 16 bit timer 6.
-Each time the timer overflows ulTIM6_OverflowCount is incremented. Therefore,
-when converting the total run time to a 32 bit number, the most significant two
-bytes are given by ulTIM6_OverflowCount and the least significant two bytes are
-given by the current TIM6 counter value. Care must be taken with data
-consistency when combining the two in case a timer overflow occurs as the
-value is being read. */
-unsigned long ulTIM6_OverflowCount = 0UL;
-
-/* The handle of the queue used to send messages from tasks and interrupts to
-the LCD task. */
-static xQueueHandle xLCDQueue = NULL;
-
-/* The definition of each message sent from tasks and interrupts to the LCD
-task. */
-typedef struct
-{
- char cMessageID; /* << States what the message is. */
- long lMessageValue; /* << States the message value (can be an integer, string pointer, etc. depending on the value of cMessageID). */
-} xQueueMessage;
-
-/*-----------------------------------------------------------*/
-
-void main( void )
-{
- /* Configure the peripherals used by this demo application. This includes
- configuring the joystick input select button to generate interrupts. */
- prvSetupHardware();
-
- /* Create the queue used by tasks and interrupts to send strings to the LCD
- task. */
- xLCDQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( xQueueMessage ) );
-
- /* If the queue could not be created then don't create any tasks that might
- attempt to use the queue. */
- if( xLCDQueue != NULL )
- {
- /* Add the created queue to the queue registry so it can be viewed in
- the IAR FreeRTOS state viewer plug-in. */
- vQueueAddToRegistry( xLCDQueue, "LCDQueue" );
-
- /* Create the LCD and button poll tasks, as described at the top of this
- file. */
- xTaskCreate( prvLCDTask, ( signed char * ) "LCD", mainLCD_TASK_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL );
- xTaskCreate( prvButtonPollTask, ( signed char * ) "ButPoll", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
-
- /* Create a subset of the standard demo tasks. */
- vStartDynamicPriorityTasks();
- vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY );
- vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
- vStartGenericQueueTasks( mainGENERIC_QUEUE_TEST_PRIORITY );
-
- /* Start the scheduler. */
- vTaskStartScheduler();
- }
-
- /* If all is well then this line will never be reached. If it is reached
- then it is likely that there was insufficient (FreeRTOS) heap memory space
- to create the idle task. This may have been trapped by the malloc() failed
- hook function, if one is configured. */
- for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-static void prvLCDTask( void *pvParameters )
-{
-xQueueMessage xReceivedMessage;
-long lLine = Line1;
-const long lFontHeight = (((sFONT *)LCD_GetFont())->Height);
-
-/* Buffer into which strings are formatted and placed ready for display on the
-LCD. Note this is a static variable to prevent it being allocated on the task
-stack, which is too small to hold such a variable. The stack size is configured
-when the task is created. */
-static char cBuffer[ 512 ];
-
- /* This function is the only function that uses printf(). If printf() is
- used from any other function then some sort of mutual exclusion on stdout
- will be necessary.
-
- This is also the only function that is permitted to access the LCD.
-
- First print out the number of bytes that remain in the FreeRTOS heap. This
- can be viewed in the terminal IO window within the IAR Embedded Workbench. */
- printf( "%d bytes of heap space remain unallocated\n", xPortGetFreeHeapSize() );
-
- for( ;; )
- {
- /* Wait for a message to be received. Using portMAX_DELAY as the block
- time will result in an indefinite wait provided INCLUDE_vTaskSuspend is
- set to 1 in FreeRTOSConfig.h, therefore there is no need to check the
- function return value and the function will only return when a value
- has been received. */
- xQueueReceive( xLCDQueue, &xReceivedMessage, portMAX_DELAY );
-
- /* Clear the LCD if no room remains for any more text output. */
- if( lLine > Line9 )
- {
- LCD_Clear( Blue );
- lLine = 0;
- }
-
- /* What is this message? What does it contain? */
- switch( xReceivedMessage.cMessageID )
- {
- case mainMESSAGE_BUTTON_UP : /* The button poll task has just
- informed this task that the up
- button on the joystick input has
- been pressed or released. */
- sprintf( cBuffer, "Button up = %d", xReceivedMessage.lMessageValue );
- break;
-
- case mainMESSAGE_BUTTON_SEL : /* The select button interrupt
- just informed this task that the
- select button was pressed.
- Generate a table of task run time
- statistics and output this to
- the terminal IO window in the IAR
- embedded workbench. */
- printf( "\nTask\t Abs Time\t %%Time\n*****************************************" );
- vTaskGetRunTimeStats( ( signed char * ) cBuffer );
- printf( cBuffer );
-
- /* Also print out a message to
- the LCD - in this case the
- pointer to the string to print
- is sent directly in the
- lMessageValue member of the
- message. This just demonstrates
- a different communication
- technique. */
- sprintf( cBuffer, "%s", ( char * ) xReceivedMessage.lMessageValue );
- break;
-
- case mainMESSAGE_STATUS : /* The tick interrupt hook
- function has just informed this
- task of the system status.
- Generate a string in accordance
- with the status value. */
- prvGenerateStatusMessage( cBuffer, xReceivedMessage.lMessageValue );
- break;
-
- default : sprintf( cBuffer, "Unknown message" );
- break;
- }
-
- /* Output the message that was placed into the cBuffer array within the
- switch statement above. */
- LCD_DisplayStringLine( lLine, ( uint8_t * ) cBuffer );
-
- /* Move onto the next LCD line, ready for the next iteration of this
- loop. */
- lLine += lFontHeight;
- }
-}
-/*-----------------------------------------------------------*/
-
-static void prvGenerateStatusMessage( char *pcBuffer, long lStatusValue )
-{
- /* Just a utility function to convert a status value into a meaningful
- string for output onto the LCD. */
- switch( lStatusValue )
- {
- case pdPASS : sprintf( pcBuffer, "Task status = PASS" );
- break;
- case mainERROR_DYNAMIC_TASKS : sprintf( pcBuffer, "Error: Dynamic tasks" );
- break;
- case mainERROR_COM_TEST : sprintf( pcBuffer, "Err: loop connected?" ); /* Error in COM test - is the Loopback connector connected? */
- break;
- case mainERROR_GEN_QUEUE_TEST : sprintf( pcBuffer, "Error: Gen Q test" );
- break;
- default : sprintf( pcBuffer, "Unknown status" );
- break;
- }
-}
-/*-----------------------------------------------------------*/
-
-void EXTI9_5_IRQHandler( void )
-{
-/* Define the message sent to the LCD task from this interrupt. */
-const xQueueMessage xMessage = { mainMESSAGE_BUTTON_SEL, ( unsigned long ) "Select Interrupt!" };
-long lHigherPriorityTaskWoken = pdFALSE;
-
- /* This is the interrupt handler for the joystick select button input.
- The button has been pushed, write a message to the LCD via the LCD task. */
- xQueueSendFromISR( xLCDQueue, &xMessage, &lHigherPriorityTaskWoken );
-
- EXTI_ClearITPendingBit( SEL_BUTTON_EXTI_LINE );
-
- /* If writing to xLCDQueue caused a task to unblock, and the unblocked task
- has a priority equal to or above the task that this interrupt interrupted,
- then lHigherPriorityTaskWoken will have been set to pdTRUE internally within
- xQueuesendFromISR(), and portEND_SWITCHING_ISR() will ensure that this
- interrupt returns directly to the higher priority unblocked task. */
- portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );
-}
-/*-----------------------------------------------------------*/
-
-void vApplicationTickHook( void )
-{
-static unsigned long ulCounter = 0;
-static const unsigned long ulCheckFrequency = 5000UL / portTICK_RATE_MS;
-long lHigherPriorityTaskWoken = pdFALSE;
-
-/* Define the status message that is sent to the LCD task. By default the
-status is PASS. */
-static xQueueMessage xStatusMessage = { mainMESSAGE_STATUS, pdPASS };
-
- /* This is called from within the tick interrupt and performs the 'check'
- functionality as described in the comments at the top of this file.
-
- Is it time to perform the 'check' functionality again? */
- ulCounter++;
- if( ulCounter >= ulCheckFrequency )
- {
- /* See if the standard demo tasks are executing as expected, changing
- the message that is sent to the LCD task from PASS to an error code if
- any tasks set reports an error. */
- if( xAreDynamicPriorityTasksStillRunning() != pdPASS )
- {
- xStatusMessage.lMessageValue = mainERROR_DYNAMIC_TASKS;
- }
-
- if( xAreComTestTasksStillRunning() != pdPASS )
- {
- xStatusMessage.lMessageValue = mainERROR_COM_TEST;
- }
-
- if( xAreGenericQueueTasksStillRunning() != pdPASS )
- {
- xStatusMessage.lMessageValue = mainERROR_GEN_QUEUE_TEST;
- }
-
- /* As this is the tick hook the lHigherPriorityTaskWoken parameter is not
- needed (a context switch is going to be performed anyway), but it must
- still be provided. */
- xQueueSendFromISR( xLCDQueue, &xStatusMessage, &lHigherPriorityTaskWoken );
- ulCounter = 0;
- }
-}
-/*-----------------------------------------------------------*/
-
-static void prvButtonPollTask( void *pvParameters )
-{
-long lLastState = pdTRUE;
-long lState;
-xQueueMessage xMessage;
-
- /* This tasks performs the button polling functionality as described at the
- top of this file. */
- for( ;; )
- {
- /* Check the button state. */
- lState = STM_EVAL_PBGetState( BUTTON_UP );
- if( lState != lLastState )
- {
- /* The state has changed, send a message to the LCD task. */
- xMessage.cMessageID = mainMESSAGE_BUTTON_UP;
- xMessage.lMessageValue = lState;
- lLastState = lState;
- xQueueSend( xLCDQueue, &xMessage, portMAX_DELAY );
- }
-
- /* Block for 10 milliseconds so this task does not utilise all the CPU
- time and debouncing of the button is not necessary. */
- vTaskDelay( 10 / portTICK_RATE_MS );
- }
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupHardware( void )
-{
- /* Ensure that all 4 interrupt priority bits are used as the pre-emption
- priority. */
- NVIC_PriorityGroupConfig( NVIC_PriorityGroup_4 );
-
- /* Initialise the LEDs. */
- vParTestInitialise();
-
- /* Initialise the joystick inputs. */
- STM_EVAL_PBInit( BUTTON_UP, BUTTON_MODE_GPIO );
- STM_EVAL_PBInit( BUTTON_DOWN, BUTTON_MODE_GPIO );
- STM_EVAL_PBInit( BUTTON_LEFT, BUTTON_MODE_GPIO );
- STM_EVAL_PBInit( BUTTON_RIGHT, BUTTON_MODE_GPIO );
-
- /* The select button in the middle of the joystick is configured to generate
- an interrupt. The Eval board library will configure the interrupt
- priority to be the lowest priority available so the priority need not be
- set here explicitly. It is important that the priority is equal to or
- below that set by the configMAX_SYSCALL_INTERRUPT_PRIORITY value set in
- FreeRTOSConfig.h. */
- STM_EVAL_PBInit( BUTTON_SEL, BUTTON_MODE_EXTI );
-
- /* Initialize the LCD */
- STM32L152_LCD_Init();
- LCD_Clear( Blue );
- LCD_SetBackColor( Blue );
- LCD_SetTextColor( White );
- LCD_DisplayStringLine( Line0, " www.FreeRTOS.org" );
-}
-/*-----------------------------------------------------------*/
-
-void vConfigureTimerForRunTimeStats( void )
-{
-TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
-NVIC_InitTypeDef NVIC_InitStructure;
-
- /* The time base for the run time stats is generated by the 16 bit timer 6.
- Each time the timer overflows ulTIM6_OverflowCount is incremented.
- Therefore, when converting the total run time to a 32 bit number, the most
- significant two bytes are given by ulTIM6_OverflowCount and the least
- significant two bytes are given by the current TIM6 counter value. Care
- must be taken with data consistency when combining the two in case a timer
- overflow occurs as the value is being read.
-
- The portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro (in FreeRTOSConfig.h) is
- defined to call this function, so the kernel will call this function
- automatically at the appropriate time. */
-
- /* TIM6 clock enable */
- RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM6, ENABLE );
-
- /* The 32MHz clock divided by 5000 should tick (very) approximately every
- 150uS and overflow a 16bit timer (very) approximately every 10 seconds. */
- TIM_TimeBaseStructure.TIM_Period = 65535;
- TIM_TimeBaseStructure.TIM_Prescaler = 5000;
- TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
- TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
-
- TIM_TimeBaseInit( TIM6, &TIM_TimeBaseStructure );
-
- /* Only interrupt on overflow events. */
- TIM6->CR1 |= TIM_CR1_URS;
-
- /* Enable the interrupt. */
- TIM_ITConfig( TIM6, TIM_IT_Update, ENABLE );
-
- /* Enable the TIM6 global Interrupt */
- NVIC_InitStructure.NVIC_IRQChannel = TIM6_IRQn;
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = configLIBRARY_LOWEST_INTERRUPT_PRIORITY;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x00; /* Not used as 4 bits are used for the pre-emption priority. */
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init(&NVIC_InitStructure);
-
- TIM_ClearITPendingBit( TIM6, TIM_IT_Update );
- TIM_Cmd( TIM6, ENABLE );
-}
-/*-----------------------------------------------------------*/
-
-void TIM6_IRQHandler( void )
-{
- /* Interrupt handler for TIM 6
-
- The time base for the run time stats is generated by the 16 bit timer 6.
- Each time the timer overflows ulTIM6_OverflowCount is incremented.
- Therefore, when converting the total run time to a 32 bit number, the most
- significant two bytes are given by ulTIM6_OverflowCount and the least
- significant two bytes are given by the current TIM6 counter value. Care
- must be taken with data consistency when combining the two in case a timer
- overflow occurs as the value is being read. */
- if( TIM_GetITStatus( TIM6, TIM_IT_Update) != RESET)
- {
- ulTIM6_OverflowCount++;
- TIM_ClearITPendingBit( TIM6, TIM_IT_Update );
- }
-}
-/*-----------------------------------------------------------*/
-
-void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )
-{
- ( void ) pcTaskName;
- ( void ) pxTask;
-
- /* Run time stack overflow checking is performed if
- configconfigCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
- function is called if a stack overflow is detected. */
- for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-void vApplicationMallocFailedHook( void )
-{
- /* Called if a call to pvPortMalloc() fails because there is insufficient
- free memory available in the FreeRTOS heap. pvPortMalloc() is called
- internally by FreeRTOS API functions that create tasks, queues or
- semaphores. */
- for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-void vApplicationIdleHook( void )
-{
- /* Called on each iteration of the idle task. In this case the idle task
- just enters a low(ish) power mode. */
- PWR_EnterSleepMode( PWR_Regulator_ON, PWR_SLEEPEntry_WFI );
-}
-
-
-
diff --git a/Demo/_Cortex_STM32L152_IAR/serial.c b/Demo/_Cortex_STM32L152_IAR/serial.c
deleted file mode 100644
index 0668d49..0000000
--- a/Demo/_Cortex_STM32L152_IAR/serial.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- FreeRTOS V6.1.0 - Copyright (C) 2010 Real Time Engineers Ltd.
-
- ***************************************************************************
- * *
- * If you are: *
- * *
- * + New to FreeRTOS, *
- * + Wanting to learn FreeRTOS or multitasking in general quickly *
- * + Looking for basic training, *
- * + Wanting to improve your FreeRTOS skills and productivity *
- * *
- * then take a look at the FreeRTOS books - available as PDF or paperback *
- * *
- * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
- * http://www.FreeRTOS.org/Documentation *
- * *
- * A pdf reference manual is also available. Both are usually delivered *
- * to your inbox within 20 minutes to two hours when purchased between 8am *
- * and 8pm GMT (although please allow up to 24 hours in case of *
- * exceptional circumstances). Thank you for your support! *
- * *
- ***************************************************************************
-
- This file is part of the FreeRTOS distribution.
-
- FreeRTOS is free software; you can redistribute it and/or modify it under
- the terms of the GNU General Public License (version 2) as published by the
- Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
- ***NOTE*** The exception to the GPL is included to allow you to distribute
- a combined work that includes FreeRTOS without being obliged to provide the
- source code for proprietary components outside of the FreeRTOS kernel.
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- more details. You should have received a copy of the GNU General Public
- License and the FreeRTOS license exception along with FreeRTOS; if not it
- can be viewed here: http://www.freertos.org/a00114.html and also obtained
- by writing to Richard Barry, contact details for whom are available on the
- FreeRTOS WEB site.
-
- 1 tab == 4 spaces!
-
- http://www.FreeRTOS.org - Documentation, latest information, license and
- contact details.
-
- http://www.SafeRTOS.com - A version that is certified for use in safety
- critical systems.
-
- http://www.OpenRTOS.com - Commercial support, development, porting,
- licensing and training services.
-*/
-
-/*
- BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
-
- ***Note*** This example uses queues to send each character into an interrupt
- service routine and out of an interrupt service routine individually. This
- is done to demonstrate queues being used in an interrupt, and to deliberately
- load the system to test the FreeRTOS port. It is *NOT* meant to be an
- example of an efficient implementation. An efficient implementation should
- use FIFO's or DMA if available, and only use FreeRTOS API functions when
- enough has been received to warrant a task being unblocked to process the
- data.
-*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "queue.h"
-#include "semphr.h"
-#include "comtest2.h"
-
-/* Library includes. */
-#include "stm32l152_eval.h"
-
-/* Demo application includes. */
-#include "serial.h"
-/*-----------------------------------------------------------*/
-
-/* Misc defines. */
-#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )
-#define serNO_BLOCK ( ( portTickType ) 0 )
-
-/*-----------------------------------------------------------*/
-
-/* The queue used to hold received characters. */
-static xQueueHandle xRxedChars;
-static xQueueHandle xCharsForTx;
-
-/*-----------------------------------------------------------*/
-
-/*
- * See the serial2.h header file.
- */
-xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
-{
-USART_InitTypeDef USART_InitStructure;
-xComPortHandle xReturn;
-NVIC_InitTypeDef NVIC_InitStructure;
-
- /* Create the queues used to hold Rx/Tx characters. */
- xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
- xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
-
- /* If the queues were created correctly then setup the serial port
- hardware. */
- if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )
- {
- USART_InitStructure.USART_BaudRate = ulWantedBaud;
- USART_InitStructure.USART_WordLength = USART_WordLength_8b;
- USART_InitStructure.USART_StopBits = USART_StopBits_1;
- USART_InitStructure.USART_Parity = USART_Parity_No;
- USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
- USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-
- /* The Eval board COM2 is being used, which in reality is the STM32
- USART3. */
- STM_EVAL_COMInit( COM2, &USART_InitStructure );
-
- NVIC_InitStructure.NVIC_IRQChannel = USART3_IRQn;
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; /* Not used as 4 bits are used for the pre-emption priority. */;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init( &NVIC_InitStructure );
- USART_ITConfig( USART3, USART_IT_RXNE, ENABLE );
- }
- else
- {
- xReturn = ( xComPortHandle ) 0;
- }
-
- /* This demo file only supports a single port but we have to return
- something to comply with the standard demo header file. */
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
-{
- /* The port handle is not required as this driver only supports one port. */
- ( void ) pxPort;
-
- /* Get the next character from the buffer. Return false if no characters
- are available, or arrive before xBlockTime expires. */
- if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
- {
- return pdTRUE;
- }
- else
- {
- return pdFALSE;
- }
-}
-/*-----------------------------------------------------------*/
-
-void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )
-{
-signed portCHAR *pxNext;
-
- /* A couple of parameters that this port does not use. */
- ( void ) usStringLength;
- ( void ) pxPort;
-
- /* NOTE: This implementation does not handle the queue being full as no
- block time is used! */
-
- /* The port handle is not required as this driver only supports UART1. */
- ( void ) pxPort;
-
- /* Send each character in the string, one at a time. */
- pxNext = ( signed portCHAR * ) pcString;
- while( *pxNext )
- {
- xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
- pxNext++;
- }
-}
-/*-----------------------------------------------------------*/
-
-signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
-{
-signed portBASE_TYPE xReturn;
-
- if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) == pdPASS )
- {
- xReturn = pdPASS;
- USART_ITConfig( USART3, USART_IT_TXE, ENABLE );
- }
- else
- {
- xReturn = pdFAIL;
- }
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vSerialClose( xComPortHandle xPort )
-{
- /* Not supported as not required by the demo application. */
-}
-/*-----------------------------------------------------------*/
-
-void USART3_IRQHandler( void )
-{
-portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
-portCHAR cChar;
-
- if( USART_GetITStatus( USART3, USART_IT_TXE ) == SET )
- {
- /* The interrupt was caused by the TX register becoming empty. Are
- there any more characters to transmit? */
- if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
- {
- /* A character was retrieved from the queue so can be sent to the
- USART now. */
- USART_SendData( USART3, cChar );
- }
- else
- {
- USART_ITConfig( USART3, USART_IT_TXE, DISABLE );
- }
- }
-
- if( USART_GetITStatus( USART3, USART_IT_RXNE ) == SET )
- {
- /* A character has been received on the USART, send it to the Rx
- handler task. */
- cChar = USART_ReceiveData( USART3 );
- xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
- }
-
- /* If sending or receiving from a queue has caused a task to unblock, and
- the unblocked task has a priority equal to or higher than the currently
- running task (the task this ISR interrupted), then xHigherPriorityTaskWoken
- will have automatically been set to pdTRUE within the queue send or receive
- function. portEND_SWITCHING_ISR() will then ensure that this ISR returns
- directly to the higher priority unblocked task. */
- portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
-}
-
-
-
-
-
-
diff --git a/Demo/_Cortex_STM32L152_IAR/settings/RTOSDemo.cspy.bat b/Demo/_Cortex_STM32L152_IAR/settings/RTOSDemo.cspy.bat
deleted file mode 100644
index b4f2a0c..0000000
--- a/Demo/_Cortex_STM32L152_IAR/settings/RTOSDemo.cspy.bat
+++ /dev/null
@@ -1,15 +0,0 @@
-@REM This batch file has been generated by the IAR Embedded Workbench
-@REM C-SPY Debugger, as an aid to preparing a command line for running
-@REM the cspybat command line utility using the appropriate settings.
-@REM
-@REM You can launch cspybat by typing the name of this batch file followed
-@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
-@REM Note that this file is generated every time a new debug session
-@REM is initialized, so you may want to move or rename the file before
-@REM making changes.
-@REM
-
-
-"C:\devtools\IAR Systems\Embedded Workbench 6.0\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armjlink.dll" %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armbat.dll" --flash_loader "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\config\flashloader\ST\FlashSTM32L15xxB.board" --backend -B "--endian=little" "--cpu=Cortex-M3" "--fpu=None" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\CONFIG\debugger\ST\iostm32l152xx.ddf" "--semihosting" "--device=STM32L152xB" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--jlink_interface=SWD" "--drv_catch_exceptions=0x000"
-
-
diff --git a/Demo/_Cortex_STM32L152_IAR/settings/RTOSDemo.dbgdt b/Demo/_Cortex_STM32L152_IAR/settings/RTOSDemo.dbgdt
deleted file mode 100644
index cf214cc..0000000
--- a/Demo/_Cortex_STM32L152_IAR/settings/RTOSDemo.dbgdt
+++ /dev/null
@@ -1,68 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<Project>
- <Desktop>
- <Static>
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- </Desktop>
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-
-
diff --git a/Demo/_Cortex_STM32L152_IAR/settings/RTOSDemo.dni b/Demo/_Cortex_STM32L152_IAR/settings/RTOSDemo.dni
deleted file mode 100644
index 5764d41..0000000
--- a/Demo/_Cortex_STM32L152_IAR/settings/RTOSDemo.dni
+++ /dev/null
@@ -1,105 +0,0 @@
-[DebugChecksum]
-Checksum=1802430239
-[DisAssemblyWindow]
-NumStates=_ 1
-State 1=_ 1
-[InstructionProfiling]
-Enabled=_ 0
-[CodeCoverage]
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-[Profiling]
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-[StackPlugin]
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-[SWOTraceHWSettings]
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-ITMlogFile=$PROJ_DIR$\ITM.log
-[Interrupts]
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-[MemoryMap]
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-UnspecRange=1
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-[TraceHelper]
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-[InterruptLog]
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-[PowerLog]
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-Title0=Power [mA]
-Setup0=0 1 0 500 2 0 4 1 0
-[Log file]
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-LogFile=_ ""
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-[TermIOLog]
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-LogFile=_ ""
-[SWOTraceWindow]
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-[TraceHelperExtra]
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-[CallStackLog]
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-[DriverProfiling]
-Enabled=0
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-[Disassemble mode]
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-[Breakpoints]
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-[Aliases]
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diff --git a/Demo/_Cortex_STM32L152_IAR/settings/RTOSDemo.wsdt b/Demo/_Cortex_STM32L152_IAR/settings/RTOSDemo.wsdt
deleted file mode 100644
index b4f7f17..0000000
--- a/Demo/_Cortex_STM32L152_IAR/settings/RTOSDemo.wsdt
+++ /dev/null
@@ -1,49 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<Workspace>
- <ConfigDictionary>
-
- <CurrentConfigs><Project>RTOSDemo/Debug</Project></CurrentConfigs></ConfigDictionary>
- <Desktop>
- <Static>
- <Workspace>
- <ColumnWidths>
-
-
-
-
- <Column0>364</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
- </Workspace>
- <Build><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build><TerminalIO/><Debug-Log><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log></Static>
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-
- <Wnd2>
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- <Tab>
- <Identity>TabID-27630-4718</Identity>
- <TabName>Workspace</TabName>
- <Factory>Workspace</Factory>
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-
- <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode></NodeDict></Session>
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-
- <SelectedTab>0</SelectedTab></Wnd2><Wnd3><Tabs><Tab><Identity>TabID-10002-7709</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab><Tab><Identity>TabID-18437-21512</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>
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diff --git a/Demo/_Cortex_STM32L152_IAR/settings/RTOSDemo_Debug.jlink b/Demo/_Cortex_STM32L152_IAR/settings/RTOSDemo_Debug.jlink
deleted file mode 100644
index 228ff82..0000000
--- a/Demo/_Cortex_STM32L152_IAR/settings/RTOSDemo_Debug.jlink
+++ /dev/null
@@ -1,23 +0,0 @@
-[BREAKPOINTS]
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diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/CoreSupport/core_cm3.c b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/CoreSupport/core_cm3.c
deleted file mode 100644
index 56fddc5..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/CoreSupport/core_cm3.c
+++ /dev/null
@@ -1,784 +0,0 @@
-/**************************************************************************//**
- * @file core_cm3.c
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
- * @version V1.30
- * @date 30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#include <stdint.h>
-
-/* define compiler specific symbols */
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-__ASM uint32_t __get_PSP(void)
-{
- mrs r0, psp
- bx lr
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
- msr psp, r0
- bx lr
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-__ASM uint32_t __get_MSP(void)
-{
- mrs r0, msp
- bx lr
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
- msr msp, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-__ASM uint32_t __REV16(uint16_t value)
-{
- rev16 r0, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-__ASM int32_t __REVSH(int16_t value)
-{
- revsh r0, r0
- bx lr
-}
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-__ASM void __CLREX(void)
-{
- clrex
-}
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-__ASM uint32_t __get_BASEPRI(void)
-{
- mrs r0, basepri
- bx lr
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-__ASM void __set_BASEPRI(uint32_t basePri)
-{
- msr basepri, r0
- bx lr
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-__ASM uint32_t __get_PRIMASK(void)
-{
- mrs r0, primask
- bx lr
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
- msr primask, r0
- bx lr
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-__ASM uint32_t __get_FAULTMASK(void)
-{
- mrs r0, faultmask
- bx lr
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-__ASM void __set_FAULTMASK(uint32_t faultMask)
-{
- msr faultmask, r0
- bx lr
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-__ASM uint32_t __get_CONTROL(void)
-{
- mrs r0, control
- bx lr
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-__ASM void __set_CONTROL(uint32_t control)
-{
- msr control, r0
- bx lr
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#pragma diag_suppress=Pe940
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void)
-{
- __ASM("mrs r0, psp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM("msr psp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
- __ASM("mrs r0, msp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM("msr msp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- __ASM("rev16 r0, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
- __ASM("rbit r0, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
- __ASM("ldrexb r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
- __ASM("ldrexh r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
- __ASM("ldrex r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- __ASM("strexb r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- __ASM("strexh r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- __ASM("strex r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void) __attribute__( ( naked ) );
-uint32_t __get_PSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, psp\n\t"
- "MOV r0, %0 \n\t"
- "BX lr \n\t" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0\n\t"
- "BX lr \n\t" : : "r" (topOfProcStack) );
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void) __attribute__( ( naked ) );
-uint32_t __get_MSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, msp\n\t"
- "MOV r0, %0 \n\t"
- "BX lr \n\t" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0\n\t"
- "BX lr \n\t" : : "r" (topOfMainStack) );
-}
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-uint32_t __get_BASEPRI(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-uint32_t __get_PRIMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-uint32_t __get_FAULTMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-uint32_t __get_CONTROL(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in integer value
- */
-uint32_t __REV(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-int32_t __REVSH(int16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
- uint8_t result=0;
-
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
- uint16_t result=0;
-
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/CoreSupport/core_cm3.h b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/CoreSupport/core_cm3.h
deleted file mode 100644
index 2c46056..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/CoreSupport/core_cm3.h
+++ /dev/null
@@ -1,1818 +0,0 @@
-/**************************************************************************//**
- * @file core_cm3.h
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version V1.30
- * @date 30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CM3_CORE_H__
-#define __CM3_CORE_H__
-
-/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
- *
- * List of Lint messages which will be suppressed and not shown:
- * - Error 10: \n
- * register uint32_t __regBasePri __asm("basepri"); \n
- * Error 10: Expecting ';'
- * .
- * - Error 530: \n
- * return(__regBasePri); \n
- * Warning 530: Symbol '__regBasePri' (line 264) not initialized
- * .
- * - Error 550: \n
- * __regBasePri = (basePri & 0x1ff); \n
- * Warning 550: Symbol '__regBasePri' (line 271) not accessed
- * .
- * - Error 754: \n
- * uint32_t RESERVED0[24]; \n
- * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
- * .
- * - Error 750: \n
- * #define __CM3_CORE_H__ \n
- * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
- * .
- * - Error 528: \n
- * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
- * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
- * .
- * - Error 751: \n
- * } InterruptType_Type; \n
- * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
- * .
- * Note: To re-enable a Message, insert a space before 'lint' *
- *
- */
-
-/*lint -save */
-/*lint -e10 */
-/*lint -e530 */
-/*lint -e550 */
-/*lint -e754 */
-/*lint -e750 */
-/*lint -e528 */
-/*lint -e751 */
-
-
-/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
- This file defines all structures and symbols for CMSIS core:
- - CMSIS version number
- - Cortex-M core registers and bitfields
- - Cortex-M core peripheral base address
- @{
- */
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x03) /*!< Cortex core */
-
-#include <stdint.h> /* Include standard types */
-
-#if defined (__ICCARM__)
- #include <intrinsics.h> /* IAR Intrinsics */
-#endif
-
-
-#ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
-#endif
-
-
-
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
- */
-
-#ifdef __cplusplus
- #define __I volatile /*!< defines 'read only' permissions */
-#else
- #define __I volatile const /*!< defines 'read only' permissions */
-#endif
-#define __O volatile /*!< defines 'write only' permissions */
-#define __IO volatile /*!< defines 'read / write' permissions */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- ******************************************************************************/
-/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
- @{
-*/
-
-
-/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
- memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
- @{
- */
-typedef struct
-{
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644];
- __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */
-} NVIC_Type;
-/*@}*/ /* end of group CMSIS_CM3_NVIC */
-
-
-/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
- memory mapped structure for System Control Block (SCB)
- @{
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */
- __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */
- __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */
- __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */
- __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */
- __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */
- __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */
- __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */
- __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */
- __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */
- __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */
- __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */
- __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */
- __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
-/*@}*/ /* end of group CMSIS_CM3_SCB */
-
-
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
- memory mapped structure for SysTick
- @{
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-/*@}*/ /* end of group CMSIS_CM3_SysTick */
-
-
-/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
- memory mapped structure for Instrumentation Trace Macrocell (ITM)
- @{
- */
-typedef struct
-{
- __O union
- {
- __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */
- __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */
- __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */
- } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
- __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */
- uint32_t RESERVED1[15];
- __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
- __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */
- uint32_t RESERVED3[29];
- __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */
- __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */
- __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */
- uint32_t RESERVED4[43];
- __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */
- __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */
- uint32_t RESERVED5[6];
- __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */
- __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */
- __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */
- __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */
- __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */
- __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */
- __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */
- __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */
- __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */
- __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */
- __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */
- __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
-/*@}*/ /* end of group CMSIS_CM3_ITM */
-
-
-/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
- memory mapped structure for Interrupt Type
- @{
- */
-typedef struct
-{
- uint32_t RESERVED0;
- __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
- __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */
-#else
- uint32_t RESERVED1;
-#endif
-} InterruptType_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */
-#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */
-#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */
-
-#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */
-#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */
-
-#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */
-#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */
-/*@}*/ /* end of group CMSIS_CM3_InterruptType */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
-/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
- memory mapped structure for Memory Protection Unit (MPU)
- @{
- */
-typedef struct
-{
- __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */
- __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */
- __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */
- __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */
- __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */
- __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */
- __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */
-#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */
-
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */
-#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */
-
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */
-#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */
-
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */
-#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */
-
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */
-#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */
-
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */
-#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */
-
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@}*/ /* end of group CMSIS_CM3_MPU */
-#endif
-
-
-/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
- memory mapped structure for Core Debug Register
- @{
- */
-typedef struct
-{
- __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-/*@}*/ /* end of group CMSIS_CM3_CoreDebug */
-
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000) /*!< ITM Base Address */
-#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
-
-#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
-#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
-#endif
-
-/*@}*/ /* end of group CMSIS_CM3_core_register */
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- ******************************************************************************/
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#define __enable_fault_irq __enable_fiq
-#define __disable_fault_irq __disable_fiq
-
-#define __NOP __nop
-#define __WFI __wfi
-#define __WFE __wfe
-#define __SEV __sev
-#define __ISB() __isb(0)
-#define __DSB() __dsb(0)
-#define __DMB() __dmb(0)
-#define __REV __rev
-#define __RBIT __rbit
-#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
-#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
-#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
-#define __STREXB(value, ptr) __strex(value, ptr)
-#define __STREXH(value, ptr) __strex(value, ptr)
-#define __STREXW(value, ptr) __strex(value, ptr)
-
-
-/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
-/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
-/* intrinsic void __enable_irq(); */
-/* intrinsic void __disable_irq(); */
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-extern void __CLREX(void);
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-#else /* (__ARMCC_VERSION >= 400000) */
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-#define __CLREX __clrex
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-static __INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return(__regBasePri);
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-static __INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0xff);
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-static __INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return(__regFaultMask);
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & 1);
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-static __INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
-#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
-
-static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
-static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
-
-#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */
-static __INLINE void __WFI() { __ASM ("wfi"); }
-static __INLINE void __WFE() { __ASM ("wfe"); }
-static __INLINE void __SEV() { __ASM ("sev"); }
-static __INLINE void __CLREX() { __ASM ("clrex"); }
-
-/* intrinsic void __ISB(void) */
-/* intrinsic void __DSB(void) */
-/* intrinsic void __DMB(void) */
-/* intrinsic void __set_PRIMASK(); */
-/* intrinsic void __get_PRIMASK(); */
-/* intrinsic void __set_FAULTMASK(); */
-/* intrinsic void __get_FAULTMASK(); */
-/* intrinsic uint32_t __REV(uint32_t value); */
-/* intrinsic uint32_t __REVSH(uint32_t value); */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
-/* intrinsic unsigned long __LDREX(unsigned long *); */
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
-static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
-
-static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
-static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
-
-static __INLINE void __NOP() { __ASM volatile ("nop"); }
-static __INLINE void __WFI() { __ASM volatile ("wfi"); }
-static __INLINE void __WFE() { __ASM volatile ("wfe"); }
-static __INLINE void __SEV() { __ASM volatile ("sev"); }
-static __INLINE void __ISB() { __ASM volatile ("isb"); }
-static __INLINE void __DSB() { __ASM volatile ("dsb"); }
-static __INLINE void __DMB() { __ASM volatile ("dmb"); }
-static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in integer value
- */
-extern uint32_t __REV(uint32_t value);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-
-/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
- Core Function Interface containing:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Reset Functions
-*/
-/*@{*/
-
-/* ########################## NVIC functions #################################### */
-
-/**
- * @brief Set the Priority Grouping in NVIC Interrupt Controller
- *
- * @param PriorityGroup is priority grouping field
- *
- * Set the priority grouping field using the required unlock sequence.
- * The parameter priority_grouping is assigned to the field
- * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- */
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-/**
- * @brief Get the Priority Grouping from NVIC Interrupt Controller
- *
- * @return priority grouping field
- *
- * Get the priority grouping from NVIC Interrupt Controller.
- * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
- */
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
-}
-
-/**
- * @brief Enable Interrupt in NVIC Interrupt Controller
- *
- * @param IRQn The positive number of the external interrupt to enable
- *
- * Enable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-/**
- * @brief Disable the interrupt line for external interrupt specified
- *
- * @param IRQn The positive number of the external interrupt to disable
- *
- * Disable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-/**
- * @brief Read the interrupt pending bit for a device specific interrupt source
- *
- * @param IRQn The number of the device specifc interrupt
- * @return 1 = interrupt pending, 0 = interrupt not pending
- *
- * Read the pending register in NVIC and return 1 if its status is pending,
- * otherwise it returns 0
- */
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-/**
- * @brief Set the pending bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for set pending
- *
- * Set the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-/**
- * @brief Clear the pending bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for clear pending
- *
- * Clear the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-/**
- * @brief Read the active bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for read active bit
- * @return 1 = interrupt active, 0 = interrupt not active
- *
- * Read the active register in NVIC and returns 1 if its status is active,
- * otherwise it returns 0.
- */
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-/**
- * @brief Set the priority for an interrupt
- *
- * @param IRQn The number of the interrupt for set priority
- * @param priority The priority to set
- *
- * Set the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
- else {
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
-}
-
-/**
- * @brief Read the priority for an interrupt
- *
- * @param IRQn The number of the interrupt for get priority
- * @return The priority for the interrupt
- *
- * Read the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * The returned priority value is automatically aligned to the implemented
- * priority bits of the microcontroller.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
- else {
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-/**
- * @brief Encode the priority for an interrupt
- *
- * @param PriorityGroup The used priority group
- * @param PreemptPriority The preemptive priority value (starting from 0)
- * @param SubPriority The sub priority value (starting from 0)
- * @return The encoded priority for the interrupt
- *
- * Encode the priority for an interrupt with the given priority group,
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The returned priority value can be used for NVIC_SetPriority(...) function
- */
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- return (
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
- );
-}
-
-
-/**
- * @brief Decode the priority of an interrupt
- *
- * @param Priority The priority for the interrupt
- * @param PriorityGroup The used priority group
- * @param pPreemptPriority The preemptive priority value (starting from 0)
- * @param pSubPriority The sub priority value (starting from 0)
- *
- * Decode an interrupt priority value with the given priority group to
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The priority value can be retrieved with NVIC_GetPriority(...) function
- */
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
-}
-
-
-
-/* ################################## SysTick function ############################################ */
-
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
-
-/**
- * @brief Initialize and start the SysTick counter and its interrupt.
- *
- * @param ticks number of ticks between two interrupts
- * @return 1 = failed, 0 = successful
- *
- * Initialise the system tick timer and its interrupt and start the
- * system tick timer / counter in free running mode to generate
- * periodical interrupts.
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-
-
-
-/* ################################## Reset function ############################################ */
-
-/**
- * @brief Initiate a system reset request.
- *
- * Initiate a system reset request to reset the MCU
- */
-static __INLINE void NVIC_SystemReset(void)
-{
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-
-/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
- Core Debug Interface containing:
- - Core Debug Receive / Transmit Functions
- - Core Debug Defines
- - Core Debug Variables
-*/
-/*@{*/
-
-extern volatile int ITM_RxBuffer; /*!< variable to receive characters */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
-
-
-/**
- * @brief Outputs a character via the ITM channel 0
- *
- * @param ch character to output
- * @return character to output
- *
- * The function outputs a character via the ITM channel 0.
- * The function returns when no debugger is connected that has booked the output.
- * It is blocking when a debugger is connected, but the previous character send is not transmitted.
- */
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
- (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t) ch;
- }
- return (ch);
-}
-
-
-/**
- * @brief Inputs a character via variable ITM_RxBuffer
- *
- * @return received character, -1 = no character received
- *
- * The function inputs a character via variable ITM_RxBuffer.
- * The function returns when no debugger is connected that has booked the output.
- * It is blocking when a debugger is connected, but the previous character send is not transmitted.
- */
-static __INLINE int ITM_ReceiveChar (void) {
- int ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- * @brief Check if a character via variable ITM_RxBuffer is available
- *
- * @return 1 = character available, 0 = no character available
- *
- * The function checks variable ITM_RxBuffer whether a character is available or not.
- * The function returns '1' if a character is available and '0' if no character is available.
- */
-static __INLINE int ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}
-
-/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/ /* end of group CMSIS_CM3_core_definitions */
-
-#endif /* __CM3_CORE_H__ */
-
-/*lint -restore */
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- <h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
-Notes for STM32L1xx CMSIS</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
- <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
-2010 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
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- <ol style="margin-top: 0cm;" start="1" type="1">
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32L1xx
-CMSIS
-update History</a><o:p></o:p></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
- </ol>
- <span style="font-family: "Times New Roman";"></span>
- <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32L1xx
-CMSIS
-update History</span></h2>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">1.0.0RC1
-- 07/02/2010</span></h3><ol style="margin-top: 0in;" start="1" type="1">
- <li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
- </ol>
- <ul style="margin-top: 0in;" type="disc">
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">STM32L1xx CMSIS files
-updated to <span style="font-weight: bold;">CMSIS V1.30</span> release</span></li>
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Directory structure
-updated to be aligned with CMSIS V1.30<br>
- </span></li>
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
-for <b>STM32L Ultra Low-power
-Medium-density (STM32L15xx8/B) devices</b>. </span><span style="font-size: 10pt;"><o:p></o:p></span></li>
- </ul>
- <ol style="margin-top: 0in;" start="2" type="1">
- <li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">CMSIS Core Peripheral
-Access Layer</span></i></b></li>
- </ol>
- <ul>
- <li><b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i></b><span style="font-size: 10pt; font-family: Verdana;"> Refer to <a href="../../../CMSIS_changes.htm" target="_blank">CMSIS changes</a></span></li>
- </ul>
- <ol style="margin-top: 0in; list-style-type: decimal;" start="3">
- <li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32L1xx CMSIS Device
-Peripheral Access Layer </span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
- </ol>
- <ul style="margin-top: 0in;" type="disc">
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32L1xx CMSIS Cortex-M3 Device
-Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32l1xx.h</span></span><br>
- </li>
- <ul>
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">All library files renamed with stm32l15x to stm32l1xx.</span></li>
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">STM32L15X_LP product name renamed to STM32L1XX_MD.<br>
- </span></li>
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">HSE_VALUE value changed to 8MHz.</span></li>
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new register in SYSCFG: PMC register</span></li>
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RTC TCR register renamed to TAFCR</span></li>
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">GPIOF renamed to GPIOH</span></li>
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add and update of all peripherals bits definitions<br>
-</span></li>
-
- </ul>
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32L1xx CMSIS Cortex-M3 Device
-Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32l1xx.h and
-system_stm32l1xx.c</span></span><br>
- <span style="font-size: 10pt; font-family: Verdana;"></span></li>
- <ul>
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SystemFrequency
-variable name changed to SystemCoreClock</span><br>
- <span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"></span></span></li>
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Default </span></span><span style="font-size: 10pt; font-family: Verdana;">SystemCoreClock</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"> is changed to 32MHz (change the default frequency from SYSCLK_FREQ_HSE to SYSCLK_FREQ_32MHz).</span></span><span style="font-size: 10pt; font-family: Verdana;"><br>
- </span></li>
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">All while(1) loop were
-removed from all clock setting functions. User has to handle the HSE
-startup failure.<br>
- </span></li>
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Additional function <span style="font-weight: bold; font-style: italic;">void
-SystemCoreClockUpdate (void)</span> is provided.<br>
- </span></li>
- </ul>
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Startup files:</span>
- <span style="font-weight: bold; font-style: italic;">startup_stm32l1xx_md.s</span></span></li>
- <ul>
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Startup file name changed from <span style="font-weight: bold;">startup_stm32l15x_lp</span>.s to <span style="font-weight: bold;">startup_stm32l1xx_md.s</span><span style="font-weight: bold; font-style: italic;">.</span></span></li>
-
- <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SystemInit() function
-is called from startup file (startup_stm32l1xx_md.s) before to branch
-to application main.<br>
-To reconfigure the default setting of SystemInit() function, refer to
-system_stm32l1xx.c file <br>
- </span></li>
-
- </ul>
- </ul>
- <ul style="margin-top: 0in;" type="disc">
- </ul>
- <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
- <p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The
-enclosed firmware and all the related documentation are not covered by
-a License Agreement, if you need such License you can contact your
-local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>
- <p class="MsoNormal"><b style=""><span style="font-size: 10pt; font-family: Verdana; color: black;">THE
-PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO
-SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
-ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
-CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
-CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
-THEIR PRODUCTS. <o:p></o:p></span></b></p>
- <p class="MsoNormal"><span style="color: black;"><o:p> </o:p></span></p>
- <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
- <hr align="center" size="2" width="100%"></span></div>
- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
-complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32L (<span style="color: black;">CORTEX M3) 32-Bit Microcontrollers
-visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32l" target="_blank">www.st.com/STM32L</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
- </td>
- </tr>
- </tbody>
- </table>
- <p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
- </td>
- </tr>
- </tbody>
-</table>
-</div>
-<p class="MsoNormal"><o:p> </o:p></p>
-</div>
-
-</body></html>
\ No newline at end of file
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/startup/arm/startup_stm32l1xx_md.s b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/startup/arm/startup_stm32l1xx_md.s
deleted file mode 100644
index 3917b31..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/startup/arm/startup_stm32l1xx_md.s
+++ /dev/null
@@ -1,312 +0,0 @@
-;******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
-;* File Name : startup_stm32l15x_lp.s
-;* Author : MCD Application Team
-;* Version : V1.0.0RC1
-;* Date : 07/02/2010
-;* Description : STM32L15x Low Power Devices vector table for RVMDK
-;* toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM3 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_IRQHandler ; ADC1
- DCD USB_HP_IRQHandler ; USB High Priority
- DCD USB_LP_IRQHandler ; USB Low Priority
- DCD DAC_IRQHandler ; DAC
- DCD COMP_IRQHandler ; COMP through EXTI Line
- DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
- DCD LCD_IRQHandler ; LCD
- DCD TIM9_IRQHandler ; TIM9
- DCD TIM10_IRQHandler ; TIM10
- DCD TIM11_IRQHandler ; TIM11
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
- DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
- DCD TIM6_IRQHandler ; TIM6
- DCD TIM7_IRQHandler ; TIM7
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMPER_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_IRQHandler [WEAK]
- EXPORT DMA1_Channel3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_IRQHandler [WEAK]
- EXPORT DMA1_Channel5_IRQHandler [WEAK]
- EXPORT DMA1_Channel6_IRQHandler [WEAK]
- EXPORT DMA1_Channel7_IRQHandler [WEAK]
- EXPORT ADC1_IRQHandler [WEAK]
- EXPORT USB_HP_IRQHandler [WEAK]
- EXPORT USB_LP_IRQHandler [WEAK]
- EXPORT DAC_IRQHandler [WEAK]
- EXPORT COMP_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT LCD_IRQHandler [WEAK]
- EXPORT TIM9_IRQHandler [WEAK]
- EXPORT TIM10_IRQHandler [WEAK]
- EXPORT TIM11_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT USB_FS_WKUP_IRQHandler [WEAK]
- EXPORT TIM6_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
-;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE*****
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/startup/iar/startup_stm32l1xx_md.s b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/startup/iar/startup_stm32l1xx_md.s
deleted file mode 100644
index 43aa9a4..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/startup/iar/startup_stm32l1xx_md.s
+++ /dev/null
@@ -1,455 +0,0 @@
-;/******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
-;* File Name : startup_stm32l15x_lp.s
-;* Author : MCD Application Team
-;* Version : V1.0.0RC1
-;* Date : 07/02/2010
-;* Description : STM32L15x Low Power Devices vector table for EWARM5.x toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == __iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address.
-;* After Reset the Cortex-M3 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************/
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_IRQHandler ; ADC1
- DCD USB_HP_IRQHandler ; USB High Priority
- DCD USB_LP_IRQHandler ; USB Low Priority
- DCD DAC_IRQHandler ; DAC
- DCD COMP_IRQHandler ; COMP through EXTI Line
- DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
- DCD LCD_IRQHandler ; LCD
- DCD TIM9_IRQHandler ; TIM9
- DCD TIM10_IRQHandler ; TIM10
- DCD TIM11_IRQHandler ; TIM11
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
- DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
- DCD TIM6_IRQHandler ; TIM6
- DCD TIM7_IRQHandler ; TIM7
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER(1)
-NMI_Handler
- B NMI_Handler
-
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER(1)
-HardFault_Handler
- B HardFault_Handler
-
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER(1)
-MemManage_Handler
- B MemManage_Handler
-
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER(1)
-BusFault_Handler
- B BusFault_Handler
-
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER(1)
-UsageFault_Handler
- B UsageFault_Handler
-
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER(1)
-SVC_Handler
- B SVC_Handler
-
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER(1)
-DebugMon_Handler
- B DebugMon_Handler
-
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER(1)
-PendSV_Handler
- B PendSV_Handler
-
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER(1)
-SysTick_Handler
- B SysTick_Handler
-
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:REORDER(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:REORDER(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
-
- PUBWEAK TAMPER_STAMP_IRQHandler
- SECTION .text:CODE:REORDER(1)
-TAMPER_STAMP_IRQHandler
- B TAMPER_STAMP_IRQHandler
-
-
- PUBWEAK RTC_WKUP_IRQHandler
- SECTION .text:CODE:REORDER(1)
-RTC_WKUP_IRQHandler
- B RTC_WKUP_IRQHandler
-
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:REORDER(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:REORDER(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:REORDER(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:REORDER(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:REORDER(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:REORDER(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:REORDER(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
-
- PUBWEAK DMA1_Channel2_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMA1_Channel2_IRQHandler
- B DMA1_Channel2_IRQHandler
-
-
- PUBWEAK DMA1_Channel3_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMA1_Channel3_IRQHandler
- B DMA1_Channel3_IRQHandler
-
-
- PUBWEAK DMA1_Channel4_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMA1_Channel4_IRQHandler
- B DMA1_Channel4_IRQHandler
-
-
- PUBWEAK DMA1_Channel5_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMA1_Channel5_IRQHandler
- B DMA1_Channel5_IRQHandler
-
-
- PUBWEAK DMA1_Channel6_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMA1_Channel6_IRQHandler
- B DMA1_Channel6_IRQHandler
-
-
- PUBWEAK DMA1_Channel7_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMA1_Channel7_IRQHandler
- B DMA1_Channel7_IRQHandler
-
-
- PUBWEAK ADC1_IRQHandler
- SECTION .text:CODE:REORDER(1)
-ADC1_IRQHandler
- B ADC1_IRQHandler
-
-
- PUBWEAK USB_HP_IRQHandler
- SECTION .text:CODE:REORDER(1)
-USB_HP_IRQHandler
- B USB_HP_IRQHandler
-
-
- PUBWEAK USB_LP_IRQHandler
- SECTION .text:CODE:REORDER(1)
-USB_LP_IRQHandler
- B USB_LP_IRQHandler
-
-
- PUBWEAK DAC_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DAC_IRQHandler
- B DAC_IRQHandler
-
-
- PUBWEAK COMP_IRQHandler
- SECTION .text:CODE:REORDER(1)
-COMP_IRQHandler
- B COMP_IRQHandler
-
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:REORDER(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
-
- PUBWEAK LCD_IRQHandler
- SECTION .text:CODE:REORDER(1)
-LCD_IRQHandler
- B LCD_IRQHandler
-
-
- PUBWEAK TIM9_IRQHandler
- SECTION .text:CODE:REORDER(1)
-TIM9_IRQHandler
- B TIM9_IRQHandler
-
-
- PUBWEAK TIM10_IRQHandler
- SECTION .text:CODE:REORDER(1)
-TIM10_IRQHandler
- B TIM10_IRQHandler
-
-
- PUBWEAK TIM11_IRQHandler
- SECTION .text:CODE:REORDER(1)
-TIM11_IRQHandler
- B TIM11_IRQHandler
-
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:REORDER(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
-
- PUBWEAK TIM3_IRQHandler
- SECTION .text:CODE:REORDER(1)
-TIM3_IRQHandler
- B TIM3_IRQHandler
-
-
- PUBWEAK TIM4_IRQHandler
- SECTION .text:CODE:REORDER(1)
-TIM4_IRQHandler
- B TIM4_IRQHandler
-
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:REORDER(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:REORDER(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:REORDER(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:REORDER(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:REORDER(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
-
- PUBWEAK SPI2_IRQHandler
- SECTION .text:CODE:REORDER(1)
-SPI2_IRQHandler
- B SPI2_IRQHandler
-
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:REORDER(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:REORDER(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:REORDER(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:REORDER(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
-
- PUBWEAK RTC_Alarm_IRQHandler
- SECTION .text:CODE:REORDER(1)
-RTC_Alarm_IRQHandler
- B RTC_Alarm_IRQHandler
-
-
- PUBWEAK USB_FS_WKUP_IRQHandler
- SECTION .text:CODE:REORDER(1)
-USB_FS_WKUP_IRQHandler
- B USB_FS_WKUP_IRQHandler
-
-
- PUBWEAK TIM6_IRQHandler
- SECTION .text:CODE:REORDER(1)
-TIM6_IRQHandler
- B TIM6_IRQHandler
-
-
- PUBWEAK TIM7_IRQHandler
- SECTION .text:CODE:REORDER(1)
-TIM7_IRQHandler
- B TIM7_IRQHandler
-
- END
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/stm32l1xx.h b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/stm32l1xx.h
deleted file mode 100644
index 1fa0eda..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/stm32l1xx.h
+++ /dev/null
@@ -1,5043 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l1xx.h
- * @author STMicroelectronics - MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
- * This file contains all the peripheral register's definitions, bits
- * definitions and memory mapping for STM32L1xx devices.
- ******************************************************************************
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32l1xx
- * @{
- */
-
-#ifndef __STM32L1XX_H
-#define __STM32L1XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup Library_configuration_section
- * @{
- */
-
-/* Uncomment the line below according to the target STM32L device used in your
- application
- */
-
-#if !defined (STM32L1XX_MD)
- #define STM32L1XX_MD /*!< STM32L1XX_MD: STM32L Ultra Low Power Medium-density devices */
-#endif
-/* Tip: To avoid modifying this file each time you need to switch between these
- devices, you can define the device in your toolchain compiler preprocessor.
-
- - Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx
- microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
-
- */
-
-#if !defined USE_STDPERIPH_DRIVER
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
- In this case, these drivers will not be included and the application code will
- be based on direct access to peripherals registers
- */
- /*#define USE_STDPERIPH_DRIVER*/
-#endif
-
-/**
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)
- used in your application
-
- Tip: To avoid modifying this file each time you need to use different HSE, you
- can define the HSE value in your toolchain compiler preprocessor.
- */
-#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
-
-/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
- Timeout value
- */
-#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
-
-#define MSI_VALUE ((uint32_t)2000000) /*!< Default value of the Internal Multi Speed oscillator in Hz */
-#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz */
-#define LSI_VALUE ((uint32_t)37000) /*!< Value of the Internal Low Speed oscillator in Hz */
-#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
-
-/**
- * @brief STM32L1xx Standard Peripheral Library version number
- */
-#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:16] STM32L1xx Standard Peripheral Library main version */
-#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [15:8] STM32L1xx Standard Peripheral Library sub1 version */
-#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32L1xx Standard Peripheral Library sub2 version */
-#define __STM32L1XX_STDPERIPH_VERSION ((__STM32L1XX_STDPERIPH_VERSION_MAIN << 16)\
- | (__STM32L1XX_STDPERIPH_VERSION_SUB1 << 8)\
- | __STM32L1XX_STDPERIPH_VERSION_SUB2)
-
-/**
- * @}
- */
-
-/** @addtogroup Configuration_section_for_CMSIS
- * @{
- */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device
- * in @ref Library_configuration_section
- */
-#define __MPU_PRESENT 1 /*!< STM32L provide a MPU present */
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-
-/*!< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
-
-/****** STM32L specific Interrupt Numbers ********************************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
- TAMPER_STAMP_IRQn = 2, /*!< Tamper and Time Stamp through EXTI Line Interrupts */
- RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */
- RCC_IRQn = 5, /*!< RCC global Interrupt */
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
- EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
- EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
- DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
- DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
- DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
- DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
- DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
- DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
- DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
- ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
- USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */
- USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */
- DAC_IRQn = 21, /*!< DAC Interrupt */
- COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- LCD_IRQn = 24, /*!< LCD Interrupt */
- TIM9_IRQn = 25, /*!< TIM9 global Interrupt */
- TIM10_IRQn = 26, /*!< TIM10 global Interrupt */
- TIM11_IRQn = 27, /*!< TIM11 global Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
- USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */
- TIM6_IRQn = 43, /*!< TIM6 global Interrupt */
- TIM7_IRQn = 44 /*!< TIM7 global Interrupt */
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Exported_types
- * @{
- */
-
-typedef enum {FALSE = 0, TRUE = !FALSE} bool;
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog to Digital Converter
- */
-
-typedef struct
-{
- __IO uint32_t SR;
- __IO uint32_t CR1;
- __IO uint32_t CR2;
- __IO uint32_t SMPR1;
- __IO uint32_t SMPR2;
- __IO uint32_t SMPR3;
- __IO uint32_t JOFR1;
- __IO uint32_t JOFR2;
- __IO uint32_t JOFR3;
- __IO uint32_t JOFR4;
- __IO uint32_t HTR;
- __IO uint32_t LTR;
- __IO uint32_t SQR1;
- __IO uint32_t SQR2;
- __IO uint32_t SQR3;
- __IO uint32_t SQR4;
- __IO uint32_t SQR5;
- __IO uint32_t JSQR;
- __IO uint32_t JDR1;
- __IO uint32_t JDR2;
- __IO uint32_t JDR3;
- __IO uint32_t JDR4;
- __IO uint32_t DR;
-} ADC_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CSR;
- __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-
-/**
- * @brief Comparator
- */
-
-typedef struct
-{
- __IO uint32_t CSR;
-} COMP_TypeDef;
-
-/**
- * @brief CRC calculation unit
- */
-
-typedef struct
-{
- __IO uint32_t DR;
- __IO uint8_t IDR;
- uint8_t RESERVED0;
- uint16_t RESERVED1;
- __IO uint32_t CR;
-} CRC_TypeDef;
-
-/**
- * @brief Digital to Analog Converter
- */
-
-typedef struct
-{
- __IO uint32_t CR;
- __IO uint32_t SWTRIGR;
- __IO uint32_t DHR12R1;
- __IO uint32_t DHR12L1;
- __IO uint32_t DHR8R1;
- __IO uint32_t DHR12R2;
- __IO uint32_t DHR12L2;
- __IO uint32_t DHR8R2;
- __IO uint32_t DHR12RD;
- __IO uint32_t DHR12LD;
- __IO uint32_t DHR8RD;
- __IO uint32_t DOR1;
- __IO uint32_t DOR2;
- __IO uint32_t SR;
-} DAC_TypeDef;
-
-/**
- * @brief Debug MCU
- */
-
-typedef struct
-{
- __IO uint32_t IDCODE;
- __IO uint32_t CR;
- __IO uint32_t APB1FZ;
- __IO uint32_t APB2FZ;
-}DBGMCU_TypeDef;
-
-/**
- * @brief DMA Controller
- */
-
-typedef struct
-{
- __IO uint32_t CCR;
- __IO uint32_t CNDTR;
- __IO uint32_t CPAR;
- __IO uint32_t CMAR;
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
- __IO uint32_t ISR;
- __IO uint32_t IFCR;
-} DMA_TypeDef;
-
-/**
- * @brief External Interrupt/Event Controller
- */
-
-typedef struct
-{
- __IO uint32_t IMR;
- __IO uint32_t EMR;
- __IO uint32_t RTSR;
- __IO uint32_t FTSR;
- __IO uint32_t SWIER;
- __IO uint32_t PR;
-} EXTI_TypeDef;
-
-/**
- * @brief FLASH Registers
- */
-
-typedef struct
-{
- __IO uint32_t ACR;
- __IO uint32_t PECR;
- __IO uint32_t PDKEYR;
- __IO uint32_t PEKEYR;
- __IO uint32_t PRGKEYR;
- __IO uint32_t OPTKEYR;
- __IO uint32_t SR;
- __IO uint32_t OBR;
- __IO uint32_t WRPR;
-} FLASH_TypeDef;
-
-/**
- * @brief Option Bytes Registers
- */
-
-typedef struct
-{
- __IO uint32_t RDP;
- __IO uint32_t USER;
- __IO uint32_t WRP01;
- __IO uint32_t WRP23;
-} OB_TypeDef;
-
-/**
- * @brief General Purpose IO
- */
-
-typedef struct
-{
- __IO uint32_t MODER;
- __IO uint16_t OTYPER;
- uint16_t RESERVED0;
- __IO uint32_t OSPEEDR;
- __IO uint32_t PUPDR;
- __IO uint16_t IDR;
- uint16_t RESERVED1;
- __IO uint16_t ODR;
- uint16_t RESERVED2;
- __IO uint16_t BSRRL; /* BSRR register is split to 2 * 16-bit fields BSRRL */
- __IO uint16_t BSRRH; /* BSRR register is split to 2 * 16-bit fields BSRRH */
- __IO uint32_t LCKR;
- __IO uint32_t AFR[2];
-} GPIO_TypeDef;
-
-/**
- * @brief SysTem Configuration
- */
-
-typedef struct
-{
- __IO uint32_t MEMRMP;
- __IO uint32_t PMC;
- __IO uint32_t EXTICR[4];
-} SYSCFG_TypeDef;
-
-/**
- * @brief Inter-integrated Circuit Interface
- */
-
-typedef struct
-{
- __IO uint16_t CR1;
- uint16_t RESERVED0;
- __IO uint16_t CR2;
- uint16_t RESERVED1;
- __IO uint16_t OAR1;
- uint16_t RESERVED2;
- __IO uint16_t OAR2;
- uint16_t RESERVED3;
- __IO uint16_t DR;
- uint16_t RESERVED4;
- __IO uint16_t SR1;
- uint16_t RESERVED5;
- __IO uint16_t SR2;
- uint16_t RESERVED6;
- __IO uint16_t CCR;
- uint16_t RESERVED7;
- __IO uint16_t TRISE;
- uint16_t RESERVED8;
-} I2C_TypeDef;
-
-/**
- * @brief Independent WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t KR;
- __IO uint32_t PR;
- __IO uint32_t RLR;
- __IO uint32_t SR;
-} IWDG_TypeDef;
-
-
-/**
- * @brief LCD
- */
-
-typedef struct
-{
- __IO uint32_t CR;
- __IO uint32_t FCR;
- __IO uint32_t SR;
- __IO uint32_t CLR;
- uint32_t RESERVED;
- __IO uint32_t RAM[16];
-} LCD_TypeDef;
-
-/**
- * @brief Power Control
- */
-
-typedef struct
-{
- __IO uint32_t CR;
- __IO uint32_t CSR;
-} PWR_TypeDef;
-
-/**
- * @brief Reset and Clock Control
- */
-
-typedef struct
-{
- __IO uint32_t CR;
- __IO uint32_t ICSCR;
- __IO uint32_t CFGR;
- __IO uint32_t CIR;
- __IO uint32_t AHBRSTR;
- __IO uint32_t APB2RSTR;
- __IO uint32_t APB1RSTR;
- __IO uint32_t AHBENR;
- __IO uint32_t APB2ENR;
- __IO uint32_t APB1ENR;
- __IO uint32_t AHBLPENR;
- __IO uint32_t APB2LPENR;
- __IO uint32_t APB1LPENR;
- __IO uint32_t CSR;
-} RCC_TypeDef;
-
-/**
- * @brief Routing Interface
- */
-
-typedef struct
-{
- __IO uint32_t ICR;
- __IO uint32_t ASCR1;
- __IO uint32_t ASCR2;
- __IO uint32_t HYSCR1;
- __IO uint32_t HYSCR2;
- __IO uint32_t HYSCR3;
-} RI_TypeDef;
-
-/**
- * @brief Real-Time Clock
- */
-
-typedef struct
-{
- __IO uint32_t TR;
- __IO uint32_t DR;
- __IO uint32_t CR;
- __IO uint32_t ISR;
- __IO uint32_t PRER;
- __IO uint32_t WUTR;
- __IO uint32_t CALIBR;
- __IO uint32_t ALRMAR;
- __IO uint32_t ALRMBR;
- __IO uint32_t WRP;
- uint32_t RESERVED1;
- uint32_t RESERVED2;
- __IO uint32_t TSTR;
- __IO uint32_t TSDR;
- uint32_t RESERVED3;
- uint32_t RESERVED4;
- __IO uint32_t TAFCR;
- uint32_t RESERVED5;
- uint32_t RESERVED6;
- uint32_t RESERVED7;
- __IO uint32_t BK0R;
- __IO uint32_t BK1R;
- __IO uint32_t BK2R;
- __IO uint32_t BK3R;
- __IO uint32_t BK4R;
- __IO uint32_t BK5R;
- __IO uint32_t BK6R;
- __IO uint32_t BK7R;
- __IO uint32_t BK8R;
- __IO uint32_t BK9R;
- __IO uint32_t BK10R;
- __IO uint32_t BK11R;
- __IO uint32_t BK12R;
- __IO uint32_t BK13R;
- __IO uint32_t BK14R;
- __IO uint32_t BK15R;
- __IO uint32_t BK16R;
- __IO uint32_t BK17R;
- __IO uint32_t BK18R;
- __IO uint32_t BK19R;
-} RTC_TypeDef;
-
-/**
- * @brief Serial Peripheral Interface
- */
-
-typedef struct
-{
- __IO uint16_t CR1;
- uint16_t RESERVED0;
- __IO uint16_t CR2;
- uint16_t RESERVED1;
- __IO uint16_t SR;
- uint16_t RESERVED2;
- __IO uint16_t DR;
- uint16_t RESERVED3;
- __IO uint16_t CRCPR;
- uint16_t RESERVED4;
- __IO uint16_t RXCRCR;
- uint16_t RESERVED5;
- __IO uint16_t TXCRCR;
- uint16_t RESERVED6;
-} SPI_TypeDef;
-
-/**
- * @brief TIM
- */
-
-typedef struct
-{
- __IO uint16_t CR1;
- uint16_t RESERVED0;
- __IO uint16_t CR2;
- uint16_t RESERVED1;
- __IO uint16_t SMCR;
- uint16_t RESERVED2;
- __IO uint16_t DIER;
- uint16_t RESERVED3;
- __IO uint16_t SR;
- uint16_t RESERVED4;
- __IO uint16_t EGR;
- uint16_t RESERVED5;
- __IO uint16_t CCMR1;
- uint16_t RESERVED6;
- __IO uint16_t CCMR2;
- uint16_t RESERVED7;
- __IO uint16_t CCER;
- uint16_t RESERVED8;
- __IO uint16_t CNT;
- uint16_t RESERVED9;
- __IO uint16_t PSC;
- uint16_t RESERVED10;
- __IO uint16_t ARR;
- uint16_t RESERVED11;
- uint32_t RESERVED12;
- __IO uint16_t CCR1;
- uint16_t RESERVED13;
- __IO uint16_t CCR2;
- uint16_t RESERVED14;
- __IO uint16_t CCR3;
- uint16_t RESERVED15;
- __IO uint16_t CCR4;
- uint16_t RESERVED16;
- uint32_t RESERVED17;
- __IO uint16_t DCR;
- uint16_t RESERVED18;
- __IO uint16_t DMAR;
- uint16_t RESERVED19;
- __IO uint16_t OR;
- uint16_t RESERVED20;
-} TIM_TypeDef;
-
-/**
- * @brief Universal Synchronous Asynchronous Receiver Transmitter
- */
-
-typedef struct
-{
- __IO uint16_t SR;
- uint16_t RESERVED0;
- __IO uint16_t DR;
- uint16_t RESERVED1;
- __IO uint16_t BRR;
- uint16_t RESERVED2;
- __IO uint16_t CR1;
- uint16_t RESERVED3;
- __IO uint16_t CR2;
- uint16_t RESERVED4;
- __IO uint16_t CR3;
- uint16_t RESERVED5;
- __IO uint16_t GTPR;
- uint16_t RESERVED6;
-} USART_TypeDef;
-
-/**
- * @brief Window WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t CR;
- __IO uint32_t CFR;
- __IO uint32_t SR;
-} WWDG_TypeDef;
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_memory_map
- * @{
- */
-
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */
-
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the bit-band region */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
-
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
-#define LCD_BASE (APB1PERIPH_BASE + 0x2400)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
-#define COMP_BASE (APB1PERIPH_BASE + 0x7C00)
-#define RI_BASE (APB1PERIPH_BASE + 0x7C04)
-
-#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
-#define TIM9_BASE (APB2PERIPH_BASE + 0x0800)
-#define TIM10_BASE (APB2PERIPH_BASE + 0x0C00)
-#define TIM11_BASE (APB2PERIPH_BASE + 0x1000)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
-#define ADC_BASE (APB2PERIPH_BASE + 0x2700)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
-
-#define GPIOA_BASE (AHBPERIPH_BASE + 0x0000)
-#define GPIOB_BASE (AHBPERIPH_BASE + 0x0400)
-#define GPIOC_BASE (AHBPERIPH_BASE + 0x0800)
-#define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00)
-#define GPIOE_BASE (AHBPERIPH_BASE + 0x1000)
-#define GPIOH_BASE (AHBPERIPH_BASE + 0x1400)
-#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
-#define RCC_BASE (AHBPERIPH_BASE + 0x3800)
-
-
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */
-#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */
-
-#define DMA1_BASE (AHBPERIPH_BASE + 0x6000)
-#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008)
-#define DMA1_Channel2_BASE (DMA1_BASE + 0x001C)
-#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030)
-#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044)
-#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058)
-#define DMA1_Channel6_BASE (DMA1_BASE + 0x006C)
-#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080)
-
-
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_declaration
- * @{
- */
-
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#define LCD ((LCD_TypeDef *) LCD_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define COMP ((COMP_TypeDef *) COMP_BASE)
-#define RI ((RI_TypeDef *) RI_BASE)
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
-#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
-
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB ((OB_TypeDef *) OB_BASE)
-
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_constants
- * @{
- */
-
- /** @addtogroup Peripheral_Registers_Bits_Definition
- * @{
- */
-
-/******************************************************************************/
-/* Peripheral Registers_Bits_Definition */
-/******************************************************************************/
-/******************************************************************************/
-/* */
-/* Analog to Digital Converter */
-/* */
-/******************************************************************************/
-
-/******************** Bit definition for ADC_SR register ********************/
-#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */
-#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */
-#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */
-#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */
-#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */
-#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */
-#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */
-#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */
-#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */
-
-/******************* Bit definition for ADC_CR1 register ********************/
-#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-
-#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
-#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
-#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
-#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
-#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
-#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
-#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
-#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
-
-#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */
-#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */
-#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */
-
-#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */
-#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */
-
-#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
-#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
-
-#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */
-#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-
-#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */
-
-/******************* Bit definition for ADC_CR2 register ********************/
-#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
-#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
-
-#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */
-#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-
-#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
-#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */
-#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */
-#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */
-
-#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */
-#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-
-#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */
-#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-
-#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */
-
-#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */
-#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-
-#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */
-#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */
-
-#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */
-
-/****************** Bit definition for ADC_SMPR1 register *******************/
-#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */
-#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-
-#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */
-#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */
-
-#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */
-#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */
-
-#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */
-#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */
-#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */
-#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */
-
-#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */
-#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */
-#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */
-
-#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */
-#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */
-#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */
-#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */
-
-/****************** Bit definition for ADC_SMPR2 register *******************/
-#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-
-#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
-
-#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
-
-#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
-#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
-#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
-
-#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
-#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
-
-#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */
-#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
-#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
-#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
-
-#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
-#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
-
-#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
-#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
-#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
-
-#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-
-#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */
-#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */
-#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */
-#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */
-
-/****************** Bit definition for ADC_SMPR3 register *******************/
-#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-
-#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
-
-#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
-
-#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
-#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
-#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
-
-#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
-#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
-
-#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
-#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
-#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
-
-#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
-#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
-
-#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
-#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
-#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
-
-#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-
-#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
-#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
-#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
-
-
-/****************** Bit definition for ADC_JOFR1 register *******************/
-#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */
-
-/****************** Bit definition for ADC_JOFR2 register *******************/
-#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */
-
-/****************** Bit definition for ADC_JOFR3 register *******************/
-#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */
-
-/****************** Bit definition for ADC_JOFR4 register *******************/
-#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */
-
-/******************* Bit definition for ADC_HTR register ********************/
-#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */
-
-/******************* Bit definition for ADC_LTR register ********************/
-#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
-
-/******************* Bit definition for ADC_SQR1 register *******************/
-#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */
-#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-
-#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */
-#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */
-#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */
-#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */
-#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */
-#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */
-
-#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */
-#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */
-#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */
-#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-
-/******************* Bit definition for ADC_SQR2 register *******************/
-#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */
-#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-
-#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */
-#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */
-#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */
-#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */
-#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */
-#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */
-
-#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */
-#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */
-#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */
-#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */
-#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */
-#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */
-#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */
-
-#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */
-#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */
-#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */
-
-#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */
-#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */
-#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */
-#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */
-#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */
-#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */
-
-/******************* Bit definition for ADC_SQR3 register *******************/
-#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
-#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-
-#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
-#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
-#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
-#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
-#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
-#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
-
-#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
-#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
-#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
-#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
-#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
-#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
-#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
-
-#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */
-#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */
-#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */
-
-#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */
-#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */
-#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */
-#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */
-#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */
-#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */
-
-/******************* Bit definition for ADC_SQR4 register *******************/
-#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
-#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-
-#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
-#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
-#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
-#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
-#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
-#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
-
-#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
-#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
-#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
-#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
-#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
-#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
-#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
-
-#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
-#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
-#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
-
-#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
-#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
-#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
-#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
-#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
-#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
-
-/******************* Bit definition for ADC_SQR5 register *******************/
-#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
-#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-
-#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
-#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
-#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
-#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
-#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
-
-#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
-#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
-#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
-#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
-#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
-#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
-
-#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
-#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
-#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
-
-#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
-#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
-#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
-#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
-#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
-#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
-
-
-/******************* Bit definition for ADC_JSQR register *******************/
-#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
-#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-
-#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
-#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
-#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
-#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
-#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
-
-#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
-#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
-#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
-#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
-#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
-
-#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */
-#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-
-/******************* Bit definition for ADC_JDR1 register *******************/
-#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
-
-/******************* Bit definition for ADC_JDR2 register *******************/
-#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
-
-/******************* Bit definition for ADC_JDR3 register *******************/
-#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
-
-/******************* Bit definition for ADC_JDR4 register *******************/
-#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
-
-/******************** Bit definition for ADC_DR register ********************/
-#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
-
-
-/******************* Bit definition for ADC_CSR register ********************/
-#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */
-#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */
-#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */
-#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */
-#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */
-#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */
-#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */
-
-/******************* Bit definition for ADC_CCR register ********************/
-#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/
-#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
-
-/******************************************************************************/
-/* */
-/* Comparator */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for COMP_CSR register ********************/
-#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */
-#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */
-#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */
-#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */
-
-#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */
-
-#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */
-#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */
-
-#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */
-#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */
-
-#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */
-#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
-#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
-
-#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */
-#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */
-#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */
-
-/******************************************************************************/
-/* */
-/* CRC calculation unit */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for CRC_DR register *********************/
-#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
-
-/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
-
-/******************** Bit definition for CRC_CR register ********************/
-#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */
-
-/******************************************************************************/
-/* */
-/* Digital to Analog Converter */
-/* */
-/******************************************************************************/
-
-/******************** Bit definition for DAC_CR register ********************/
-#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
-#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
-#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
-
-#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
-#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
-
-#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-
-#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
-#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
-#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
-#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
-
-#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
-#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
-
-#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-
-#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
-
-/***************** Bit definition for DAC_SWTRIGR register ******************/
-#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
-
-/***************** Bit definition for DAC_DHR12R1 register ******************/
-#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
-
-/***************** Bit definition for DAC_DHR12L1 register ******************/
-#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
-
-/****************** Bit definition for DAC_DHR8R1 register ******************/
-#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
-
-/***************** Bit definition for DAC_DHR12R2 register ******************/
-#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
-
-/***************** Bit definition for DAC_DHR12L2 register ******************/
-#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
-
-/****************** Bit definition for DAC_DHR8R2 register ******************/
-#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
-
-/***************** Bit definition for DAC_DHR12RD register ******************/
-#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
-
-/***************** Bit definition for DAC_DHR12LD register ******************/
-#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
-
-/****************** Bit definition for DAC_DHR8RD register ******************/
-#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
-
-/******************* Bit definition for DAC_DOR1 register *******************/
-#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
-
-/******************* Bit definition for DAC_DOR2 register *******************/
-#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
-
-/******************** Bit definition for DAC_SR register ********************/
-#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/* */
-/* Debug MCU */
-/* */
-/******************************************************************************/
-
-/**************** Bit definition for DBGMCU_IDCODE register *****************/
-#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
-#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
-#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
-#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
-#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
-#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
-#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
-#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
-
-/****************** Bit definition for DBGMCU_CR register *******************/
-#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-
-/****************** Bit definition for DBGMCU_APB1_FZ register **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) /*!< SMBUS timeout mode stopped when Core is halted */
-
-/****************** Bit definition for DBGMCU_APB2_FZ register **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004) /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008) /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010) /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/* */
-/* DMA Controller */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for DMA_ISR register ********************/
-#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
-
-/******************* Bit definition for DMA_IFCR register *******************/
-#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */
-#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
-
-/******************* Bit definition for DMA_CCR1 register *******************/
-#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/
-#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
-#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
-#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
-#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
-#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */
-#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
-#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
-
-#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
-
-#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
-
-#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
-
-/******************* Bit definition for DMA_CCR2 register *******************/
-#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */
-#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */
-#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
-#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
-#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
-#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */
-#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
-#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
-
-#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
-
-#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
-
-#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
-
-/******************* Bit definition for DMA_CCR3 register *******************/
-#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */
-#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
-#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
-#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
-#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
-#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */
-#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
-#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
-
-#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
-
-#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
-
-#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
-
-/*!<****************** Bit definition for DMA_CCR4 register *******************/
-#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */
-#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
-#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
-#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
-#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
-#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */
-#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
-#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
-
-#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
-
-#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
-
-#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
-
-/****************** Bit definition for DMA_CCR5 register *******************/
-#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */
-#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
-#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
-#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
-#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
-#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */
-#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
-#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
-
-#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
-
-#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
-
-#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
-
-/******************* Bit definition for DMA_CCR6 register *******************/
-#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */
-#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
-#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
-#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
-#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
-#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */
-#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
-#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
-
-#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
-
-#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
-
-#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
-
-/******************* Bit definition for DMA_CCR7 register *******************/
-#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */
-#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
-#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
-#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
-#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
-#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */
-#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
-#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
-
-#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
-
-#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
-
-#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
-
-/****************** Bit definition for DMA_CNDTR1 register ******************/
-#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
-
-/****************** Bit definition for DMA_CNDTR2 register ******************/
-#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
-
-/****************** Bit definition for DMA_CNDTR3 register ******************/
-#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
-
-/****************** Bit definition for DMA_CNDTR4 register ******************/
-#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
-
-/****************** Bit definition for DMA_CNDTR5 register ******************/
-#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
-
-/****************** Bit definition for DMA_CNDTR6 register ******************/
-#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
-
-/****************** Bit definition for DMA_CNDTR7 register ******************/
-#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
-
-/****************** Bit definition for DMA_CPAR1 register *******************/
-#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
-
-/****************** Bit definition for DMA_CPAR2 register *******************/
-#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
-
-/****************** Bit definition for DMA_CPAR3 register *******************/
-#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
-
-
-/****************** Bit definition for DMA_CPAR4 register *******************/
-#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
-
-/****************** Bit definition for DMA_CPAR5 register *******************/
-#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
-
-/****************** Bit definition for DMA_CPAR6 register *******************/
-#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
-
-
-/****************** Bit definition for DMA_CPAR7 register *******************/
-#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
-
-/****************** Bit definition for DMA_CMAR1 register *******************/
-#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
-
-/****************** Bit definition for DMA_CMAR2 register *******************/
-#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
-
-/****************** Bit definition for DMA_CMAR3 register *******************/
-#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
-
-
-/****************** Bit definition for DMA_CMAR4 register *******************/
-#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
-
-/****************** Bit definition for DMA_CMAR5 register *******************/
-#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
-
-/****************** Bit definition for DMA_CMAR6 register *******************/
-#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
-
-/****************** Bit definition for DMA_CMAR7 register *******************/
-#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
-
-/******************************************************************************/
-/* */
-/* External Interrupt/Event Controller */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for EXTI_IMR register *******************/
-#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
-
-/******************* Bit definition for EXTI_EMR register *******************/
-#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
-
-/****************** Bit definition for EXTI_RTSR register *******************/
-#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
-
-/****************** Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
-
-/****************** Bit definition for EXTI_SWIER register ******************/
-#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
-
-/******************* Bit definition for EXTI_PR register ********************/
-#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
-#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
-#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
-#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
-#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
-#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
-#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
-#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
-#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
-#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
-#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
-#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
-#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
-#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
-#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
-#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
-#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
-#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
-#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit 18 */
-#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
-#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
-#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
-#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
-
-/******************************************************************************/
-/* */
-/* FLASH and Option Bytes Registers */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for FLASH_ACR register ******************/
-#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< Latency */
-#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64 ((uint32_t)0x00000004) /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /*!< Flash mode during RUN mode */
-
-/******************* Bit definition for FLASH_PECR register ******************/
-#define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */
-#define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */
-#define FLASH_PECR_FTDW ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */
-#define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */
-#define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */
-#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */
-
-/****************** Bit definition for FLASH_PDKEYR register ******************/
-#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
-
-/****************** Bit definition for FLASH_PEKEYR register ******************/
-#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
-
-/****************** Bit definition for FLASH_PRGKEYR register ******************/
-#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /*!< Program matrix Key */
-
-/****************** Bit definition for FLASH_OPTKEYR register ******************/
-#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option bytes matrix Key */
-
-/****************** Bit definition for FLASH_SR register *******************/
-#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
-#define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/
-#define FLASH_SR_ENHV ((uint32_t)0x00000004) /*!< End of high voltage */
-#define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protected error */
-#define FLASH_SR_PGAERR ((uint32_t)0x00000200) /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR ((uint32_t)0x00000400) /*!< Size error */
-#define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /*!< Option validity error */
-
-/****************** Bit definition for FLASH_OBR register *******************/
-#define FLASH_OBR_RDPRT ((uint16_t)0x000000AA) /*!< Read Protection */
-#define FLASH_OBR_BOR_LEV ((uint16_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER ((uint32_t)0x00700000) /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW ((uint32_t)0x00100000) /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP ((uint32_t)0x00200000) /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000) /*!< nRST_STDBY */
-
-/****************** Bit definition for FLASH_WRPR register ******************/
-#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
-
-/******************************************************************************/
-/* */
-/* General Purpose IOs */
-/* */
-/******************************************************************************/
-/******************* Bit definition for GPIO_MODER register *****************/
-#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
-#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
-#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
-#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
-#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
-#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
-#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
-#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
-#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
-#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
-#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
-#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
-#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
-#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
-#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
-#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
-#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
-#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
-#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
-#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
-#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
-#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
-#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
-#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
-#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
-#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
-#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
-#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
-#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
-#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
-#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
-#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
-#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
-#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
-#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
-#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
-#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
-#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
-#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
-#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
-
-/******************* Bit definition for GPIO_OTYPER register ****************/
-#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
-
-/******************* Bit definition for GPIO_OSPEEDR register ***************/
-#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
-#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
-#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
-#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
-#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
-#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
-#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
-#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
-#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
-#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
-#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
-#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
-#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
-#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
-#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
-#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
-
-/******************* Bit definition for GPIO_PUPDR register *****************/
-#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
-#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
-#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
-#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
-#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
-#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
-#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
-#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
-#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
-#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
-#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
-#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
-#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
-#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
-#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
-#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
-
-/******************* Bit definition for GPIO_IDR register *******************/
-#define GPIO_OTYPER_IDR_0 ((uint32_t)0x00000001)
-#define GPIO_OTYPER_IDR_1 ((uint32_t)0x00000002)
-#define GPIO_OTYPER_IDR_2 ((uint32_t)0x00000004)
-#define GPIO_OTYPER_IDR_3 ((uint32_t)0x00000008)
-#define GPIO_OTYPER_IDR_4 ((uint32_t)0x00000010)
-#define GPIO_OTYPER_IDR_5 ((uint32_t)0x00000020)
-#define GPIO_OTYPER_IDR_6 ((uint32_t)0x00000040)
-#define GPIO_OTYPER_IDR_7 ((uint32_t)0x00000080)
-#define GPIO_OTYPER_IDR_8 ((uint32_t)0x00000100)
-#define GPIO_OTYPER_IDR_9 ((uint32_t)0x00000200)
-#define GPIO_OTYPER_IDR_10 ((uint32_t)0x00000400)
-#define GPIO_OTYPER_IDR_11 ((uint32_t)0x00000800)
-#define GPIO_OTYPER_IDR_12 ((uint32_t)0x00001000)
-#define GPIO_OTYPER_IDR_13 ((uint32_t)0x00002000)
-#define GPIO_OTYPER_IDR_14 ((uint32_t)0x00004000)
-#define GPIO_OTYPER_IDR_15 ((uint32_t)0x00008000)
-
-/******************* Bit definition for GPIO_ODR register *******************/
-#define GPIO_OTYPER_ODR_0 ((uint32_t)0x00000001)
-#define GPIO_OTYPER_ODR_1 ((uint32_t)0x00000002)
-#define GPIO_OTYPER_ODR_2 ((uint32_t)0x00000004)
-#define GPIO_OTYPER_ODR_3 ((uint32_t)0x00000008)
-#define GPIO_OTYPER_ODR_4 ((uint32_t)0x00000010)
-#define GPIO_OTYPER_ODR_5 ((uint32_t)0x00000020)
-#define GPIO_OTYPER_ODR_6 ((uint32_t)0x00000040)
-#define GPIO_OTYPER_ODR_7 ((uint32_t)0x00000080)
-#define GPIO_OTYPER_ODR_8 ((uint32_t)0x00000100)
-#define GPIO_OTYPER_ODR_9 ((uint32_t)0x00000200)
-#define GPIO_OTYPER_ODR_10 ((uint32_t)0x00000400)
-#define GPIO_OTYPER_ODR_11 ((uint32_t)0x00000800)
-#define GPIO_OTYPER_ODR_12 ((uint32_t)0x00001000)
-#define GPIO_OTYPER_ODR_13 ((uint32_t)0x00002000)
-#define GPIO_OTYPER_ODR_14 ((uint32_t)0x00004000)
-#define GPIO_OTYPER_ODR_15 ((uint32_t)0x00008000)
-
-/******************* Bit definition for GPIO_BSRR register ******************/
-#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
-
-/******************************************************************************/
-/* */
-/* Inter-integrated Circuit Interface */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for I2C_CR1 register ********************/
-#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */
-#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */
-#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */
-#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */
-#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */
-#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */
-#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */
-#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */
-#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */
-
-/******************* Bit definition for I2C_CR2 register ********************/
-#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */
-#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */
-#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */
-#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */
-#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */
-#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */
-
-#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */
-#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */
-
-/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */
-#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */
-
-#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */
-#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */
-#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */
-#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */
-#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */
-#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */
-#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */
-#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */
-#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */
-#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */
-
-/******************* Bit definition for I2C_OAR2 register *******************/
-#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */
-
-/******************** Bit definition for I2C_DR register ********************/
-#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */
-
-/******************* Bit definition for I2C_SR1 register ********************/
-#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */
-#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */
-#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */
-
-/******************* Bit definition for I2C_SR2 register ********************/
-#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */
-#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */
-#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */
-
-/******************* Bit definition for I2C_CCR register ********************/
-#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */
-
-/****************** Bit definition for I2C_TRISE register *******************/
-#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/* */
-/* Independent WATCHDOG */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for IWDG_KR register ********************/
-#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */
-
-/******************* Bit definition for IWDG_PR register ********************/
-#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */
-#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */
-#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */
-
-/******************* Bit definition for IWDG_RLR register *******************/
-#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */
-
-/******************* Bit definition for IWDG_SR register ********************/
-#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/* */
-/* LCD */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for LCD_CR register *********************/
-#define LCD_CR_LCDEN ((uint32_t)0x00000001) /*!< LCD Enable Bit */
-#define LCD_CR_VSEL ((uint32_t)0x00000002) /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY ((uint32_t)0x0000001C) /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /*!< Duty selector Bit 0 */
-#define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /*!< Duty selector Bit 1 */
-#define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /*!< Duty selector Bit 2 */
-
-#define LCD_CR_BIAS ((uint32_t)0x00000060) /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */
-#define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */
-
-#define LCD_CR_MUX_SEG ((uint32_t)0x00000080) /*!< Mux Segment Enable Bit */
-
-/******************* Bit definition for LCD_FCR register ********************/
-#define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE ((uint32_t)0x00000008) /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON ((uint32_t)0x00000070) /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define LCD_FCR_PON_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define LCD_FCR_PON_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-
-#define LCD_FCR_DEAD ((uint32_t)0x00000380) /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /*!< Bit 0 */
-#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /*!< Bit 1 */
-#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /*!< Bit 2 */
-
-#define LCD_FCR_CC ((uint32_t)0x00001C00) /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define LCD_FCR_CC_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define LCD_FCR_CC_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-
-#define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /*!< Bit 0 */
-#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /*!< Bit 1 */
-#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /*!< Bit 2 */
-
-#define LCD_FCR_BLINK ((uint32_t)0x00030000) /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-
-#define LCD_FCR_DIV ((uint32_t)0x003C0000) /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS ((uint32_t)0x03C00000) /*!< PS[3:0] bits (Prescaler) */
-
-/******************* Bit definition for LCD_SR register *********************/
-#define LCD_SR_ENS ((uint32_t)0x00000001) /*!< LCD Enabled Bit */
-#define LCD_SR_SOF ((uint32_t)0x00000002) /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR ((uint32_t)0x00000004) /*!< Update Display Request Bit */
-#define LCD_SR_UDD ((uint32_t)0x00000008) /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY ((uint32_t)0x00000010) /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR ((uint32_t)0x00000020) /*!< LCD FCR Register Synchronization Flag Bit */
-
-/******************* Bit definition for LCD_CLR register ********************/
-#define LCD_CLR_SOFC ((uint32_t)0x00000002) /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC ((uint32_t)0x00000008) /*!< Update Display Done Flag Clear Bit */
-
-/******************* Bit definition for LCD_RAM register ********************/
-#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /*!< Segment Data Bits */
-
-/******************************************************************************/
-/* */
-/* Power Control */
-/* */
-/******************************************************************************/
-
-/******************** Bit definition for PWR_CR register ********************/
-#define PWR_CR_LPSDSR ((uint16_t)0x0001) /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
-#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
-#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
-#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */
-
-#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP ((uint16_t)0x0200) /*!< Ultra Low Power mode */
-#define PWR_CR_FWU ((uint16_t)0x0400) /*!< Fast wakeup */
-
-#define PWR_CR_VOS ((uint16_t)0x1800) /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0 ((uint16_t)0x0800) /*!< Bit 0 */
-#define PWR_CR_VOS_1 ((uint16_t)0x1000) /*!< Bit 1 */
-#define PWR_CR_LPRUN ((uint16_t)0x4000) /*!< Low power run mode */
-
-/******************* Bit definition for PWR_CSR register ********************/
-#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
-#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
-#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF ((uint16_t)0x0010) /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF ((uint16_t)0x0020) /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1 ((uint16_t)0x0100) /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2 ((uint16_t)0x0200) /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3 ((uint16_t)0x0400) /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/* */
-/* Reset and Clock Control */
-/* */
-/******************************************************************************/
-/******************** Bit definition for RCC_CR register ********************/
-#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION ((uint32_t)0x00000100) /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY ((uint32_t)0x00000200) /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
-#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
-#define RCC_CR_CSSON ((uint32_t)0x10000000) /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE ((uint32_t)0x60000000) /*!< RTC/LCD Prescaler */
-#define RCC_CR_RTCPRE_0 ((uint32_t)0x20000000) /*!< Bit0 */
-#define RCC_CR_RTCPRE_1 ((uint32_t)0x40000000) /*!< Bit1 */
-
-/******************** Bit definition for RCC_ICSCR register *****************/
-#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_64KHz ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 64KHz */
-#define RCC_ICSCR_MSIRANGE_128KHz ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 128KHz */
-#define RCC_ICSCR_MSIRANGE_256KHz ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 256KHz */
-#define RCC_ICSCR_MSIRANGE_512KHz ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 512KHz */
-#define RCC_ICSCR_MSIRANGE_1MHz ((uint32_t)0x00008000) /*!< Internal Multi Speed clock Range 1MHz */
-#define RCC_ICSCR_MSIRANGE_2MHz ((uint32_t)0x0000A000) /*!< Internal Multi Speed clock Range 2MHz */
-#define RCC_ICSCR_MSIRANGE_4MHz ((uint32_t)0x0000C000) /*!< Internal Multi Speed clock Range 4MHz */
-#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /*!< Internal Multi Speed clock trimming */
-
-/******************** Bit definition for RCC_CFGR register ******************/
-#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
-#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
-#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
-#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE as PLL entry clock source */
-
-
-#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
-#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
-#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /*!< Bit0 */
-#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /*!< Bit1 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000) /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /*!< System clock selected */
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /*!< PLL clock divided */
-#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /*!< LSI selected */
-#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
-#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
-#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /*!< Bit 2 */
-
-/*!< MCO Prescaler configuration */
-#define RCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000) /*!< MCO Clock divided by 1 */
-#define RCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000) /*!< MCO Clock divided by 2 */
-#define RCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000) /*!< MCO Clock divided by 4 */
-#define RCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000) /*!< MCO Clock divided by 8 */
-#define RCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000) /*!< MCO Clock divided by 16 */
-
-/*!<****************** Bit definition for RCC_CIR register ********************/
-#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF ((uint32_t)0x00000020) /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE ((uint32_t)0x00002000) /*!< MSI Ready Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC ((uint32_t)0x00200000) /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
-
-
-/***************** Bit definition for RCC_AHBRSTR register ******************/
-#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001) /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002) /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004) /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008) /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010) /*!< GPIO port E reset */
-#define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020) /*!< GPIO port H reset */
-#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000) /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000) /*!< DMA1 reset */
-
-/***************** Bit definition for RCC_APB2RSTR register *****************/
-#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004) /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008) /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010) /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
-
-/***************** Bit definition for RCC_APB1RSTR register *****************/
-#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
-#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) /*!< LCD reset */
-#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
-#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */
-#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000) /*!< Comparator interface reset */
-
-/****************** Bit definition for RCC_AHBENR register ******************/
-#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001) /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002) /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004) /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN ((uint32_t)0x00000008) /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010) /*!< GPIO port E clock enable */
-#define RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020) /*!< GPIO port H clock enable */
-#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN ((uint32_t)0x00008000) /*!< FLITF clock enable (has effect only when
- the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN ((uint32_t)0x01000000) /*!< DMA1 clock enable */
-
-
-/****************** Bit definition for RCC_APB2ENR register *****************/
-#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004) /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008) /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
-
-
-/***************** Bit definition for RCC_APB1ENR register ******************/
-#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
-#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enable */
-
-/****************** Bit definition for RCC_AHBLPENR register ****************/
-#define RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001) /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002) /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004) /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008) /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010) /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020) /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000) /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000) /*!< Flash Interface clock enabled in sleep mode
- (has effect only when the Flash memory is
- in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000) /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000) /*!< DMA1 clock enabled in sleep mode */
-
-/****************** Bit definition for RCC_APB2LPENR register ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004) /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008) /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200) /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000) /*!< USART1 clock enabled in sleep mode */
-
-/***************** Bit definition for RCC_APB1LPENR register ****************/
-#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200) /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000) /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enabled in sleep mode*/
-
-/******************* Bit definition for RCC_CSR register ********************/
-#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON ((uint32_t)0x00000100) /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY ((uint32_t)0x00000200) /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN ((uint32_t)0x00400000) /*!< RTC clock enable */
-#define RCC_CSR_RTCRST ((uint32_t)0x00800000) /*!< RTC reset */
-
-#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
-
-
-/******************************************************************************/
-/* */
-/* Real-Time Clock */
-/* */
-/******************************************************************************/
-/******************** Bits definition for RTC_TR register *******************/
-#define RTC_TR_PM ((uint32_t)0x00400000)
-#define RTC_TR_HT ((uint32_t)0x00300000)
-#define RTC_TR_HT_0 ((uint32_t)0x00100000)
-#define RTC_TR_HT_1 ((uint32_t)0x00200000)
-#define RTC_TR_HU ((uint32_t)0x000F0000)
-#define RTC_TR_HU_0 ((uint32_t)0x00010000)
-#define RTC_TR_HU_1 ((uint32_t)0x00020000)
-#define RTC_TR_HU_2 ((uint32_t)0x00040000)
-#define RTC_TR_HU_3 ((uint32_t)0x00080000)
-#define RTC_TR_MNT ((uint32_t)0x00007000)
-#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
-#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
-#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
-#define RTC_TR_MNU ((uint32_t)0x00000F00)
-#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
-#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
-#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
-#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
-#define RTC_TR_ST ((uint32_t)0x00000070)
-#define RTC_TR_ST_0 ((uint32_t)0x00000010)
-#define RTC_TR_ST_1 ((uint32_t)0x00000020)
-#define RTC_TR_ST_2 ((uint32_t)0x00000040)
-#define RTC_TR_SU ((uint32_t)0x0000000F)
-#define RTC_TR_SU_0 ((uint32_t)0x00000001)
-#define RTC_TR_SU_1 ((uint32_t)0x00000002)
-#define RTC_TR_SU_2 ((uint32_t)0x00000004)
-#define RTC_TR_SU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_DR register *******************/
-#define RTC_DR_YT ((uint32_t)0x00F00000)
-#define RTC_DR_YT_0 ((uint32_t)0x00100000)
-#define RTC_DR_YT_1 ((uint32_t)0x00200000)
-#define RTC_DR_YT_2 ((uint32_t)0x00400000)
-#define RTC_DR_YT_3 ((uint32_t)0x00800000)
-#define RTC_DR_YU ((uint32_t)0x000F0000)
-#define RTC_DR_YU_0 ((uint32_t)0x00010000)
-#define RTC_DR_YU_1 ((uint32_t)0x00020000)
-#define RTC_DR_YU_2 ((uint32_t)0x00040000)
-#define RTC_DR_YU_3 ((uint32_t)0x00080000)
-#define RTC_DR_WDU ((uint32_t)0x0000E000)
-#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
-#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
-#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
-#define RTC_DR_MT ((uint32_t)0x00001000)
-#define RTC_DR_MU ((uint32_t)0x00000F00)
-#define RTC_DR_MU_0 ((uint32_t)0x00000100)
-#define RTC_DR_MU_1 ((uint32_t)0x00000200)
-#define RTC_DR_MU_2 ((uint32_t)0x00000400)
-#define RTC_DR_MU_3 ((uint32_t)0x00000800)
-#define RTC_DR_DT ((uint32_t)0x00000030)
-#define RTC_DR_DT_0 ((uint32_t)0x00000010)
-#define RTC_DR_DT_1 ((uint32_t)0x00000020)
-#define RTC_DR_DU ((uint32_t)0x0000000F)
-#define RTC_DR_DU_0 ((uint32_t)0x00000001)
-#define RTC_DR_DU_1 ((uint32_t)0x00000002)
-#define RTC_DR_DU_2 ((uint32_t)0x00000004)
-#define RTC_DR_DU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_CR register *******************/
-#define RTC_CR_COE ((uint32_t)0x00800000)
-#define RTC_CR_OSEL ((uint32_t)0x00600000)
-#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
-#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
-#define RTC_CR_POL ((uint32_t)0x00100000)
-#define RTC_CR_BCK ((uint32_t)0x00040000)
-#define RTC_CR_SUB1H ((uint32_t)0x00020000)
-#define RTC_CR_ADD1H ((uint32_t)0x00010000)
-#define RTC_CR_TSIE ((uint32_t)0x00008000)
-#define RTC_CR_WUTIE ((uint32_t)0x00004000)
-#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
-#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
-#define RTC_CR_TSE ((uint32_t)0x00000800)
-#define RTC_CR_WUTE ((uint32_t)0x00000400)
-#define RTC_CR_ALRBE ((uint32_t)0x00000200)
-#define RTC_CR_ALRAE ((uint32_t)0x00000100)
-#define RTC_CR_DCE ((uint32_t)0x00000080)
-#define RTC_CR_FMT ((uint32_t)0x00000040)
-#define RTC_CR_REFCKON ((uint32_t)0x00000010)
-#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
-#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
-#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
-#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
-#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
-
-/******************** Bits definition for RTC_ISR register ******************/
-#define RTC_ISR_TAMPF ((uint32_t)0x00002000)
-#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
-#define RTC_ISR_TSF ((uint32_t)0x00000800)
-#define RTC_ISR_WUTF ((uint32_t)0x00000400)
-#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
-#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
-#define RTC_ISR_INIT ((uint32_t)0x00000080)
-#define RTC_ISR_INITF ((uint32_t)0x00000040)
-#define RTC_ISR_RSF ((uint32_t)0x00000020)
-#define RTC_ISR_INITS ((uint32_t)0x00000010)
-#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
-#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
-#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
-
-/******************** Bits definition for RTC_PRER register *****************/
-#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
-
-/******************** Bits definition for RTC_WUTR register *****************/
-#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
-
-/******************** Bits definition for RTC_CALIBR register ***************/
-#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
-#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
-
-/******************** Bits definition for RTC_ALRMAR register ***************/
-#define RTC_ALRMAR_MSK3 ((uint32_t)0x80000000)
-#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
-#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
-#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
-#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
-#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
-#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
-#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
-#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
-#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
-#define RTC_ALRMAR_MSK2 ((uint32_t)0x00800000)
-#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
-#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
-#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
-#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
-#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
-#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
-#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
-#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
-#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
-#define RTC_ALRMAR_MSK1 ((uint32_t)0x00008000)
-#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
-#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
-#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
-#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
-#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
-#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
-#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
-#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
-#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
-#define RTC_ALRMAR_MSK0 ((uint32_t)0x00000080)
-#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
-#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
-#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
-#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
-#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
-#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
-#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
-#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
-#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_ALRMBR register ***************/
-#define RTC_ALRMBR_MSK3 ((uint32_t)0x80000000)
-#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
-#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
-#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
-#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
-#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
-#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
-#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
-#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
-#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
-#define RTC_ALRMBR_MSK2 ((uint32_t)0x00800000)
-#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
-#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
-#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
-#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
-#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
-#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
-#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
-#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
-#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
-#define RTC_ALRMBR_MSK1 ((uint32_t)0x00008000)
-#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
-#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
-#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
-#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
-#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
-#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
-#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
-#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
-#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
-#define RTC_ALRMBR_MSK0 ((uint32_t)0x00000080)
-#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
-#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
-#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
-#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
-#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
-#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
-#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
-#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
-#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_WRP register ******************/
-#define RTC_WRP_KEY ((uint32_t)0x000000FF)
-
-/******************** Bits definition for RTC_TSTR register *****************/
-#define RTC_TSTR_PM ((uint32_t)0x00400000)
-#define RTC_TSTR_HT ((uint32_t)0x00300000)
-#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
-#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
-#define RTC_TSTR_HU ((uint32_t)0x000F0000)
-#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
-#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
-#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
-#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
-#define RTC_TSTR_MNT ((uint32_t)0x00007000)
-#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
-#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
-#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
-#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
-#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
-#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
-#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
-#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
-#define RTC_TSTR_ST ((uint32_t)0x00000070)
-#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
-#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
-#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
-#define RTC_TSTR_SU ((uint32_t)0x0000000F)
-#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
-#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
-#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
-#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_TSDR register *****************/
-#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
-#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
-#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
-#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
-#define RTC_TSDR_MT ((uint32_t)0x00001000)
-#define RTC_TSDR_MU ((uint32_t)0x00000F00)
-#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
-#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
-#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
-#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
-#define RTC_TSDR_DT ((uint32_t)0x00000030)
-#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
-#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
-#define RTC_TSDR_DU ((uint32_t)0x0000000F)
-#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
-#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
-#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
-#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_TAFCR register ****************/
-#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
-#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
-#define RTC_TAFCR_TAMPEDGE ((uint32_t)0x00000002)
-#define RTC_TAFCR_TAMPE ((uint32_t)0x00000001)
-
-/******************** Bits definition for RTC_BK0R register *****************/
-#define RTC_BK0R_BCK ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BK1R register *****************/
-#define RTC_BK1R_BCK ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BK2R register *****************/
-#define RTC_BK2R_BCK ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BK3R register *****************/
-#define RTC_BK3R_BCK ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BK4R register *****************/
-#define RTC_BK4R_BCK ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BK5R register *****************/
-#define RTC_BK5R_BCK ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BK6R register *****************/
-#define RTC_BK6R_BCK ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BK7R register *****************/
-#define RTC_BK7R_BCK ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BK8R register *****************/
-#define RTC_BK8R_BCK ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BK9R register *****************/
-#define RTC_BK9R_BCK ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BK10R register ****************/
-#define RTC_BK10R_BCK ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BK11R register ****************/
-#define RTC_BK11R_BCK ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BK12R register ****************/
-#define RTC_BK12R_BCK ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BK13R register ****************/
-#define RTC_BK13R_BCK ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BK14R register ****************/
-#define RTC_BK14R_BCK ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BK15R register ****************/
-#define RTC_BK15R_BCK ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BK16R register ****************/
-#define RTC_BK16R_BCK ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BK17R register ****************/
-#define RTC_BK17R_BCK ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BK18R register ****************/
-#define RTC_BK18R_BCK ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BK19R register ****************/
-#define RTC_BK19R_BCK ((uint32_t)0xFFFFFFFF)
-
-/******************************************************************************/
-/* */
-/* Serial Peripheral Interface */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for SPI_CR1 register ********************/
-#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */
-#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */
-#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */
-
-#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */
-#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */
-#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */
-
-#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */
-#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */
-#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */
-#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */
-#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
-
-/******************* Bit definition for SPI_CR2 register ********************/
-#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */
-#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */
-
-/******************** Bit definition for SPI_SR register ********************/
-#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */
-#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */
-#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */
-#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */
-#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */
-
-/******************** Bit definition for SPI_DR register ********************/
-#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */
-
-/******************* Bit definition for SPI_CRCPR register ******************/
-#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
-
-/****************** Bit definition for SPI_RXCRCR register ******************/
-#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */
-
-/****************** Bit definition for SPI_TXCRCR register ******************/
-#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */
-
-/******************************************************************************/
-/* */
-/* System Configuration (SYSCFG) */
-/* */
-/******************************************************************************/
-/***************** Bit definition for SYSCFG_MEMRMP register ****************/
-#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-
-/***************** Bit definition for SYSCFG_PMC register *******************/
-#define SYSCFG_PMC_USB_PU ((uint32_t)0x00000001) /*!< SYSCFG PMC */
-
-/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
-#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
-
-/**
- * @brief EXTI0 configuration
- */
-#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0005) /*!< PH[0] pin */
-
-/**
- * @brief EXTI1 configuration
- */
-#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0050) /*!< PH[1] pin */
-
-/**
- * @brief EXTI2 configuration
- */
-#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0500) /*!< PH[2] pin */
-
-/**
- * @brief EXTI3 configuration
- */
-#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
-
-/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
-#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
-
-/**
- * @brief EXTI4 configuration
- */
-#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
-
-/**
- * @brief EXTI5 configuration
- */
-#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
-
-/**
- * @brief EXTI6 configuration
- */
-#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
-
-/**
- * @brief EXTI7 configuration
- */
-#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
-
-/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
-#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
-
-/**
- * @brief EXTI8 configuration
- */
-#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
-
-/**
- * @brief EXTI9 configuration
- */
-#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
-
-/**
- * @brief EXTI10 configuration
- */
-#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */
-
-/**
- * @brief EXTI11 configuration
- */
-#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
-
-/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
-#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
-
-/**
- * @brief EXTI12 configuration
- */
-#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
-
-/**
- * @brief EXTI13 configuration
- */
-#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
-
-/**
- * @brief EXTI14 configuration
- */
-#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
-
-/**
- * @brief EXTI15 configuration
- */
-#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
-
-/******************************************************************************/
-/* */
-/* Routing Interface (RI) */
-/* */
-/******************************************************************************/
-
-/******************** Bit definition for RI_ICR register ********************/
-#define RI_ICR_IC1Z ((uint32_t)0x0000000F) /*!< IC1Z[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1Z_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define RI_ICR_IC1Z_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define RI_ICR_IC1Z_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define RI_ICR_IC1Z_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-
-#define RI_ICR_IC2Z ((uint32_t)0x000000F0) /*!< IC2Z[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2Z_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define RI_ICR_IC2Z_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define RI_ICR_IC2Z_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-#define RI_ICR_IC2Z_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-
-#define RI_ICR_IC3Z ((uint32_t)0x00000F00) /*!< IC3Z[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3Z_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define RI_ICR_IC3Z_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define RI_ICR_IC3Z_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define RI_ICR_IC3Z_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-
-#define RI_ICR_IC4Z ((uint32_t)0x0000F000) /*!< IC2Z[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC4Z_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define RI_ICR_IC4Z_1 ((uint32_t)0x00002000) /*!< Bit 1 */
-#define RI_ICR_IC4Z_2 ((uint32_t)0x00004000) /*!< Bit 2 */
-#define RI_ICR_IC4Z_3 ((uint32_t)0x00008000) /*!< Bit 3 */
-
-#define RI_ICR_TIM ((uint32_t)0x00030000) /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define RI_ICR_TIM_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-
-#define RI_ICR_IC1 ((uint32_t)0x00040000) /*!< Input capture 1 */
-#define RI_ICR_IC2 ((uint32_t)0x00080000) /*!< Input capture 2 */
-#define RI_ICR_IC3 ((uint32_t)0x00100000) /*!< Input capture 3 */
-#define RI_ICR_IC4 ((uint32_t)0x00200000) /*!< Input capture 4 */
-
-/******************** Bit definition for RI_ASCR1 register ********************/
-#define RI_ASCR1_CH ((uint32_t)0x03FCFFFF) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define RI_ASCR1_CH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define RI_ASCR1_CH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define RI_ASCR1_CH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define RI_ASCR1_CH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define RI_ASCR1_CH_5 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define RI_ASCR1_CH_6 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define RI_ASCR1_CH_7 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define RI_ASCR1_CH_8 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define RI_ASCR1_CH_9 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define RI_ASCR1_CH_10 ((uint32_t)0x00000400) /*!< Bit 10 */
-#define RI_ASCR1_CH_11 ((uint32_t)0x00000800) /*!< Bit 11 */
-#define RI_ASCR1_CH_12 ((uint32_t)0x00001000) /*!< Bit 12 */
-#define RI_ASCR1_CH_13 ((uint32_t)0x00002000) /*!< Bit 13 */
-#define RI_ASCR1_CH_14 ((uint32_t)0x00004000) /*!< Bit 14 */
-#define RI_ASCR1_CH_15 ((uint32_t)0x00008000) /*!< Bit 15 */
-#define RI_ASCR1_CH_18 ((uint32_t)0x00040000) /*!< Bit 18 */
-#define RI_ASCR1_CH_19 ((uint32_t)0x00080000) /*!< Bit 19 */
-#define RI_ASCR1_CH_20 ((uint32_t)0x00100000) /*!< Bit 20 */
-#define RI_ASCR1_CH_21 ((uint32_t)0x00200000) /*!< Bit 21 */
-#define RI_ASCR1_CH_22 ((uint32_t)0x00400000) /*!< Bit 22 */
-#define RI_ASCR1_CH_23 ((uint32_t)0x00800000) /*!< Bit 23 */
-#define RI_ASCR1_CH_24 ((uint32_t)0x01000000) /*!< Bit 24 */
-#define RI_ASCR1_CH_25 ((uint32_t)0x02000000) /*!< Bit 25 */
-
-#define RI_ASCR1_VCOMP ((uint32_t)0x04000000) /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_SCM ((uint32_t)0x80000000) /*!< I/O Switch control mode */
-
-/******************** Bit definition for RI_ASCR2 register ********************/
-#define RI_ASCR2_GR10_1 ((uint32_t)0x00000001) /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2 ((uint32_t)0x00000002) /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3 ((uint32_t)0x00000004) /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4 ((uint32_t)0x00000008) /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_1 ((uint32_t)0x00000010) /*!< GR6-1 selection bit */
-#define RI_ASCR2_GR6_2 ((uint32_t)0x00000020) /*!< GR6-2 selection bit */
-#define RI_ASCR2_GR5_1 ((uint32_t)0x00000040) /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2 ((uint32_t)0x00000080) /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3 ((uint32_t)0x00000100) /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1 ((uint32_t)0x00000200) /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2 ((uint32_t)0x00000400) /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3 ((uint32_t)0x00000800) /*!< GR4-3 selection bit */
-
-
-/******************** Bit definition for RI_HYSCR1 register ********************/
-#define RI_HYSCR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define RI_HYSCR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define RI_HYSCR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define RI_HYSCR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define RI_HYSCR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define RI_HYSCR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define RI_HYSCR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define RI_HYSCR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define RI_HYSCR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define RI_HYSCR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define RI_HYSCR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
-#define RI_HYSCR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
-#define RI_HYSCR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
-#define RI_HYSCR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
-#define RI_HYSCR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
-#define RI_HYSCR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
-
-#define RI_HYSCR1_PB ((uint32_t)0xFFFF0000) /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define RI_HYSCR1_PB_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define RI_HYSCR1_PB_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define RI_HYSCR1_PB_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define RI_HYSCR1_PB_4 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define RI_HYSCR1_PB_5 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define RI_HYSCR1_PB_6 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define RI_HYSCR1_PB_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define RI_HYSCR1_PB_8 ((uint32_t)0x01000000) /*!< Bit 8 */
-#define RI_HYSCR1_PB_9 ((uint32_t)0x02000000) /*!< Bit 9 */
-#define RI_HYSCR1_PB_10 ((uint32_t)0x04000000) /*!< Bit 10 */
-#define RI_HYSCR1_PB_11 ((uint32_t)0x08000000) /*!< Bit 11 */
-#define RI_HYSCR1_PB_12 ((uint32_t)0x10000000) /*!< Bit 12 */
-#define RI_HYSCR1_PB_13 ((uint32_t)0x20000000) /*!< Bit 13 */
-#define RI_HYSCR1_PB_14 ((uint32_t)0x40000000) /*!< Bit 14 */
-#define RI_HYSCR1_PB_15 ((uint32_t)0x80000000) /*!< Bit 15 */
-
-/******************** Bit definition for RI_HYSCR2 register ********************/
-#define RI_HYSCR2_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define RI_HYSCR2_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define RI_HYSCR2_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define RI_HYSCR2_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define RI_HYSCR2_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define RI_HYSCR2_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define RI_HYSCR2_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define RI_HYSCR2_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define RI_HYSCR2_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define RI_HYSCR2_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define RI_HYSCR2_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
-#define RI_HYSCR2_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
-#define RI_HYSCR2_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
-#define RI_HYSCR2_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
-#define RI_HYSCR2_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
-#define RI_HYSCR2_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
-
-#define RI_HYSCR2_PD ((uint32_t)0xFFFF0000) /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define RI_HYSCR2_PD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define RI_HYSCR2_PD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define RI_HYSCR2_PD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define RI_HYSCR2_PD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define RI_HYSCR2_PD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define RI_HYSCR2_PD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define RI_HYSCR2_PD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define RI_HYSCR2_PD_8 ((uint32_t)0x01000000) /*!< Bit 8 */
-#define RI_HYSCR2_PD_9 ((uint32_t)0x02000000) /*!< Bit 9 */
-#define RI_HYSCR2_PD_10 ((uint32_t)0x04000000) /*!< Bit 10 */
-#define RI_HYSCR2_PD_11 ((uint32_t)0x08000000) /*!< Bit 11 */
-#define RI_HYSCR2_PD_12 ((uint32_t)0x10000000) /*!< Bit 12 */
-#define RI_HYSCR2_PD_13 ((uint32_t)0x20000000) /*!< Bit 13 */
-#define RI_HYSCR2_PD_14 ((uint32_t)0x40000000) /*!< Bit 14 */
-#define RI_HYSCR2_PD_15 ((uint32_t)0x80000000) /*!< Bit 15 */
-
-/******************** Bit definition for RI_HYSCR3 register ********************/
-#define RI_HYSCR2_PE ((uint32_t)0x0000FFFF) /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR2_PE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define RI_HYSCR2_PE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define RI_HYSCR2_PE_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define RI_HYSCR2_PE_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define RI_HYSCR2_PE_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define RI_HYSCR2_PE_5 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define RI_HYSCR2_PE_6 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define RI_HYSCR2_PE_7 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define RI_HYSCR2_PE_8 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define RI_HYSCR2_PE_9 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define RI_HYSCR2_PE_10 ((uint32_t)0x00000400) /*!< Bit 10 */
-#define RI_HYSCR2_PE_11 ((uint32_t)0x00000800) /*!< Bit 11 */
-#define RI_HYSCR2_PE_12 ((uint32_t)0x00001000) /*!< Bit 12 */
-#define RI_HYSCR2_PE_13 ((uint32_t)0x00002000) /*!< Bit 13 */
-#define RI_HYSCR2_PE_14 ((uint32_t)0x00004000) /*!< Bit 14 */
-#define RI_HYSCR2_PE_15 ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/******************************************************************************/
-/* */
-/* TIM */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for TIM_CR1 register ********************/
-#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
-#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
-#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
-#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
-#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
-
-#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
-#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
-
-#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
-
-/******************* Bit definition for TIM_CR2 register ********************/
-#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
-#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
-#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
-
-#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
-#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
-#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
-#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
-#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
-#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
-#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
-#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
-
-/******************* Bit definition for TIM_SMCR register *******************/
-#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
-
-#define TIM_SMCR_OCCS ((uint16_t)0x0008) /*!<OCCS bits (OCref Clear Selection) */
-
-#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
-
-#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
-#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
-#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
-
-#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
-
-#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
-#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
-
-/******************* Bit definition for TIM_DIER register *******************/
-#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
-#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
-#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
-#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
-#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
-
-/******************** Bit definition for TIM_SR register ********************/
-#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */
-#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
-#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */
-#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
-
-/******************* Bit definition for TIM_EGR register ********************/
-#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
-#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
-#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
-#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */
-
-/****************** Bit definition for TIM_CCMR1 register *******************/
-#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
-
-#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
-
-#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
-
-#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
-
-#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
-#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
-
-#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
-#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
-
-#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
-
-#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
-#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
-
-/****************** Bit definition for TIM_CCMR2 register *******************/
-#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
-
-#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
-
-#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
-
-#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
-
-#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
-#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
-
-#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
-#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
-
-#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
-
-#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
-#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
-
-/******************* Bit definition for TIM_CCER register *******************/
-#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
-#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
-#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
-#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
-
-/******************* Bit definition for TIM_CNT register ********************/
-#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
-
-/******************* Bit definition for TIM_PSC register ********************/
-#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
-
-/******************* Bit definition for TIM_ARR register ********************/
-#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
-
-/******************* Bit definition for TIM_RCR register ********************/
-#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
-
-/******************* Bit definition for TIM_CCR1 register *******************/
-#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
-
-/******************* Bit definition for TIM_CCR2 register *******************/
-#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
-
-/******************* Bit definition for TIM_CCR3 register *******************/
-#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
-
-/******************* Bit definition for TIM_CCR4 register *******************/
-#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
-
-/******************* Bit definition for TIM_DCR register ********************/
-#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
-#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
-#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
-
-#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
-#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
-#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
-#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
-
-/******************* Bit definition for TIM_DMAR register *******************/
-#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
-
-/******************* Bit definition for TIM_OR register *********************/
-#define TIM_OR_TI1RMP ((uint16_t)0x0003) /*!<Option register for TI1 Remapping */
-#define TIM_OR_TI1RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_OR_TI1RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */
-
-/******************************************************************************/
-/* */
-/* Universal Synchronous Asynchronous Receiver Transmitter */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for USART_SR register *******************/
-#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */
-#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */
-#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */
-#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */
-#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */
-#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */
-#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */
-#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */
-#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */
-#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */
-
-/******************* Bit definition for USART_DR register *******************/
-#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */
-
-/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
-
-/****************** Bit definition for USART_CR1 register *******************/
-#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */
-#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */
-#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */
-#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */
-#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */
-#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */
-#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */
-#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */
-#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */
-#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< Oversampling mode */
-
-/****************** Bit definition for USART_CR2 register *******************/
-#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */
-#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */
-#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */
-#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */
-
-#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */
-#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */
-
-#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */
-
-/****************** Bit definition for USART_CR3 register *******************/
-#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */
-#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */
-#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */
-#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */
-#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */
-#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */
-#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One sample bit method enable */
-
-/****************** Bit definition for USART_GTPR register ******************/
-#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */
-#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */
-#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */
-#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */
-#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */
-#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */
-#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */
-#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */
-
-#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */
-
-/******************************************************************************/
-/* */
-/* USB */
-/* */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-/******************* Bit definition for USB_EP0R register *******************/
-#define USB_EP0R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
-
-#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
-#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
-
-#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
-
-#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP1R register *******************/
-#define USB_EP1R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
-
-#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
-#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
-
-#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
-
-#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP2R register *******************/
-#define USB_EP2R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
-
-#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
-#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
-
-#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
-
-#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP3R register *******************/
-#define USB_EP3R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
-
-#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
-#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
-
-#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
-
-#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP4R register *******************/
-#define USB_EP4R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
-
-#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
-#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
-
-#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
-
-#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP5R register *******************/
-#define USB_EP5R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
-
-#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
-#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
-
-#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
-
-#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP6R register *******************/
-#define USB_EP6R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
-
-#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
-#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
-
-#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
-
-#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP7R register *******************/
-#define USB_EP7R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
-
-#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
-#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
-
-#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
-
-#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-/******************* Bit definition for USB_CNTR register *******************/
-#define USB_CNTR_FRES ((uint16_t)0x0001) /*!<Force USB Reset */
-#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!<Power down */
-#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!<Low-power mode */
-#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!<Force suspend */
-#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!<Resume request */
-#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!<Correct Transfer Interrupt Mask */
-
-/******************* Bit definition for USB_ISTR register *******************/
-#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!<Endpoint Identifier */
-#define USB_ISTR_DIR ((uint16_t)0x0010) /*!<Direction of transaction */
-#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF ((uint16_t)0x0200) /*!<Start Of Frame */
-#define USB_ISTR_RESET ((uint16_t)0x0400) /*!<USB RESET request */
-#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!<Suspend mode request */
-#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!<Wake up */
-#define USB_ISTR_ERR ((uint16_t)0x2000) /*!<Error */
-#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR ((uint16_t)0x8000) /*!<Correct Transfer */
-
-/******************* Bit definition for USB_FNR register ********************/
-#define USB_FNR_FN ((uint16_t)0x07FF) /*!<Frame Number */
-#define USB_FNR_LSOF ((uint16_t)0x1800) /*!<Lost SOF */
-#define USB_FNR_LCK ((uint16_t)0x2000) /*!<Locked */
-#define USB_FNR_RXDM ((uint16_t)0x4000) /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP ((uint16_t)0x8000) /*!<Receive Data + Line Status */
-
-/****************** Bit definition for USB_DADDR register *******************/
-#define USB_DADDR_ADD ((uint8_t)0x7F) /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!<Bit 0 */
-#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!<Bit 1 */
-#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!<Bit 2 */
-#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!<Bit 3 */
-#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!<Bit 4 */
-#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!<Bit 5 */
-#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!<Bit 6 */
-
-#define USB_DADDR_EF ((uint8_t)0x80) /*!<Enable Function */
-
-/****************** Bit definition for USB_BTABLE register ******************/
-#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/***************** Bit definition for USB_ADDR0_TX register *****************/
-#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */
-
-/***************** Bit definition for USB_ADDR1_TX register *****************/
-#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */
-
-/***************** Bit definition for USB_ADDR2_TX register *****************/
-#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */
-
-/***************** Bit definition for USB_ADDR3_TX register *****************/
-#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */
-
-/***************** Bit definition for USB_ADDR4_TX register *****************/
-#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */
-
-/***************** Bit definition for USB_ADDR5_TX register *****************/
-#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */
-
-/***************** Bit definition for USB_ADDR6_TX register *****************/
-#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */
-
-/***************** Bit definition for USB_ADDR7_TX register *****************/
-#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/***************** Bit definition for USB_COUNT0_TX register ****************/
-#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */
-
-/***************** Bit definition for USB_COUNT1_TX register ****************/
-#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */
-
-/***************** Bit definition for USB_COUNT2_TX register ****************/
-#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */
-
-/***************** Bit definition for USB_COUNT3_TX register ****************/
-#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */
-
-/***************** Bit definition for USB_COUNT4_TX register ****************/
-#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */
-
-/***************** Bit definition for USB_COUNT5_TX register ****************/
-#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */
-
-/***************** Bit definition for USB_COUNT6_TX register ****************/
-#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */
-
-/***************** Bit definition for USB_COUNT7_TX register ****************/
-#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
-
-/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
-
-/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
-
-/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
-
-/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
-
-/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
-
-/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
-
-/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
-
-/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
-
-/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
-
-/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
-
-/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
-
-/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
-
-/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
-
-/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
-
-/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/***************** Bit definition for USB_ADDR0_RX register *****************/
-#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */
-
-/***************** Bit definition for USB_ADDR1_RX register *****************/
-#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */
-
-/***************** Bit definition for USB_ADDR2_RX register *****************/
-#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */
-
-/***************** Bit definition for USB_ADDR3_RX register *****************/
-#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */
-
-/***************** Bit definition for USB_ADDR4_RX register *****************/
-#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */
-
-/***************** Bit definition for USB_ADDR5_RX register *****************/
-#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */
-
-/***************** Bit definition for USB_ADDR6_RX register *****************/
-#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */
-
-/***************** Bit definition for USB_ADDR7_RX register *****************/
-#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/***************** Bit definition for USB_COUNT0_RX register ****************/
-#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
-#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
-#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-
-#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT1_RX register ****************/
-#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
-#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
-#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-
-#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT2_RX register ****************/
-#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
-#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
-#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-
-#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT3_RX register ****************/
-#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
-#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
-#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-
-#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT4_RX register ****************/
-#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
-#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
-#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-
-#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT5_RX register ****************/
-#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
-#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
-#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-
-#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT6_RX register ****************/
-#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
-#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
-#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-
-#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT7_RX register ****************/
-#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
-#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
-#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
-#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-
-#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
-
-/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
-
-/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
-
-/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
-
-/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
-
-/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
-
-/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
-
-/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
-
-/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/* */
-/* Window WATCHDOG */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for WWDG_CR register ********************/
-#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */
-#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */
-#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */
-#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */
-#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */
-#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */
-#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */
-
-#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */
-
-/******************* Bit definition for WWDG_CFR register *******************/
-#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */
-#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */
-#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */
-#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */
-#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */
-#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */
-#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */
-
-#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */
-#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */
-
-#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */
-
-/******************* Bit definition for WWDG_SR register ********************/
-#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */
-
-/******************************************************************************/
-/* */
-/* SystemTick */
-/* */
-/******************************************************************************/
-
-/***************** Bit definition for SysTick_CTRL register *****************/
-#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
-#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
-#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
-#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
-
-/***************** Bit definition for SysTick_LOAD register *****************/
-#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/***************** Bit definition for SysTick_VAL register ******************/
-#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
-
-/***************** Bit definition for SysTick_CALIB register ****************/
-#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
-#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
-#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/* */
-/* Nested Vectored Interrupt Controller */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for NVIC_ISER register *******************/
-#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
-#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
-#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
-#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
-#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
-#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
-#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
-#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
-#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
-#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
-#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
-#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
-#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
-#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
-#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
-#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
-#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
-#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
-#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
-#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
-#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
-#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
-#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
-#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
-#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
-#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
-#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
-#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
-#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
-#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
-#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
-#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
-#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
-
-/****************** Bit definition for NVIC_ICER register *******************/
-#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
-#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
-#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
-#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
-#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
-#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
-#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
-#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
-#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
-#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
-#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
-#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
-#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
-#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
-#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
-#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
-#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
-#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
-#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
-#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
-#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
-#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
-#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
-#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
-#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
-#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
-#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
-#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
-#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
-#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
-#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
-#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
-#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
-
-/****************** Bit definition for NVIC_ISPR register *******************/
-#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
-#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
-#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
-#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
-#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
-#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
-#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
-#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
-#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
-#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
-#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
-#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
-#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
-#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
-#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
-#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
-#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
-#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
-#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
-#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
-#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
-#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
-#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
-#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
-#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
-#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
-#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
-#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
-#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
-#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
-#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
-#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
-#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
-
-/****************** Bit definition for NVIC_ICPR register *******************/
-#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
-#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
-#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
-#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
-#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
-#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
-#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
-#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
-#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
-#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
-#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
-#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
-#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
-#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
-#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
-#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
-#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
-#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
-#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
-#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
-#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
-#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
-#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
-#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
-#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
-#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
-#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
-#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
-#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
-#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
-#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
-#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
-#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
-
-/****************** Bit definition for NVIC_IABR register *******************/
-#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
-#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
-#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
-#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
-#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
-#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
-#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
-#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
-#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
-#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
-#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
-#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
-#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
-#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
-#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
-#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
-#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
-#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
-#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
-#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
-#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
-#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
-#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
-#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
-#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
-#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
-#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
-#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
-#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
-#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
-#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
-#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
-#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
-
-/****************** Bit definition for NVIC_PRI0 register *******************/
-#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
-#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
-#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
-#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
-
-/****************** Bit definition for NVIC_PRI1 register *******************/
-#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
-#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
-#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
-#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
-
-/****************** Bit definition for NVIC_PRI2 register *******************/
-#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
-#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
-#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
-#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
-
-/****************** Bit definition for NVIC_PRI3 register *******************/
-#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
-#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
-#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
-#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
-
-/****************** Bit definition for NVIC_PRI4 register *******************/
-#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
-#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
-#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
-#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
-
-/****************** Bit definition for NVIC_PRI5 register *******************/
-#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
-#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
-#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
-#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
-
-/****************** Bit definition for NVIC_PRI6 register *******************/
-#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
-#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
-#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
-#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
-
-/****************** Bit definition for NVIC_PRI7 register *******************/
-#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
-#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
-#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
-#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
-
-/****************** Bit definition for SCB_CPUID register *******************/
-#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
-#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
-#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
-#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
-#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
-
-/******************* Bit definition for SCB_ICSR register *******************/
-#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
-#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
-#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
-#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
-#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
-#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
-#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
-#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
-
-/******************* Bit definition for SCB_VTOR register *******************/
-#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
-#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
-
-/*!<***************** Bit definition for SCB_AIRCR register *******************/
-#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
-#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
-#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
-
-#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
-#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-/* prority group configuration */
-#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
-#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/******************* Bit definition for SCB_SCR register ********************/
-#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */
-#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */
-#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */
-
-/******************** Bit definition for SCB_CCR register *******************/
-#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */
-#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */
-#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */
-#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/******************* Bit definition for SCB_SHPR register ********************/
-#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/****************** Bit definition for SCB_SHCSR register *******************/
-#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
-#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
-#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
-#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
-#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
-#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
-#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
-#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
-#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
-#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
-#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
-#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
-#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
-#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
-
-/******************* Bit definition for SCB_CFSR register *******************/
-/*!< MFSR */
-#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
-#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
-#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
-#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
-#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
-#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
-#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
-#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
-#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
-#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */
-#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
-#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
-#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
-#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/******************* Bit definition for SCB_HFSR register *******************/
-#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */
-#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
-
-/******************* Bit definition for SCB_DFSR register *******************/
-#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */
-#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */
-#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */
-#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */
-#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */
-
-/******************* Bit definition for SCB_MMFAR register ******************/
-#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
-
-/******************* Bit definition for SCB_BFAR register *******************/
-#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
-
-/******************* Bit definition for SCB_afsr register *******************/
-#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
-/**
- * @}
- */
-
- /**
- * @}
- */
-
-#ifdef USE_STDPERIPH_DRIVER
- #include "stm32l1xx_conf.h"
-#endif
-
-/** @addtogroup Exported_macro
- * @{
- */
-
-#define SET_BIT(REG, BIT) ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT) ((REG) & (BIT))
-
-#define CLEAR_REG(REG) ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL) ((REG) = (VAL))
-
-#define READ_REG(REG) ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1XX_H */
-
-/**
- * @}
- */
-
- /**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/system_stm32l1xx.h b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/system_stm32l1xx.h
deleted file mode 100644
index 9f2ec07..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/system_stm32l1xx.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32l1xx.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
- ******************************************************************************
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32l1xx_system
- * @{
- */
-
-/**
- * @brief Define to prevent recursive inclusion
- */
-#ifndef __SYSTEM_STM32L1XX_H
-#define __SYSTEM_STM32L1XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup STM32L1xx_System_Includes
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @addtogroup STM32L1xx_System_Exported_types
- * @{
- */
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32L1xx_System_Exported_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32L1xx_System_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32L1xx_System_Exported_Functions
- * @{
- */
-
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32L1XX_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CMSIS changes.htm b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CMSIS changes.htm
deleted file mode 100644
index 162ffcc..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CMSIS changes.htm
+++ /dev/null
@@ -1,320 +0,0 @@
-<html>
-
-<head>
-<title>CMSIS Changes</title>
-<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
-<meta name="GENERATOR" content="Microsoft FrontPage 6.0">
-<meta name="ProgId" content="FrontPage.Editor.Document">
-<style>
-<!--
-/*-----------------------------------------------------------
-Keil Software CHM Style Sheet
------------------------------------------------------------*/
-body { color: #000000; background-color: #FFFFFF; font-size: 75%; font-family:
- Verdana, Arial, 'Sans Serif' }
-a:link { color: #0000FF; text-decoration: underline }
-a:visited { color: #0000FF; text-decoration: underline }
-a:active { color: #FF0000; text-decoration: underline }
-a:hover { color: #FF0000; text-decoration: underline }
-h1 { font-family: Verdana; font-size: 18pt; color: #000080; font-weight: bold;
- text-align: Center; margin-right: 3 }
-h2 { font-family: Verdana; font-size: 14pt; color: #000080; font-weight: bold;
- background-color: #CCCCCC; margin-top: 24; margin-bottom: 3;
- padding: 6 }
-h3 { font-family: Verdana; font-size: 10pt; font-weight: bold; background-color:
- #CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 }
-pre { font-family: Courier New; font-size: 10pt; background-color: #CCFFCC;
- margin-left: 24; margin-right: 24 }
-ul { list-style-type: square; margin-top: 6pt; margin-bottom: 0 }
-ol { margin-top: 6pt; margin-bottom: 0 }
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- bottom; padding-right: 6pt }
-tr { text-align: left; vertical-align: top }
-td { text-align: left; vertical-align: top; padding-right: 6pt }
-.ToolT { font-size: 8pt; color: #808080 }
-.TinyT { font-size: 8pt; text-align: Center }
-code { color: #000000; background-color: #E0E0E0; font-family: 'Courier New', Courier;
- line-height: 120%; font-style: normal }
-/*-----------------------------------------------------------
-Notes
------------------------------------------------------------*/
-p.note { font-weight: bold; clear: both; margin-bottom: 3pt; padding-top: 6pt }
-/*-----------------------------------------------------------
-Expanding/Contracting Divisions
------------------------------------------------------------*/
-#expand { text-decoration: none; margin-bottom: 3pt }
-img.expand { border-style: none; border-width: medium }
-div.expand { display: none; margin-left: 9pt; margin-top: 0 }
-/*-----------------------------------------------------------
-Where List Tags
------------------------------------------------------------*/
-p.wh { font-weight: bold; clear: both; margin-top: 6pt; margin-bottom: 3pt }
-table.wh { width: 100% }
-td.whItem { white-space: nowrap; font-style: italic; padding-right: 6pt; padding-bottom:
- 6pt }
-td.whDesc { padding-bottom: 6pt }
-/*-----------------------------------------------------------
-Keil Table Tags
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-table.kt { border: 1pt solid #000000 }
-th.kt { white-space: nowrap; border-bottom: 1pt solid #000000; padding-left: 6pt;
- padding-right: 6pt; padding-top: 4pt; padding-bottom: 4pt }
-tr.kt { }
-td.kt { color: #000000; background-color: #E0E0E0; border-top: 1pt solid #A0A0A0;
- padding-left: 6pt; padding-right: 6pt; padding-top: 2pt;
- padding-bottom: 2pt }
-/*-----------------------------------------------------------
------------------------------------------------------------*/
--->
-
-</style>
-</head>
-
-<body>
-
-<h1>Changes to CMSIS version V1.20</h1>
-
-<hr>
-
-<h2>1. Removed CMSIS Middelware packages</h2>
-<p>
- CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.
-</p>
-
-<h2>2. SystemFrequency renamed to SystemCoreClock</h2>
-<p>
- The variable name <strong>SystemCoreClock</strong> is more precise than <strong>SystemFrequency</strong>
- because the variable holds the clock value at which the core is running.
-</p>
-
-<h2>3. Changed startup concept</h2>
-<p>
- The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit
- from main) has the weakness that it does not work for controllers which need a already
- configuerd clock system to configure the external memory controller.
-</p>
-
-<h3>Changed startup concept</h3>
-<ul>
- <li>
- SystemInit() is called from startup file before <strong>premain</strong>.
- </li>
- <li>
- <strong>SystemInit()</strong> configures the clock system and also configures
- an existing external memory controller.
- </li>
- <li>
- <strong>SystemInit()</strong> must not use global variables.
- </li>
- <li>
- <strong>SystemCoreClock</strong> is initialized with a correct predefined value.
- </li>
- <li>
- Additional function <strong>void SystemCoreClockUpdate (void)</strong> is provided.<br>
- <strong>SystemCoreClockUpdate()</strong> updates the variable <strong>SystemCoreClock</strong>
- and must be called whenever the core clock is changed.<br>
- <strong>SystemCoreClockUpdate()</strong> evaluates the clock register settings and calculates
- the current core clock.
- </li>
-</ul>
-
-
-<h2>4. Advanced Debug Functions</h2>
-<p>
- ITM communication channel is only capable for OUT direction. To allow also communication for
- IN direction a simple concept is provided.
-</p>
-<ul>
- <li>
- Global variable <strong>volatile int ITM_RxBuffer</strong> used for IN data.
- </li>
- <li>
- Function <strong>int ITM_CheckChar (void)</strong> checks if a new character is available.
- </li>
- <li>
- Function <strong>int ITM_ReceiveChar (void)</strong> retrieves the new character.
- </li>
-</ul>
-
-<p>
- For detailed explanation see file <strong>CMSIS debug support.htm</strong>.
-</p>
-
-
-<h2>5. Core Register Bit Definitions</h2>
-<p>
- Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
- defines correspond with the Cortex-M Technical Reference Manual.
-</p>
-<p>
- e.g. SysTick structure with bit definitions
-</p>
-<pre>
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
- memory mapped structure for SysTick
- @{
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-/*@}*/ /* end of group CMSIS_CM3_SysTick */</pre>
-
-<h2>7. DoxyGen Tags</h2>
-<p>
- DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
- using DoxyGen.
-</p>
-
-<h2>8. Folder Structure</h2>
-<p>
- The folder structure is changed to differentiate the single support packages.
-</p>
-
- <ul>
- <li>CM0</li>
- <li>CM3
- <ul>
- <li>CoreSupport</li>
- <li>DeviceSupport</li>
- <ul>
- <li>Vendor
- <ul>
- <li>Device
- <ul>
- <li>Startup
- <ul>
- <li>Toolchain</li>
- <li>Toolchain</li>
- <li>...</li>
- </ul>
- </li>
- </ul>
- </li>
- <li>Device</li>
- <li>...</li>
- </ul>
- </li>
- <li>Vendor</li>
- <li>...</li>
- </ul>
- </li>
- <li>Example
- <ul>
- <li>Toolchain
- <ul>
- <li>Device</li>
- <li>Device</li>
- <li>...</li>
- </ul>
- </li>
- <li>Toolchain</li>
- <li>...</li>
- </ul>
- </li>
- </ul>
- </li>
-
- <li>Documentation</li>
- </ul>
-
-<h2>9. Open Points</h2>
-<p>
- Following points need to be clarified and solved:
-</p>
-<ul>
- <li>
- <p>
- Equivalent C and Assembler startup files.
- </p>
- <p>
- Is there a need for having C startup files although assembler startup files are
- very efficient and do not need to be changed?
- <p/>
- </li>
- <li>
- <p>
- Placing of HEAP in external RAM.
- </p>
- <p>
- It must be possible to place HEAP in external RAM if the device supports an
- external memory controller.
- </p>
- </li>
- <li>
- <p>
- Placing of STACK /HEAP.
- </p>
- <p>
- STACK should always be placed at the end of internal RAM.
- </p>
- <p>
- If HEAP is placed in internal RAM than it should be placed after RW ZI section.
- </p>
- </li>
- <li>
- <p>
- Removing core_cm3.c and core_cm0.c.
- </p>
- <p>
- On a long term the functions in core_cm3.c and core_cm0.c must be replaced with
- appropriate compiler intrinsics.
- </p>
- </li>
-</ul>
-
-
-<h2>10. Limitations</h2>
-<p>
- The following limitations are not covered with the current CMSIS version:
-</p>
-<ul>
- <li>
- No <strong>C startup files</strong> for ARM toolchain are provided.
- </li>
- <li>
- No <strong>C startup files</strong> for GNU toolchain are provided.
- </li>
- <li>
- No <strong>C startup files</strong> for IAR toolchain are provided.
- </li>
- <li>
- No <strong>Tasking</strong> projects are provided yet.
- </li>
-</ul>
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CMSIS debug support.htm b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CMSIS debug support.htm
deleted file mode 100644
index efda685..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CMSIS debug support.htm
+++ /dev/null
@@ -1,243 +0,0 @@
-<html>
-
-<head>
-<title>CMSIS Debug Support</title>
-<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
-<meta name="GENERATOR" content="Microsoft FrontPage 6.0">
-<meta name="ProgId" content="FrontPage.Editor.Document">
-<style>
-<!--
-/*-----------------------------------------------------------
-Keil Software CHM Style Sheet
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-body { color: #000000; background-color: #FFFFFF; font-size: 75%; font-family:
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- text-align: Center; margin-right: 3 }
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- background-color: #CCCCCC; margin-top: 24; margin-bottom: 3;
- padding: 6 }
-h3 { font-family: Verdana; font-size: 10pt; font-weight: bold; background-color:
- #CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 }
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- margin-left: 24; margin-right: 24 }
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- line-height: 120%; font-style: normal }
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-td.kt { color: #000000; background-color: #E0E0E0; border-top: 1pt solid #A0A0A0;
- padding-left: 6pt; padding-right: 6pt; padding-top: 2pt;
- padding-bottom: 2pt }
-/*-----------------------------------------------------------
------------------------------------------------------------*/
--->
-
-</style>
-</head>
-
-<body>
-
-<h1>CMSIS Debug Support</h1>
-
-<hr>
-
-<h2>Cortex-M3 ITM Debug Access</h2>
-<p>
- The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with
- the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has
- 32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM
- communication channels are used by CMSIS to output the following information:
-</p>
-<ul>
- <li>ITM Channel 0: used for printf-style output via the debug interface.</li>
- <li>ITM Channel 31: is reserved for RTOS kernel awareness debugging.</li>
-</ul>
-
-<h2>Debug IN / OUT functions</h2>
-<p>CMSIS provides following debug functions:</p>
-<ul>
- <li>ITM_SendChar (uses ITM channel 0)</li>
- <li>ITM_ReceiveChar (uses global variable)</li>
- <li>ITM_CheckChar (uses global variable)</li>
-</ul>
-
-<h3>ITM_SendChar</h3>
-<p>
- <strong>ITM_SendChar</strong> is used to transmit a character over ITM channel 0 from
- the microcontroller system to the debug system. <br>
- Only a 8 bit value is transmitted.
-</p>
-<pre>
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- /* check if debugger connected and ITM channel enabled for tracing */
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
- (ITM->TCR & ITM_TCR_ITMENA) &&
- (ITM->TER & (1UL << 0)) )
- {
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t)ch;
- }
- return (ch);
-}</pre>
-
-<h3>ITM_ReceiveChar</h3>
-<p>
- ITM communication channel is only capable for OUT direction. For IN direction
- a globel variable is used. A simple mechansim detects if a character is received.
- The project to test need to be build with debug information.
-</p>
-
-<p>
- The globale variable <strong>ITM_RxBuffer</strong> is used to transmit a 8 bit value from debug system
- to microcontroller system. <strong>ITM_RxBuffer</strong> is 32 bit wide to enshure a proper handshake.
-</p>
-<pre>
-extern volatile int ITM_RxBuffer; /* variable to receive characters */
-</pre>
-<p>
- A dedicated bit pattern is used to determin if <strong>ITM_RxBuffer</strong> is empty
- or contains a valid value.
-</p>
-<pre>
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
-</pre>
-<p>
- <strong>ITM_ReceiveChar</strong> is used to receive a 8 bit value from the debug system. The function is nonblocking.
- It returns the received character or '-1' if no character was available.
-</p>
-<pre>
-static __INLINE int ITM_ReceiveChar (void) {
- int ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-</pre>
-
-<h3>ITM_CheckChar</h3>
-<p>
- <strong>ITM_CheckChar</strong> is used to check if a character is received.
-</p>
-<pre>
-static __INLINE int ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}</pre>
-
-
-<h2>ITM Debug Support in uVision</h2>
-<p>
- uVision uses in a debug session the <strong>Debug (printf) Viewer</strong> window to
- display the debug data.
-</p>
-<p>Direction microcontroller system -> uVision:</p>
-<ul>
- <li>
- Characters received via ITM communication channel 0 are written in a printf style
- to <strong>Debug (printf) Viewer</strong> window.
- </li>
-</ul>
-
-<p>Direction uVision -> microcontroller system:</p>
-<ul>
- <li>Check if <strong>ITM_RxBuffer</strong> variable is available (only performed once).</li>
- <li>Read character from <strong>Debug (printf) Viewer</strong> window.</li>
- <li>If <strong>ITM_RxBuffer</strong> empty write character to <strong>ITM_RxBuffer</strong>.</li>
-</ul>
-
-<p class="Note">Note</p>
-<ul>
- <li><p>Current solution does not use a buffer machanism for trasmitting the characters.</p>
- </li>
-</ul>
-
-<h2>RTX Kernel awareness in uVision</h2>
-<p>
- uVision / RTX are using a simple and efficient solution for RTX Kernel awareness.
- No format overhead is necessary.<br>
- uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access
- to ITM communication channel 31.
-</p>
-
-<p>Following RTX events are traced:</p>
-<ul>
- <li>Task Create / Delete event
- <ol>
- <li>32 bit access. Task start address is transmitted</li>
- <li>16 bit access. Task ID and Create/Delete flag are transmitted<br>
- High byte holds Create/Delete flag, Low byte holds TASK ID.
- </li>
- </ol>
- </li>
- <li>Task switch event
- <ol>
- <li>8 bit access. Task ID of current task is transmitted</li>
- </ol>
- </li>
-</ul>
-
-<p class="Note">Note</p>
-<ul>
- <li><p>Other RTOS information could be retrieved via memory read access in a polling mode manner.</p>
- </li>
-</ul>
-
-
-<p class="MsoNormal"><span lang="EN-GB"> </span></p>
-
-<hr>
-
-<p class="TinyT">Copyright © KEIL - An ARM Company.<br>
-All rights reserved.<br>
-Visit our web site at <a href="http://www.keil.com">www.keil.com</a>.
-</p>
-
-</body>
-
-</html>
\ No newline at end of file
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CMSIS_changes.htm b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CMSIS_changes.htm
deleted file mode 100644
index 162ffcc..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/CMSIS_changes.htm
+++ /dev/null
@@ -1,320 +0,0 @@
-<html>
-
-<head>
-<title>CMSIS Changes</title>
-<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
-<meta name="GENERATOR" content="Microsoft FrontPage 6.0">
-<meta name="ProgId" content="FrontPage.Editor.Document">
-<style>
-<!--
-/*-----------------------------------------------------------
-Keil Software CHM Style Sheet
------------------------------------------------------------*/
-body { color: #000000; background-color: #FFFFFF; font-size: 75%; font-family:
- Verdana, Arial, 'Sans Serif' }
-a:link { color: #0000FF; text-decoration: underline }
-a:visited { color: #0000FF; text-decoration: underline }
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-a:hover { color: #FF0000; text-decoration: underline }
-h1 { font-family: Verdana; font-size: 18pt; color: #000080; font-weight: bold;
- text-align: Center; margin-right: 3 }
-h2 { font-family: Verdana; font-size: 14pt; color: #000080; font-weight: bold;
- background-color: #CCCCCC; margin-top: 24; margin-bottom: 3;
- padding: 6 }
-h3 { font-family: Verdana; font-size: 10pt; font-weight: bold; background-color:
- #CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 }
-pre { font-family: Courier New; font-size: 10pt; background-color: #CCFFCC;
- margin-left: 24; margin-right: 24 }
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-ol { margin-top: 6pt; margin-bottom: 0 }
-li { clear: both; margin-bottom: 6pt }
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-th { color: #FFFFFF; background-color: #000080; text-align: left; vertical-align:
- bottom; padding-right: 6pt }
-tr { text-align: left; vertical-align: top }
-td { text-align: left; vertical-align: top; padding-right: 6pt }
-.ToolT { font-size: 8pt; color: #808080 }
-.TinyT { font-size: 8pt; text-align: Center }
-code { color: #000000; background-color: #E0E0E0; font-family: 'Courier New', Courier;
- line-height: 120%; font-style: normal }
-/*-----------------------------------------------------------
-Notes
------------------------------------------------------------*/
-p.note { font-weight: bold; clear: both; margin-bottom: 3pt; padding-top: 6pt }
-/*-----------------------------------------------------------
-Expanding/Contracting Divisions
------------------------------------------------------------*/
-#expand { text-decoration: none; margin-bottom: 3pt }
-img.expand { border-style: none; border-width: medium }
-div.expand { display: none; margin-left: 9pt; margin-top: 0 }
-/*-----------------------------------------------------------
-Where List Tags
------------------------------------------------------------*/
-p.wh { font-weight: bold; clear: both; margin-top: 6pt; margin-bottom: 3pt }
-table.wh { width: 100% }
-td.whItem { white-space: nowrap; font-style: italic; padding-right: 6pt; padding-bottom:
- 6pt }
-td.whDesc { padding-bottom: 6pt }
-/*-----------------------------------------------------------
-Keil Table Tags
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-table.kt { border: 1pt solid #000000 }
-th.kt { white-space: nowrap; border-bottom: 1pt solid #000000; padding-left: 6pt;
- padding-right: 6pt; padding-top: 4pt; padding-bottom: 4pt }
-tr.kt { }
-td.kt { color: #000000; background-color: #E0E0E0; border-top: 1pt solid #A0A0A0;
- padding-left: 6pt; padding-right: 6pt; padding-top: 2pt;
- padding-bottom: 2pt }
-/*-----------------------------------------------------------
------------------------------------------------------------*/
--->
-
-</style>
-</head>
-
-<body>
-
-<h1>Changes to CMSIS version V1.20</h1>
-
-<hr>
-
-<h2>1. Removed CMSIS Middelware packages</h2>
-<p>
- CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.
-</p>
-
-<h2>2. SystemFrequency renamed to SystemCoreClock</h2>
-<p>
- The variable name <strong>SystemCoreClock</strong> is more precise than <strong>SystemFrequency</strong>
- because the variable holds the clock value at which the core is running.
-</p>
-
-<h2>3. Changed startup concept</h2>
-<p>
- The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit
- from main) has the weakness that it does not work for controllers which need a already
- configuerd clock system to configure the external memory controller.
-</p>
-
-<h3>Changed startup concept</h3>
-<ul>
- <li>
- SystemInit() is called from startup file before <strong>premain</strong>.
- </li>
- <li>
- <strong>SystemInit()</strong> configures the clock system and also configures
- an existing external memory controller.
- </li>
- <li>
- <strong>SystemInit()</strong> must not use global variables.
- </li>
- <li>
- <strong>SystemCoreClock</strong> is initialized with a correct predefined value.
- </li>
- <li>
- Additional function <strong>void SystemCoreClockUpdate (void)</strong> is provided.<br>
- <strong>SystemCoreClockUpdate()</strong> updates the variable <strong>SystemCoreClock</strong>
- and must be called whenever the core clock is changed.<br>
- <strong>SystemCoreClockUpdate()</strong> evaluates the clock register settings and calculates
- the current core clock.
- </li>
-</ul>
-
-
-<h2>4. Advanced Debug Functions</h2>
-<p>
- ITM communication channel is only capable for OUT direction. To allow also communication for
- IN direction a simple concept is provided.
-</p>
-<ul>
- <li>
- Global variable <strong>volatile int ITM_RxBuffer</strong> used for IN data.
- </li>
- <li>
- Function <strong>int ITM_CheckChar (void)</strong> checks if a new character is available.
- </li>
- <li>
- Function <strong>int ITM_ReceiveChar (void)</strong> retrieves the new character.
- </li>
-</ul>
-
-<p>
- For detailed explanation see file <strong>CMSIS debug support.htm</strong>.
-</p>
-
-
-<h2>5. Core Register Bit Definitions</h2>
-<p>
- Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
- defines correspond with the Cortex-M Technical Reference Manual.
-</p>
-<p>
- e.g. SysTick structure with bit definitions
-</p>
-<pre>
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
- memory mapped structure for SysTick
- @{
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-/*@}*/ /* end of group CMSIS_CM3_SysTick */</pre>
-
-<h2>7. DoxyGen Tags</h2>
-<p>
- DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
- using DoxyGen.
-</p>
-
-<h2>8. Folder Structure</h2>
-<p>
- The folder structure is changed to differentiate the single support packages.
-</p>
-
- <ul>
- <li>CM0</li>
- <li>CM3
- <ul>
- <li>CoreSupport</li>
- <li>DeviceSupport</li>
- <ul>
- <li>Vendor
- <ul>
- <li>Device
- <ul>
- <li>Startup
- <ul>
- <li>Toolchain</li>
- <li>Toolchain</li>
- <li>...</li>
- </ul>
- </li>
- </ul>
- </li>
- <li>Device</li>
- <li>...</li>
- </ul>
- </li>
- <li>Vendor</li>
- <li>...</li>
- </ul>
- </li>
- <li>Example
- <ul>
- <li>Toolchain
- <ul>
- <li>Device</li>
- <li>Device</li>
- <li>...</li>
- </ul>
- </li>
- <li>Toolchain</li>
- <li>...</li>
- </ul>
- </li>
- </ul>
- </li>
-
- <li>Documentation</li>
- </ul>
-
-<h2>9. Open Points</h2>
-<p>
- Following points need to be clarified and solved:
-</p>
-<ul>
- <li>
- <p>
- Equivalent C and Assembler startup files.
- </p>
- <p>
- Is there a need for having C startup files although assembler startup files are
- very efficient and do not need to be changed?
- <p/>
- </li>
- <li>
- <p>
- Placing of HEAP in external RAM.
- </p>
- <p>
- It must be possible to place HEAP in external RAM if the device supports an
- external memory controller.
- </p>
- </li>
- <li>
- <p>
- Placing of STACK /HEAP.
- </p>
- <p>
- STACK should always be placed at the end of internal RAM.
- </p>
- <p>
- If HEAP is placed in internal RAM than it should be placed after RW ZI section.
- </p>
- </li>
- <li>
- <p>
- Removing core_cm3.c and core_cm0.c.
- </p>
- <p>
- On a long term the functions in core_cm3.c and core_cm0.c must be replaced with
- appropriate compiler intrinsics.
- </p>
- </li>
-</ul>
-
-
-<h2>10. Limitations</h2>
-<p>
- The following limitations are not covered with the current CMSIS version:
-</p>
-<ul>
- <li>
- No <strong>C startup files</strong> for ARM toolchain are provided.
- </li>
- <li>
- No <strong>C startup files</strong> for GNU toolchain are provided.
- </li>
- <li>
- No <strong>C startup files</strong> for IAR toolchain are provided.
- </li>
- <li>
- No <strong>Tasking</strong> projects are provided yet.
- </li>
-</ul>
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/Documentation/CMSIS_Core.htm b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/Documentation/CMSIS_Core.htm
deleted file mode 100644
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--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/Documentation/CMSIS_Core.htm
+++ /dev/null
@@ -1,1337 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html xmlns:p="urn:schemas-microsoft-com:office:powerpoint" xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office"><head>
-
- <title>CMSIS: Cortex Microcontroller Software Interface Standard</title><meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
- <meta name="ProgId" content="FrontPage.Editor.Document">
- <style>
-<!--
-/*-----------------------------------------------------------Keil Software CHM Style Sheet
------------------------------------------------------------*/
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- </style></head>
-<body>
-<h1>Cortex Microcontroller Software Interface Standard</h1>
-
-<p align="center">This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).</p>
-<p align="center">Version: 1.30 - 30. October 2009</p>
-
-<p class="TinyT">Information in this file, the accompany manuals, and software is<br>
- Copyright © ARM Ltd.<br>All rights reserved.
-</p>
-
-<hr>
-
-<p><span style="FONT-WEIGHT: bold">Revision History</span></p>
-<ul>
- <li>Version 1.00: initial release. </li>
- <li>Version 1.01: added __LDREX<em>x</em>, __STREX<em>x</em>, and __CLREX.</li>
- <li>Version 1.02: added Cortex-M0. </li>
- <li>Version 1.10: second review. </li>
- <li>Version 1.20: third review. </li>
- <li>Version 1.30 PRE-RELEASE: reworked Startup Concept, additional Debug Functionality.</li>
- <li>Version 1.30 2nd PRE-RELEASE: changed folder structure, added doxyGen comments, added Bit definitions.</li>
- <li>Version 1.30: updated Device Support Packages.</li>
-</ul>
-
-<hr>
-
-<h2>Contents</h2>
-
-<ol>
- <li class="LI2"><a href="#1">About</a></li>
- <li class="LI2"><a href="#2">Coding Rules and Conventions</a></li>
- <li class="LI2"><a href="#3">CMSIS Files</a></li>
- <li class="LI2"><a href="#4">Core Peripheral Access Layer</a></li>
- <li class="LI2"><a href="#5">CMSIS Example</a></li>
-</ol>
-
-<h2><a name="1"></a>About</h2>
-
-<p>
- The <strong>Cortex Microcontroller Software Interface Standard (CMSIS)</strong> answers the challenges
- that are faced when software components are deployed to physical microcontroller devices based on a
- Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M
- processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation
- with various silicon and software vendors and provides a common approach to interface to peripherals,
- real-time operating systems, and middleware components.
-</p>
-
-<p>ARM provides as part of the CMSIS the following software layers that are
-available for various compiler implementations:</p>
-<ul>
- <li><strong>Core Peripheral Access Layer</strong>: contains name definitions,
- address definitions and helper functions to
- access core registers and peripherals. It defines also a device
- independent interface for RTOS Kernels that includes debug channel
- definitions.</li>
-</ul>
-
-<p>These software layers are expanded by Silicon partners with:</p>
-<ul>
- <li><strong>Device Peripheral Access Layer</strong>: provides definitions
- for all device peripherals</li>
- <li><strong>Access Functions for Peripherals (optional)</strong>: provides
- additional helper functions for peripherals</li>
-</ul>
-
-<p>CMSIS defines for a Cortex-M Microcontroller System:</p>
-<ul>
- <li style="text-align: left;">A common way to access peripheral registers
- and a common way to define exception vectors.</li>
- <li style="text-align: left;">The register names of the <strong>Core
- Peripherals</strong> and<strong> </strong>the names of the <strong>Core
- Exception Vectors</strong>.</li>
- <li>An device independent interface for RTOS Kernels including a debug
- channel.</li>
-</ul>
-
-<p>
- By using CMSIS compliant software components, the user can easier re-use template code.
- CMSIS is intended to enable the combination of software components from multiple middleware vendors.
-</p>
-
-<h2><a name="2"></a>Coding Rules and Conventions</h2>
-
-<p>
- The following section describes the coding rules and conventions used in the CMSIS
- implementation. It contains also information about data types and version number information.
-</p>
-
-<h3>Essentials</h3>
-<ul>
- <li>The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations,
- there are disable and enable sequences for PC-LINT inserted.</li>
- <li>ANSI standard data types defined in the ANSI C header file
- <strong><stdint.h></strong> are used.</li>
- <li>#define constants that include expressions must be enclosed by
- parenthesis.</li>
- <li>Variables and parameters have a complete data type.</li>
- <li>All functions in the <strong>Core Peripheral Access Layer</strong> are
- re-entrant.</li>
- <li>The <strong>Core Peripheral Access Layer</strong> has no blocking code
- (which means that wait/query loops are done at other software layers).</li>
- <li>For each exception/interrupt there is definition for:
- <ul>
- <li>an exception/interrupt handler with the postfix <strong>_Handler </strong>
- (for exceptions) or <strong>_IRQHandler</strong> (for interrupts).</li>
- <li>a default exception/interrupt handler (weak definition) that contains an endless loop.</li>
- <li>a #define of the interrupt number with the postfix <strong>_IRQn</strong>.</li>
- </ul></li>
-</ul>
-
-<h3>Recommendations</h3>
-
-<p>The CMSIS recommends the following conventions for identifiers.</p>
-<ul>
- <li><strong>CAPITAL</strong> names to identify Core Registers, Peripheral Registers, and CPU Instructions.</li>
- <li><strong>CamelCase</strong> names to identify peripherals access functions and interrupts.</li>
- <li><strong>PERIPHERAL_</strong> prefix to identify functions that belong to specify peripherals.</li>
- <li><strong>Doxygen</strong> comments for all functions are included as described under <strong>Function Comments</strong> below.</li>
-</ul>
-
-<b>Comments</b>
-
-<ul>
- <li>Comments use the ANSI C90 style (<em>/* comment */</em>) or C++ style
- (<em>// comment</em>). It is assumed that the programming tools support today
- consistently the C++ comment style.</li>
- <li><strong>Function Comments</strong> provide for each function the following information:
- <ul>
- <li>one-line brief function overview.</li>
- <li>detailed parameter explanation.</li>
- <li>detailed information about return values.</li>
- <li>detailed description of the actual function.</li>
- </ul>
- <p><b>Doxygen Example:</b></p>
- <pre>
-/**
- * @brief Enable Interrupt in NVIC Interrupt Controller
- * @param IRQn interrupt number that specifies the interrupt
- * @return none.
- * Enable the specified interrupt in the NVIC Interrupt Controller.
- * Other settings of the interrupt such as priority are not affected.
- */</pre>
- </li>
-</ul>
-
-<h3>Data Types and IO Type Qualifiers</h3>
-
-<p>
- The <strong>Cortex-M HAL</strong> uses the standard types from the standard ANSI C header file
- <strong><stdint.h></strong>. <strong>IO Type Qualifiers</strong> are used to specify the access
- to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of
- debug information of peripheral registers.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">IO Type Qualifier</th>
- <th class="kt">#define</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">__I</td>
- <td class="kt">volatile const</td>
- <td class="kt">Read access only</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">__O</td>
- <td class="kt">volatile</td>
- <td class="kt">Write access only</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">__IO</td>
- <td class="kt">volatile</td>
- <td class="kt">Read and write access</td>
- </tr>
- </tbody>
-</table>
-
-<h3>CMSIS Version Number</h3>
-<p>
- File <strong>core_cm3.h</strong> contains the version number of the CMSIS with the following define:
-</p>
-
-<pre>
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /* [31:16] main version */
-#define __CM3_CMSIS_VERSION_SUB (0x30) /* [15:0] sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)</pre>
-
-<p>
- File <strong>core_cm0.h</strong> contains the version number of the CMSIS with the following define:
-</p>
-
-<pre>
-#define __CM0_CMSIS_VERSION_MAIN (0x01) /* [31:16] main version */
-#define __CM0_CMSIS_VERSION_SUB (0x30) /* [15:0] sub version */
-#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)</pre>
-
-
-<h3>CMSIS Cortex Core</h3>
-<p>
- File <strong>core_cm3.h</strong> contains the type of the CMSIS Cortex-M with the following define:
-</p>
-
-<pre>
-#define __CORTEX_M (0x03)</pre>
-
-<p>
- File <strong>core_cm0.h</strong> contains the type of the CMSIS Cortex-M with the following define:
-</p>
-
-<pre>
-#define __CORTEX_M (0x00)</pre>
-
-
-<h2><a name="3"></a>CMSIS Files</h2>
-<p>
- This section describes the Files provided in context with the CMSIS to access the Cortex-M
- hardware and peripherals.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">File</th>
- <th class="kt">Provider</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap"><i>device.h</i></td>
- <td class="kt">Device specific (provided by silicon partner)</td>
- <td class="kt">Defines the peripherals for the actual device. The file may use
- several other include files to define the peripherals of the actual device.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">core_cm0.h</td>
- <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
- <td class="kt">Defines the core peripherals for the Cortex-M0 CPU and core peripherals.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">core_cm3.h</td>
- <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
- <td class="kt">Defines the core peripherals for the Cortex-M3 CPU and core peripherals.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">core_cm0.c</td>
- <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
- <td class="kt">Provides helper functions that access core registers.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">core_cm3.c</td>
- <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
- <td class="kt">Provides helper functions that access core registers.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">startup<i>_device</i></td>
- <td class="kt">ARM (adapted by compiler partner / silicon partner)</td>
- <td class="kt">Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">system<i>_device</i></td>
- <td class="kt">ARM (adapted by silicon partner)</td>
- <td class="kt">Provides a device specific configuration file for the device. It configures the device initializes
- typically the oscillator (PLL) that is part of the microcontroller device</td>
- </tr>
- </tbody>
-</table>
-
-<h3><em>device.h</em></h3>
-
-<p>
- The file <em><strong>device.h</strong></em> is provided by the silicon vendor and is the
- <u><strong>central include file</strong></u> that the application programmer is using in
- the C source code. This file contains:
-</p>
-<ul>
- <li>
- <p><strong>Interrupt Number Definition</strong>: provides interrupt numbers
- (IRQn) for all core and device specific exceptions and interrupts.</p>
- </li>
- <li>
- <p><strong>Configuration for core_cm0.h / core_cm3.h</strong>: reflects the
- actual configuration of the Cortex-M processor that is part of the actual
- device. As such the file <strong>core_cm0.h / core_cm3.h</strong> is included that
- implements access to processor registers and core peripherals. </p>
- </li>
- <li>
- <p><strong>Device Peripheral Access Layer</strong>: provides definitions
- for all device peripherals. It contains all data structures and the address
- mapping for the device specific peripherals. </p>
- </li>
- <li><strong>Access Functions for Peripherals (optional)</strong>: provides
- additional helper functions for peripherals that are useful for programming
- of these peripherals. Access Functions may be provided as inline functions
- or can be extern references to a device specific library provided by the
- silicon vendor.</li>
-</ul>
-
-
-<h4><strong>Interrupt Number Definition</strong></h4>
-
-<p>To access the device specific interrupts the device.h file defines IRQn
-numbers for the complete device using a enum typedef as shown below:</p>
-<pre>
-typedef enum IRQn
-{
-/****** Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
-/****** STM32 specific Interrupt Numbers ****************************************************************/
- WWDG_STM_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_STM_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
- :
- :
- } IRQn_Type;</pre>
-
-
-<h4>Configuration for core_cm0.h / core_cm3.h</h4>
-<p>
- The Cortex-M core configuration options which are defined for each device implementation. Some
- configuration options are reflected in the CMSIS layer using the #define settings described below.
-</p>
-<p>
- To access core peripherals file <em><strong>device.h</strong></em> includes file <b>core_cm0.h / core_cm3.h</b>.
- Several features in <strong>core_cm0.h / core_cm3.h</strong> are configured by the following defines that must be
- defined before <strong>#include <core_cm0.h></strong> / <strong>#include <core_cm3.h></strong>
- preprocessor command.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">#define</th>
- <th class="kt" nowrap="nowrap">File</th>
- <th class="kt" nowrap="nowrap">Value</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td>
- <td class="kt">core_cm0.h</td>
- <td class="kt" nowrap="nowrap">(2)</td>
- <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td>
- <td class="kt">core_cm3.h</td>
- <td class="kt" nowrap="nowrap">(2 ... 8)</td>
- <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">__MPU_PRESENT</td>
- <td class="kt">core_cm0.h, core_cm3.h</td>
- <td class="kt" nowrap="nowrap">(0, 1)</td>
- <td class="kt">Defines if an MPU is present or not</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">__Vendor_SysTickConfig</td>
- <td class="kt">core_cm0.h, core_cm3.h</td>
- <td class="kt" nowrap="nowrap">(1)</td>
- <td class="kt">When this define is setup to 1, the <strong>SysTickConfig</strong> function
- in <strong>core_cm3.h</strong> is excluded. In this case the <em><strong>device.h</strong></em>
- file must contain a vendor specific implementation of this function.</td>
- </tr>
- </tbody>
-</table>
-
-
-<h4>Device Peripheral Access Layer</h4>
-<p>
- Each peripheral uses a prefix which consists of <strong><device abbreviation>_</strong>
- and <strong><peripheral name>_</strong> to identify peripheral registers that access this
- specific peripheral. The intention of this is to avoid name collisions caused
- due to short names. If more than one peripheral of the same type exists,
- identifiers have a postfix (digit or letter). For example:
-</p>
-<ul>
- <li><device abbreviation>_UART_Type: defines the generic register layout for all UART channels in a device.
- <pre>
-typedef struct
-{
- union {
- __I uint8_t RBR; /*!< Offset: 0x000 Receiver Buffer Register */
- __O uint8_t THR; /*!< Offset: 0x000 Transmit Holding Register */
- __IO uint8_t DLL; /*!< Offset: 0x000 Divisor Latch LSB */
- uint32_t RESERVED0;
- };
- union {
- __IO uint8_t DLM; /*!< Offset: 0x004 Divisor Latch MSB */
- __IO uint32_t IER; /*!< Offset: 0x004 Interrupt Enable Register */
- };
- union {
- __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register */
- __O uint8_t FCR; /*!< Offset: 0x008 FIFO Control Register */
- };
- __IO uint8_t LCR; /*!< Offset: 0x00C Line Control Register */
- uint8_t RESERVED1[7];
- __I uint8_t LSR; /*!< Offset: 0x014 Line Status Register */
- uint8_t RESERVED2[7];
- __IO uint8_t SCR; /*!< Offset: 0x01C Scratch Pad Register */
- uint8_t RESERVED3[3];
- __IO uint32_t ACR; /*!< Offset: 0x020 Autobaud Control Register */
- __IO uint8_t ICR; /*!< Offset: 0x024 IrDA Control Register */
- uint8_t RESERVED4[3];
- __IO uint8_t FDR; /*!< Offset: 0x028 Fractional Divider Register */
- uint8_t RESERVED5[7];
- __IO uint8_t TER; /*!< Offset: 0x030 Transmit Enable Register */
- uint8_t RESERVED6[39];
- __I uint8_t FIFOLVL; /*!< Offset: 0x058 FIFO Level Register */
-} LPC_UART_TypeDef;</pre>
- </li>
- <li><device abbreviation>_UART1: is a pointer to a register structure that refers to a specific UART.
- For example UART1->DR is the data register of UART1.
- <pre>
-#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
-#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )</pre>
- </li>
-</ul>
-
-<h5>Minimal Requiements</h5>
-<p>
- To access the peripheral registers and related function in a device the files <strong><em>device.h</em></strong>
- and <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong> defines as a minimum:
-</p>
-<ul>
- <li>The <strong>Register Layout Typedef</strong> for each peripheral that defines all register names.
- Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of
- the peripheral registers. For example:
- <pre>
-typedef struct {
- __IO uint32_t CTRL; /* SysTick Control and Status Register */
- __IO uint32_t LOAD; /* SysTick Reload Value Register */
- __IO uint32_t VAL; /* SysTick Current Value Register */
- __I uint32_t CALIB; /* SysTick Calibration Register */
- } SysTick_Type;</pre>
- </li>
-
- <li>
- <strong>Base Address</strong> for each peripheral (in case of multiple peripherals
- that use the same <strong>register layout typedef</strong> multiple base addresses are defined). For example:
- <pre>
-#define SysTick_BASE (SCS_BASE + 0x0010) /* SysTick Base Address */</pre>
- </li>
-
- <li>
- <strong>Access Definition</strong> for each peripheral (in case of multiple peripherals that use
- the same <strong>register layout typedef</strong> multiple access definitions exist, i.e. LPC_UART0,
- LPC_UART2). For Example:
- <pre>
-#define SysTick ((SysTick_Type *) SysTick_BASE) /* SysTick access definition */</pre>
- </li>
-</ul>
-
-<p>
- These definitions allow to access the peripheral registers from user code with simple assignments like:
-</p>
-<pre>SysTick->CTRL = 0;</pre>
-
-<h5>Optional Features</h5>
-<p>In addition the <em> <strong>device.h </strong></em>file may define:</p>
-<ul>
- <li>
- #define constants that simplify access to the peripheral registers.
- These constant define bit-positions or other specific patterns are that required for the
- programming of the peripheral registers. The identifiers used start with
- <strong><device abbreviation>_</strong> and <strong><peripheral name>_</strong>.
- It is recommended to use CAPITAL letters for such #define constants.
- </li>
- <li>
- Functions that perform more complex functions with the peripheral (i.e. status query before
- a sending register is accessed). Again these function start with
- <strong><device abbreviation>_</strong> and <strong><peripheral name>_</strong>.
- </li>
-</ul>
-
-<h3>core_cm0.h and core_cm0.c</h3>
-<p>
- File <b>core_cm0.h</b> describes the data structures for the Cortex-M0 core peripherals and does
- the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers
- and core peripherals with efficient functions (defined as <strong>static inline</strong>).
-</p>
-<p>
- File <b>core_cm0.c</b> defines several helper functions that access processor registers.
-</p>
-<p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M0.</p>
-
-<h3>core_cm3.h and core_cm3.c</h3>
-<p>
- File <b>core_cm3.h</b> describes the data structures for the Cortex-M3 core peripherals and does
- the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers
- and core peripherals with efficient functions (defined as <strong>static inline</strong>).
-</p>
-<p>
- File <b>core_cm3.c</b> defines several helper functions that access processor registers.
-</p>
-<p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M3.</p>
-
-<h3>startup_<em>device</em></h3>
-<p>
- A template file for <strong>startup_<em>device</em></strong> is provided by ARM for each supported
- compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific
- interrupt handlers. Each interrupt handler is defined as <strong><em>weak</em></strong> function
- to an dummy handler. Therefore the interrupt handler can be directly used in application software
- without any requirements to adapt the <strong>startup_<em>device</em></strong> file.
-</p>
-<p>
- The following exception names are fixed and define the start of the vector table for a Cortex-M0:
-</p>
-<pre>
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler</pre>
-
-<p>
- The following exception names are fixed and define the start of the vector table for a Cortex-M3:
-</p>
-<pre>
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler</pre>
-
-<p>
- In the following examples for device specific interrupts are shown:
-</p>
-<pre>
-; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper</pre>
-
-<p>
- Device specific interrupts must have a dummy function that can be overwritten in user code.
- Below is an example for this dummy function.
-</p>
-<pre>
-Default_Handler PROC
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMPER_IRQHandler [WEAK]
- :
- :
- WWDG_IRQHandler
- PVD_IRQHandler
- TAMPER_IRQHandler
- :
- :
- B .
- ENDP</pre>
-
-<p>
- The user application may simply define an interrupt handler function by using the handler name
- as shown below.
-</p>
-<pre>
-void WWDG_IRQHandler(void)
-{
- :
- :
-}</pre>
-
-
-<h3><a name="4"></a>system_<em>device</em>.c</h3>
-<p>
- A template file for <strong>system_<em>device</em>.c</strong> is provided by ARM but adapted by
- the silicon vendor to match their actual device. As a <strong>minimum requirement</strong>
- this file must provide a device specific system configuration function and a global variable
- that contains the system frequency. It configures the device and initializes typically the
- oscillator (PLL) that is part of the microcontroller device.
-</p>
-<p>
- The file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong> must provide
- as a minimum requirement the SystemInit function as shown below.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt">Function Definition</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void SystemInit (void)</td>
- <td class="kt">Setup the microcontroller system. Typically this function configures the
- oscillator (PLL) that is part of the microcontroller device. For systems
- with variable clock speed it also updates the variable SystemCoreClock.<br>
- SystemInit is called from startup<i>_device</i> file.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void SystemCoreClockUpdate (void)</td>
- <td class="kt">Updates the variable SystemCoreClock and must be called whenever the
- core clock is changed during program execution. SystemCoreClockUpdate()
- evaluates the clock register settings and calculates the current core clock.
-</td>
- </tr>
- </tbody>
-</table>
-
-<p>
- Also part of the file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong>
- is the variable <strong>SystemCoreClock</strong> which contains the current CPU clock speed shown below.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt">Variable Definition</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t SystemCoreClock</td>
- <td class="kt">Contains the system core clock (which is the system clock frequency supplied
- to the SysTick timer and the processor core clock). This variable can be
- used by the user application to setup the SysTick timer or configure other
- parameters. It may also be used by debugger to query the frequency of the
- debug timer or configure the trace clock speed.<br>
- SystemCoreClock is initialized with a correct predefined value.<br><br>
- The compiler must be configured to avoid the removal of this variable in
- case that the application program is not using it. It is important for
- debug systems that the variable is physically present in memory so that
- it can be examined to configure the debugger.</td>
- </tr>
- </tbody>
-</table>
-
-<p class="Note">Note</p>
-<ul>
- <li><p>The above definitions are the minimum requirements for the file <strong>
- system_</strong><em><strong>device</strong></em><strong>.c</strong>. This
- file may export more functions or variables that provide a more flexible
- configuration of the microcontroller system.</p>
- </li>
-</ul>
-
-
-<h2>Core Peripheral Access Layer</h2>
-
-<h3>Cortex-M Core Register Access</h3>
-<p>
- The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>
- and provide access to Cortex-M core registers.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt">Function Definition</th>
- <th class="kt">Core</th>
- <th class="kt">Core Register</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __enable_irq (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">PRIMASK = 0</td>
- <td class="kt">Global Interrupt enable (using the instruction <strong>CPSIE
- i</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __disable_irq (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">PRIMASK = 1</td>
- <td class="kt">Global Interrupt disable (using the instruction <strong>
- CPSID i</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __set_PRIMASK (uint32_t value)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">PRIMASK = value</td>
- <td class="kt">Assign value to Priority Mask Register (using the instruction
- <strong>MSR</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __get_PRIMASK (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">return PRIMASK</td>
- <td class="kt">Return Priority Mask Register (using the instruction
- <strong>MRS</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __enable_fault_irq (void)</td>
- <td class="kt">M3</td>
- <td class="kt">FAULTMASK = 0</td>
- <td class="kt">Global Fault exception and Interrupt enable (using the
- instruction <strong>CPSIE
- f</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __disable_fault_irq (void)</td>
- <td class="kt">M3</td>
- <td class="kt">FAULTMASK = 1</td>
- <td class="kt">Global Fault exception and Interrupt disable (using the
- instruction <strong>CPSID f</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __set_FAULTMASK (uint32_t value)</td>
- <td class="kt">M3</td>
- <td class="kt">FAULTMASK = value</td>
- <td class="kt">Assign value to Fault Mask Register (using the instruction
- <strong>MSR</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __get_FAULTMASK (void)</td>
- <td class="kt">M3</td>
- <td class="kt">return FAULTMASK</td>
- <td class="kt">Return Fault Mask Register (using the instruction <strong>MRS</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __set_BASEPRI (uint32_t value)</td>
- <td class="kt">M3</td>
- <td class="kt">BASEPRI = value</td>
- <td class="kt">Set Base Priority (using the instruction <strong>MSR</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uiuint32_t __get_BASEPRI (void)</td>
- <td class="kt">M3</td>
- <td class="kt">return BASEPRI</td>
- <td class="kt">Return Base Priority (using the instruction <strong>MRS</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __set_CONTROL (uint32_t value)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">CONTROL = value</td>
- <td class="kt">Set CONTROL register value (using the instruction <strong>MSR</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __get_CONTROL (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">return CONTROL</td>
- <td class="kt">Return Control Register Value (using the instruction
- <strong>MRS</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __set_PSP (uint32_t TopOfProcStack)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">PSP = TopOfProcStack</td>
- <td class="kt">Set Process Stack Pointer value (using the instruction
- <strong>MSR</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __get_PSP (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">return PSP</td>
- <td class="kt">Return Process Stack Pointer (using the instruction <strong>MRS</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __set_MSP (uint32_t TopOfMainStack)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">MSP = TopOfMainStack</td>
- <td class="kt">Set Main Stack Pointer (using the instruction <strong>MSR</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __get_MSP (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">return MSP</td>
- <td class="kt">Return Main Stack Pointer (using the instruction <strong>MRS</strong>)</td>
- </tr>
- </tbody>
-</table>
-
-<h3>Cortex-M Instruction Access</h3>
-<p>
- The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>and
- generate specific Cortex-M instructions. The functions are implemented in the file
- <strong>core_cm0.c</strong> / <strong>core_cm3.c</strong>.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt">Name</th>
- <th class="kt">Core</th>
- <th class="kt">Generated CPU Instruction</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __NOP (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">NOP</td>
- <td class="kt">No Operation</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __WFI (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">WFI</td>
- <td class="kt">Wait for Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __WFE (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">WFE</td>
- <td class="kt">Wait for Event</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __SEV (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">SEV</td>
- <td class="kt">Set Event</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __ISB (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">ISB</td>
- <td class="kt">Instruction Synchronization Barrier</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __DSB (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">DSB</td>
- <td class="kt">Data Synchronization Barrier</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __DMB (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">DMB</td>
- <td class="kt">Data Memory Barrier</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __REV (uint32_t value)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">REV</td>
- <td class="kt">Reverse byte order in integer value.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __REV16 (uint16_t value)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">REV16</td>
- <td class="kt">Reverse byte order in unsigned short value. </td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">sint32_t __REVSH (sint16_t value)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">REVSH</td>
- <td class="kt">Reverse byte order in signed short value with sign extension to integer.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __RBIT (uint32_t value)</td>
- <td class="kt">M3</td>
- <td class="kt">RBIT</td>
- <td class="kt">Reverse bit order of value</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint8_t __LDREXB (uint8_t *addr)</td>
- <td class="kt">M3</td>
- <td class="kt">LDREXB</td>
- <td class="kt">Load exclusive byte</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint16_t __LDREXH (uint16_t *addr)</td>
- <td class="kt">M3</td>
- <td class="kt">LDREXH</td>
- <td class="kt">Load exclusive half-word</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __LDREXW (uint32_t *addr)</td>
- <td class="kt">M3</td>
- <td class="kt">LDREXW</td>
- <td class="kt">Load exclusive word</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint8_t value, uint8_t *addr)</td>
- <td class="kt">M3</td>
- <td class="kt">STREXB</td>
- <td class="kt">Store exclusive byte</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint16_t value, uint16_t *addr)</td>
- <td class="kt">M3</td>
- <td class="kt">STREXH</td>
- <td class="kt">Store exclusive half-word</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint32_t value, uint32_t *addr)</td>
- <td class="kt">M3</td>
- <td class="kt">STREXW</td>
- <td class="kt">Store exclusive word</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __CLREX (void)</td>
- <td class="kt">M3</td>
- <td class="kt">CLREX</td>
- <td class="kt">Remove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW</td>
- </tr>
- </tbody>
-</table>
-
-
-<h3>NVIC Access Functions</h3>
-<p>
- The CMSIS provides access to the NVIC via the register interface structure and several helper
- functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to
- identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative
- IRQn values are used for processor core exceptions.
-</p>
-<p>
- For the IRQn values of core exceptions the file <strong><em>device.h</em></strong> provides
- the following enum names.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">Core Exception enum Value</th>
- <th class="kt">Core</th>
- <th class="kt">IRQn</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">NonMaskableInt_IRQn</td>
- <td class="kt">M0, M3</td>
- <td class="kt">-14</td>
- <td class="kt">Cortex-M Non Maskable Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">HardFault_IRQn</td>
- <td class="kt">M0, M3</td>
- <td class="kt">-13</td>
- <td class="kt">Cortex-M Hard Fault Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">MemoryManagement_IRQn</td>
- <td class="kt">M3</td>
- <td class="kt">-12</td>
- <td class="kt">Cortex-M Memory Management Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">BusFault_IRQn</td>
- <td class="kt">M3</td>
- <td class="kt">-11</td>
- <td class="kt">Cortex-M Bus Fault Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">UsageFault_IRQn</td>
- <td class="kt">M3</td>
- <td class="kt">-10</td>
- <td class="kt">Cortex-M Usage Fault Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">SVCall_IRQn</td>
- <td class="kt">M0, M3</td>
- <td class="kt">-5</td>
- <td class="kt">Cortex-M SV Call Interrupt </td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">DebugMonitor_IRQn</td>
- <td class="kt">M3</td>
- <td class="kt">-4</td>
- <td class="kt">Cortex-M Debug Monitor Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">PendSV_IRQn</td>
- <td class="kt">M0, M3</td>
- <td class="kt">-2</td>
- <td class="kt">Cortex-M Pend SV Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">SysTick_IRQn</td>
- <td class="kt">M0, M3</td>
- <td class="kt">-1</td>
- <td class="kt">Cortex-M System Tick Interrupt</td>
- </tr>
- </tbody>
-</table>
-
-<p>The following functions simplify the setup of the NVIC.
-The functions are defined as <strong>static inline</strong>.</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">Name</th>
- <th class="kt">Core</th>
- <th class="kt">Parameter</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)</td>
- <td class="kt">M3</td>
- <td class="kt">Priority Grouping Value</td>
- <td class="kt">Set the Priority Grouping (Groups . Subgroups)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriorityGrouping (void)</td>
- <td class="kt">M3</td>
- <td class="kt">(void)</td>
- <td class="kt">Get the Priority Grouping (Groups . Subgroups)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void NVIC_EnableIRQ (IRQn_Type IRQn)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">IRQ Number</td>
- <td class="kt">Enable IRQn</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void NVIC_DisableIRQ (IRQn_Type IRQn)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">IRQ Number</td>
- <td class="kt">Disable IRQn</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">IRQ Number</td>
- <td class="kt">Return 1 if IRQn is pending else 0</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void NVIC_SetPendingIRQ (IRQn_Type IRQn)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">IRQ Number</td>
- <td class="kt">Set IRQn Pending</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void NVIC_ClearPendingIRQ (IRQn_Type IRQn)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">IRQ Number</td>
- <td class="kt">Clear IRQn Pending Status</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t NVIC_GetActive (IRQn_Type IRQn)</td>
- <td class="kt">M3</td>
- <td class="kt">IRQ Number</td>
- <td class="kt">Return 1 if IRQn is active else 0</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">IRQ Number, Priority</td>
- <td class="kt">Set Priority for IRQn<br>
- (not threadsafe for Cortex-M0)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriority (IRQn_Type IRQn)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">IRQ Number</td>
- <td class="kt">Get Priority for IRQn</td>
- </tr>
- <tr>
-<!-- <td class="kt" nowrap="nowrap">uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td> -->
- <td class="kt">uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td>
- <td class="kt">M3</td>
- <td class="kt">IRQ Number, Priority Group, Preemptive Priority, Sub Priority</td>
- <td class="kt">Encode priority for given group, preemptive and sub priority</td>
- </tr>
-<!-- <td class="kt" nowrap="nowrap">NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)</td> -->
- <td class="kt">NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)</td>
- <td class="kt">M3</td>
- <td class="kt">IRQ Number, Priority, pointer to Priority Group, pointer to Preemptive Priority, pointer to Sub Priority</td>
- <td class="kt">Deccode given priority to group, preemptive and sub priority</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void NVIC_SystemReset (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">(void)</td>
- <td class="kt">Resets the System</td>
- </tr>
- </tbody>
-</table>
-<p class="Note">Note</p>
-<ul>
- <li><p>The processor exceptions have negative enum values. Device specific interrupts
- have positive enum values and start with 0. The values are defined in
- <b><em>device.h</em></b> file.
- </p>
- </li>
- <li><p>The values for <b>PreemptPriority</b> and <b>SubPriority</b>
- used in functions <b>NVIC_EncodePriority</b> and <b>NVIC_DecodePriority</b>
- depend on the available __NVIC_PRIO_BITS implemented in the NVIC.
- </p>
- </li>
-</ul>
-
-
-<h3>SysTick Configuration Function</h3>
-
-<p>The following function is used to configure the SysTick timer and start the
-SysTick interrupt.</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">Name</th>
- <th class="kt">Parameter</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t Sys<span class="style1">TickConfig
- (uint32_t ticks)</span></td>
- <td class="kt">ticks is SysTick counter reload value</td>
- <td class="kt">Setup the SysTick timer and enable the SysTick interrupt. After this
- call the SysTick timer creates interrupts with the specified time
- interval. <br>
- <br>
- Return: 0 when successful, 1 on failure.<br>
- </td>
- </tr>
- </tbody>
-</table>
-
-
-<h3>Cortex-M3 ITM Debug Access</h3>
-
-<p>The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that
-provides together with the Serial Viewer Output trace capabilities for the
-microcontroller system. The ITM has 32 communication channels; two ITM
-communication channels are used by CMSIS to output the following information:</p>
-<ul>
- <li>ITM Channel 0: implements the <strong>ITM_SendChar</strong> function
- which can be used for printf-style output via the debug interface.</li>
- <li>ITM Channel 31: is reserved for the RTOS kernel and can be used for
- kernel awareness debugging.</li>
-</ul>
-<p class="Note">Note</p>
-<ul>
- <li><p>The ITM channel 31 is selected for the RTOS kernel since some kernels
- may use the Privileged level for program execution. ITM
- channels have 4 groups with 8 channels each, whereby each group can be
- configured for access rights in the Unprivileged level. The ITM channel 0
- may be therefore enabled for the user task whereas ITM channel 31 may be
- accessible only in Privileged level from the RTOS kernel itself.</p>
- </li>
-</ul>
-
-<p>The prototype of the <strong>ITM_SendChar</strong> routine is shown in the
-table below.</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">Name</th>
- <th class="kt">Parameter</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void uint32_t ITM_SendChar(uint32_t chr)</td>
- <td class="kt">character to output</td>
- <td class="kt">The function outputs a character via the ITM channel 0. The
- function returns when no debugger is connected that has booked the
- output. It is blocking when a debugger is connected, but the
- previous character send is not transmitted. <br><br>
- Return: the input character 'chr'.</td>
- </tr>
- </tbody>
-</table>
-
-<p>
- Example for the usage of the ITM Channel 31 for RTOS Kernels:
-</p>
-<pre>
- // check if debugger connected and ITM channel enabled for tracing
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
- (ITM->TCR & ITM_TCR_ITMENA) &&
- (ITM->TER & (1UL << 31))) {
- // transmit trace data
- while (ITM->PORT31_U32 == 0);
- ITM->PORT[31].u8 = task_id; // id of next task
- while (ITM->PORT[31].u32 == 0);
- ITM->PORT[31].u32 = task_status; // status information
- }</pre>
-
-
-<h3>Cortex-M3 additional Debug Access</h3>
-
-<p>CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access.
-Data can be transmitted via a certain global buffer variable towards the target system.</p>
-
-<p>The buffer variable and the prototypes of the additional functions are shown in the
-table below.</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">Name</th>
- <th class="kt">Parameter</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">extern volatile int ITM_RxBuffer</td>
- <td class="kt"> </td>
- <td class="kt">Buffer to transmit data towards debug system. <br><br>
- Value 0x5AA55AA5 indicates that buffer is empty.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">int ITM_ReceiveChar (void)</td>
- <td class="kt">none</td>
- <td class="kt">The nonblocking functions returns the character stored in
- ITM_RxBuffer. <br><br>
- Return: -1 indicates that no character was received.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">int ITM_CheckChar (void)</td>
- <td class="kt">none</td>
- <td class="kt">The function checks if a character is available in ITM_RxBuffer. <br><br>
- Return: 1 indicates that a character is available, 0 indicates that
- no character is available.</td>
- </tr>
- </tbody>
-</table>
-
-
-<h2><a name="5"></a>CMSIS Example</h2>
-<p>
- The following section shows a typical example for using the CMSIS layer in user applications.
- The example is based on a STM32F10x Device.
-</p>
-<pre>
-#include "stm32f10x.h"
-
-volatile uint32_t msTicks; /* timeTicks counter */
-
-void SysTick_Handler(void) {
- msTicks++; /* increment timeTicks counter */
-}
-
-__INLINE static void Delay (uint32_t dlyTicks) {
- uint32_t curTicks = msTicks;
-
- while ((msTicks - curTicks) < dlyTicks);
-}
-
-__INLINE static void LED_Config(void) {
- ; /* Configure the LEDs */
-}
-
-__INLINE static void LED_On (uint32_t led) {
- ; /* Turn On LED */
-}
-
-__INLINE static void LED_Off (uint32_t led) {
- ; /* Turn Off LED */
-}
-
-int main (void) {
- if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */
- ; /* Handle Error */
- while (1);
- }
-
- LED_Config(); /* configure the LEDs */
-
- while(1) {
- LED_On (0x100); /* Turn on the LED */
- Delay (100); /* delay 100 Msec */
- LED_Off (0x100); /* Turn off the LED */
- Delay (100); /* delay 100 Msec */
- }
-}</pre>
-
-
-</body></html>
\ No newline at end of file
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/License.doc b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/License.doc
deleted file mode 100644
index b6b8ace..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/CMSIS/License.doc
+++ /dev/null
Binary files differ
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/Common/fonts.c b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/Common/fonts.c
deleted file mode 100644
index d45111b..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/Common/fonts.c
+++ /dev/null
@@ -1,996 +0,0 @@
-/**
- ******************************************************************************
- * @file fonts.c
- * @author MCD Application Team
- * @version V4.4.0RC1
- * @date 07/02/2010
- * @brief This file provides text fonts for STM32xx-EVAL's LCD driver.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "fonts.h"
-
-/** @addtogroup Utilities
- * @{
- */
-
-/** @addtogroup STM32_EVAL
- * @{
- */
-
-/** @addtogroup Common
- * @{
- */
-
-/** @addtogroup FONTS
- * @brief This file includes the Fonts driver of STM32-EVAL boards.
- * @{
- */
-
-/** @defgroup FONTS_Private_Types
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup FONTS_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup FONTS_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup FONTS_Private_Variables
- * @{
- */
-const uint16_t ASCII16x24_Table [] = {
-/**
- * @brief Space ' '
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '!'
- */
- 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
- 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, 0x0000,
- 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '"'
- */
- 0x0000, 0x0000, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '#'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C60, 0x0C60,
- 0x0C60, 0x0630, 0x0630, 0x1FFE, 0x1FFE, 0x0630, 0x0738, 0x0318,
- 0x1FFE, 0x1FFE, 0x0318, 0x0318, 0x018C, 0x018C, 0x018C, 0x0000,
-/**
- * @brief '$'
- */
- 0x0000, 0x0080, 0x03E0, 0x0FF8, 0x0E9C, 0x1C8C, 0x188C, 0x008C,
- 0x0098, 0x01F8, 0x07E0, 0x0E80, 0x1C80, 0x188C, 0x188C, 0x189C,
- 0x0CB8, 0x0FF0, 0x03E0, 0x0080, 0x0080, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '%'
- */
- 0x0000, 0x0000, 0x0000, 0x180E, 0x0C1B, 0x0C11, 0x0611, 0x0611,
- 0x0311, 0x0311, 0x019B, 0x018E, 0x38C0, 0x6CC0, 0x4460, 0x4460,
- 0x4430, 0x4430, 0x4418, 0x6C18, 0x380C, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '&'
- */
- 0x0000, 0x01E0, 0x03F0, 0x0738, 0x0618, 0x0618, 0x0330, 0x01F0,
- 0x00F0, 0x00F8, 0x319C, 0x330E, 0x1E06, 0x1C06, 0x1C06, 0x3F06,
- 0x73FC, 0x21F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '''
- */
- 0x0000, 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '('
- */
- 0x0000, 0x0200, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x0060, 0x0060,
- 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,
- 0x0060, 0x0060, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0200, 0x0000,
-/**
- * @brief ')'
- */
- 0x0000, 0x0020, 0x0060, 0x00C0, 0x0180, 0x0180, 0x0300, 0x0300,
- 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,
- 0x0300, 0x0300, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0020, 0x0000,
-/**
- * @brief '*'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
- 0x06D8, 0x07F8, 0x01E0, 0x0330, 0x0738, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '+'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
- 0x0180, 0x0180, 0x0180, 0x3FFC, 0x3FFC, 0x0180, 0x0180, 0x0180,
- 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief ','
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000,
-/**
- * @brief '-'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x07E0, 0x07E0, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '.'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '/'
- */
- 0x0000, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300,
- 0x0300, 0x0380, 0x0180, 0x0180, 0x0180, 0x00C0, 0x00C0, 0x00C0,
- 0x0060, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '0'
- */
- 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x180C, 0x180C, 0x180C,
- 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C18, 0x0E38,
- 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '1'
- */
- 0x0000, 0x0100, 0x0180, 0x01C0, 0x01F0, 0x0198, 0x0188, 0x0180,
- 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
- 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '2'
- */
- 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x1800,
- 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,
- 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '3'
- */
- 0x0000, 0x01E0, 0x07F8, 0x0E18, 0x0C0C, 0x0C0C, 0x0C00, 0x0600,
- 0x03C0, 0x07C0, 0x0C00, 0x1800, 0x1800, 0x180C, 0x180C, 0x0C18,
- 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '4'
- */
- 0x0000, 0x0C00, 0x0E00, 0x0F00, 0x0F00, 0x0D80, 0x0CC0, 0x0C60,
- 0x0C60, 0x0C30, 0x0C18, 0x0C0C, 0x3FFC, 0x3FFC, 0x0C00, 0x0C00,
- 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '5'
- */
- 0x0000, 0x0FF8, 0x0FF8, 0x0018, 0x0018, 0x000C, 0x03EC, 0x07FC,
- 0x0E1C, 0x1C00, 0x1800, 0x1800, 0x1800, 0x180C, 0x0C1C, 0x0E18,
- 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '6'
- */
- 0x0000, 0x07C0, 0x0FF0, 0x1C38, 0x1818, 0x0018, 0x000C, 0x03CC,
- 0x0FEC, 0x0E3C, 0x1C1C, 0x180C, 0x180C, 0x180C, 0x1C18, 0x0E38,
- 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '7'
- */
- 0x0000, 0x1FFC, 0x1FFC, 0x0C00, 0x0600, 0x0600, 0x0300, 0x0380,
- 0x0180, 0x01C0, 0x00C0, 0x00E0, 0x0060, 0x0060, 0x0070, 0x0030,
- 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '8'
- */
- 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x0C18, 0x0C18, 0x0638,
- 0x07F0, 0x07F0, 0x0C18, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C38,
- 0x0FF8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '9'
- */
- 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C1C, 0x180C, 0x180C, 0x180C,
- 0x1C1C, 0x1E38, 0x1BF8, 0x19E0, 0x1800, 0x0C00, 0x0C00, 0x0E1C,
- 0x07F8, 0x01F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief ':'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief ';'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '<'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x1000, 0x1C00, 0x0F80, 0x03E0, 0x00F8, 0x0018, 0x00F8, 0x03E0,
- 0x0F80, 0x1C00, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '='
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x1FF8, 0x0000, 0x0000, 0x0000, 0x1FF8, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '>'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0008, 0x0038, 0x01F0, 0x07C0, 0x1F00, 0x1800, 0x1F00, 0x07C0,
- 0x01F0, 0x0038, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '?'
- */
- 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x0C00,
- 0x0600, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x0000, 0x0000,
- 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '@'
- */
- 0x0000, 0x0000, 0x07E0, 0x1818, 0x2004, 0x29C2, 0x4A22, 0x4411,
- 0x4409, 0x4409, 0x4409, 0x2209, 0x1311, 0x0CE2, 0x4002, 0x2004,
- 0x1818, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'A'
- */
- 0x0000, 0x0380, 0x0380, 0x06C0, 0x06C0, 0x06C0, 0x0C60, 0x0C60,
- 0x1830, 0x1830, 0x1830, 0x3FF8, 0x3FF8, 0x701C, 0x600C, 0x600C,
- 0xC006, 0xC006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'B'
- */
- 0x0000, 0x03FC, 0x0FFC, 0x0C0C, 0x180C, 0x180C, 0x180C, 0x0C0C,
- 0x07FC, 0x0FFC, 0x180C, 0x300C, 0x300C, 0x300C, 0x300C, 0x180C,
- 0x1FFC, 0x07FC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'C'
- */
- 0x0000, 0x07C0, 0x1FF0, 0x3838, 0x301C, 0x700C, 0x6006, 0x0006,
- 0x0006, 0x0006, 0x0006, 0x0006, 0x0006, 0x6006, 0x700C, 0x301C,
- 0x1FF0, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'D'
- */
- 0x0000, 0x03FE, 0x0FFE, 0x0E06, 0x1806, 0x1806, 0x3006, 0x3006,
- 0x3006, 0x3006, 0x3006, 0x3006, 0x3006, 0x1806, 0x1806, 0x0E06,
- 0x0FFE, 0x03FE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'E'
- */
- 0x0000, 0x3FFC, 0x3FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
- 0x1FFC, 0x1FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
- 0x3FFC, 0x3FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'F'
- */
- 0x0000, 0x3FF8, 0x3FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
- 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
- 0x0018, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'G'
- */
- 0x0000, 0x0FE0, 0x3FF8, 0x783C, 0x600E, 0xE006, 0xC007, 0x0003,
- 0x0003, 0xFE03, 0xFE03, 0xC003, 0xC007, 0xC006, 0xC00E, 0xF03C,
- 0x3FF8, 0x0FE0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'H'
- */
- 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
- 0x3FFC, 0x3FFC, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
- 0x300C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'I'
- */
- 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
- 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
- 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'J'
- */
- 0x0000, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,
- 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0618, 0x0618, 0x0738,
- 0x03F0, 0x01E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'K'
- */
- 0x0000, 0x3006, 0x1806, 0x0C06, 0x0606, 0x0306, 0x0186, 0x00C6,
- 0x0066, 0x0076, 0x00DE, 0x018E, 0x0306, 0x0606, 0x0C06, 0x1806,
- 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'L'
- */
- 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
- 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
- 0x1FF8, 0x1FF8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'M'
- */
- 0x0000, 0xE00E, 0xF01E, 0xF01E, 0xF01E, 0xD836, 0xD836, 0xD836,
- 0xD836, 0xCC66, 0xCC66, 0xCC66, 0xC6C6, 0xC6C6, 0xC6C6, 0xC6C6,
- 0xC386, 0xC386, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'N'
- */
- 0x0000, 0x300C, 0x301C, 0x303C, 0x303C, 0x306C, 0x306C, 0x30CC,
- 0x30CC, 0x318C, 0x330C, 0x330C, 0x360C, 0x360C, 0x3C0C, 0x3C0C,
- 0x380C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'O'
- */
- 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xC003, 0xC003,
- 0xC003, 0xC003, 0xC003, 0xC003, 0xC003, 0x6006, 0x700E, 0x381C,
- 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'P'
- */
- 0x0000, 0x0FFC, 0x1FFC, 0x380C, 0x300C, 0x300C, 0x300C, 0x300C,
- 0x180C, 0x1FFC, 0x07FC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
- 0x000C, 0x000C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'Q'
- */
- 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xE003, 0xC003,
- 0xC003, 0xC003, 0xC003, 0xC003, 0xE007, 0x6306, 0x3F0E, 0x3C1C,
- 0x3FF8, 0xF7E0, 0xC000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'R'
- */
- 0x0000, 0x0FFE, 0x1FFE, 0x3806, 0x3006, 0x3006, 0x3006, 0x3806,
- 0x1FFE, 0x07FE, 0x0306, 0x0606, 0x0C06, 0x1806, 0x1806, 0x3006,
- 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'S'
- */
- 0x0000, 0x03E0, 0x0FF8, 0x0C1C, 0x180C, 0x180C, 0x000C, 0x001C,
- 0x03F8, 0x0FE0, 0x1E00, 0x3800, 0x3006, 0x3006, 0x300E, 0x1C1C,
- 0x0FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'T'
- */
- 0x0000, 0x7FFE, 0x7FFE, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
- 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
- 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'U'
- */
- 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
- 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x1818,
- 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'V'
- */
- 0x0000, 0x6003, 0x3006, 0x3006, 0x3006, 0x180C, 0x180C, 0x180C,
- 0x0C18, 0x0C18, 0x0E38, 0x0630, 0x0630, 0x0770, 0x0360, 0x0360,
- 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'W'
- */
- 0x0000, 0x6003, 0x61C3, 0x61C3, 0x61C3, 0x3366, 0x3366, 0x3366,
- 0x3366, 0x3366, 0x3366, 0x1B6C, 0x1B6C, 0x1B6C, 0x1A2C, 0x1E3C,
- 0x0E38, 0x0E38, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'X'
- */
- 0x0000, 0xE00F, 0x700C, 0x3018, 0x1830, 0x0C70, 0x0E60, 0x07C0,
- 0x0380, 0x0380, 0x03C0, 0x06E0, 0x0C70, 0x1C30, 0x1818, 0x300C,
- 0x600E, 0xE007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'Y'
- */
- 0x0000, 0xC003, 0x6006, 0x300C, 0x381C, 0x1838, 0x0C30, 0x0660,
- 0x07E0, 0x03C0, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
- 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'Z'
- */
- 0x0000, 0x7FFC, 0x7FFC, 0x6000, 0x3000, 0x1800, 0x0C00, 0x0600,
- 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, 0x000C, 0x0006,
- 0x7FFE, 0x7FFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '['
- */
- 0x0000, 0x03E0, 0x03E0, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,
- 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,
- 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x03E0, 0x03E0, 0x0000,
-/**
- * @brief '\'
- */
- 0x0000, 0x0030, 0x0030, 0x0060, 0x0060, 0x0060, 0x00C0, 0x00C0,
- 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0300, 0x0300, 0x0300,
- 0x0600, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief ']'
- */
- 0x0000, 0x03E0, 0x03E0, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,
- 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,
- 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x03E0, 0x03E0, 0x0000,
-/**
- * @brief '^'
- */
- 0x0000, 0x0000, 0x01C0, 0x01C0, 0x0360, 0x0360, 0x0360, 0x0630,
- 0x0630, 0x0C18, 0x0C18, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '_'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000, 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '''
- */
- 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'a'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03F0, 0x07F8,
- 0x0C1C, 0x0C0C, 0x0F00, 0x0FF0, 0x0CF8, 0x0C0C, 0x0C0C, 0x0F1C,
- 0x0FF8, 0x18F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'b'
- */
- 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x03D8, 0x0FF8,
- 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,
- 0x0FF8, 0x03D8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'c'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x07F0,
- 0x0E30, 0x0C18, 0x0018, 0x0018, 0x0018, 0x0018, 0x0C18, 0x0E30,
- 0x07F0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'd'
- */
- 0x0000, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1BC0, 0x1FF0,
- 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,
- 0x1FF0, 0x1BC0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'e'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,
- 0x0C30, 0x1818, 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x1838, 0x1C30,
- 0x0FF0, 0x07C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'f'
- */
- 0x0000, 0x0F80, 0x0FC0, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,
- 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
- 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'g'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0DE0, 0x0FF8,
- 0x0E18, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0E18,
- 0x0FF8, 0x0DE0, 0x0C00, 0x0C0C, 0x061C, 0x07F8, 0x01F0, 0x0000,
-/**
- * @brief 'h'
- */
- 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x07D8, 0x0FF8,
- 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,
- 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'i'
- */
- 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
- 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
- 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'j'
- */
- 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
- 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
- 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00F8, 0x0078, 0x0000,
-/**
- * @brief 'k'
- */
- 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0C0C, 0x060C,
- 0x030C, 0x018C, 0x00CC, 0x006C, 0x00FC, 0x019C, 0x038C, 0x030C,
- 0x060C, 0x0C0C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'l'
- */
- 0x0000, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
- 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
- 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'm'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3C7C, 0x7EFF,
- 0xE3C7, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183,
- 0xC183, 0xC183, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'n'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0798, 0x0FF8,
- 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,
- 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'o'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,
- 0x0C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C30,
- 0x0FF0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'p'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03D8, 0x0FF8,
- 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,
- 0x0FF8, 0x03D8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0000,
-/**
- * @brief 'q'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1BC0, 0x1FF0,
- 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,
- 0x1FF0, 0x1BC0, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x0000,
-/**
- * @brief 'r'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x07B0, 0x03F0,
- 0x0070, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,
- 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 's'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03E0, 0x03F0,
- 0x0E38, 0x0C18, 0x0038, 0x03F0, 0x07C0, 0x0C00, 0x0C18, 0x0E38,
- 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 't'
- */
- 0x0000, 0x0000, 0x0080, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,
- 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
- 0x07C0, 0x0780, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'u'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1818, 0x1818,
- 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C38,
- 0x1FF0, 0x19E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'v'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x180C, 0x0C18,
- 0x0C18, 0x0C18, 0x0630, 0x0630, 0x0630, 0x0360, 0x0360, 0x0360,
- 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'w'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0x41C1,
- 0x61C3, 0x6363, 0x6363, 0x6363, 0x3636, 0x3636, 0x3636, 0x1C1C,
- 0x1C1C, 0x1C1C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'x'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x381C, 0x1C38,
- 0x0C30, 0x0660, 0x0360, 0x0360, 0x0360, 0x0360, 0x0660, 0x0C30,
- 0x1C38, 0x381C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief 'y'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3018, 0x1830,
- 0x1830, 0x1870, 0x0C60, 0x0C60, 0x0CE0, 0x06C0, 0x06C0, 0x0380,
- 0x0380, 0x0380, 0x0180, 0x0180, 0x01C0, 0x00F0, 0x0070, 0x0000,
-/**
- * @brief 'z'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1FFC, 0x1FFC,
- 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,
- 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/**
- * @brief '{'
- */
- 0x0000, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
- 0x00C0, 0x0060, 0x0060, 0x0030, 0x0060, 0x0040, 0x00C0, 0x00C0,
- 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0000, 0x0000,
-/**
- * @brief '|'
- */
- 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
- 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
- 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000,
-/**
- * @brief '}'
- */
- 0x0000, 0x0060, 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0180,
- 0x0180, 0x0300, 0x0300, 0x0600, 0x0300, 0x0100, 0x0180, 0x0180,
- 0x0180, 0x0180, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0000, 0x0000,
-/**
- * @brief '~'
- */
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x10F0, 0x1FF8, 0x0F08, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000};
-
-const uint16_t ASCII12x12_Table [] = {
- 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
- 0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x0000,0x2000,0x0000,0x0000,
- 0x0000,0x5000,0x5000,0x5000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
- 0x0000,0x0900,0x0900,0x1200,0x7f00,0x1200,0x7f00,0x1200,0x2400,0x2400,0x0000,0x0000,
- 0x1000,0x3800,0x5400,0x5000,0x5000,0x3800,0x1400,0x5400,0x5400,0x3800,0x1000,0x0000,
- 0x0000,0x3080,0x4900,0x4900,0x4a00,0x32c0,0x0520,0x0920,0x0920,0x10c0,0x0000,0x0000,
- 0x0000,0x0c00,0x1200,0x1200,0x1400,0x1800,0x2500,0x2300,0x2300,0x1d80,0x0000,0x0000,
- 0x0000,0x4000,0x4000,0x4000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
- 0x0000,0x0800,0x1000,0x1000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x1000,0x1000,
- 0x0000,0x4000,0x2000,0x2000,0x1000,0x1000,0x1000,0x1000,0x1000,0x1000,0x2000,0x2000,
- 0x0000,0x2000,0x7000,0x2000,0x5000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
- 0x0000,0x0000,0x0000,0x0800,0x0800,0x7f00,0x0800,0x0800,0x0000,0x0000,0x0000,0x0000,
- 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2000,0x4000,
- 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x7000,0x0000,0x0000,0x0000,0x0000,0x0000,
- 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,
- 0x0000,0x1000,0x1000,0x1000,0x2000,0x2000,0x2000,0x2000,0x4000,0x4000,0x0000,0x0000,
- 0x0000,0x1000,0x2800,0x4400,0x4400,0x4400,0x4400,0x4400,0x2800,0x1000,0x0000,0x0000,
- 0x0000,0x1000,0x3000,0x5000,0x1000,0x1000,0x1000,0x1000,0x1000,0x1000,0x0000,0x0000,
- 0x0000,0x3000,0x4800,0x4400,0x0400,0x0800,0x1000,0x2000,0x4000,0x7c00,0x0000,0x0000,
- 0x0000,0x3000,0x4800,0x0400,0x0800,0x1000,0x0800,0x4400,0x4800,0x3000,0x0000,0x0000,
- 0x0000,0x0800,0x1800,0x1800,0x2800,0x2800,0x4800,0x7c00,0x0800,0x0800,0x0000,0x0000,
- 0x0000,0x3c00,0x2000,0x4000,0x7000,0x4800,0x0400,0x4400,0x4800,0x3000,0x0000,0x0000,
- 0x0000,0x1800,0x2400,0x4000,0x5000,0x6800,0x4400,0x4400,0x2800,0x1000,0x0000,0x0000,
- 0x0000,0x7c00,0x0400,0x0800,0x1000,0x1000,0x1000,0x2000,0x2000,0x2000,0x0000,0x0000,
- 0x0000,0x1000,0x2800,0x4400,0x2800,0x1000,0x2800,0x4400,0x2800,0x1000,0x0000,0x0000,
- 0x0000,0x1000,0x2800,0x4400,0x4400,0x2c00,0x1400,0x0400,0x4800,0x3000,0x0000,0x0000,
- 0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,
- 0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2000,0x4000,
- 0x0000,0x0000,0x0400,0x0800,0x3000,0x4000,0x3000,0x0800,0x0400,0x0000,0x0000,0x0000,
- 0x0000,0x0000,0x0000,0x7c00,0x0000,0x0000,0x7c00,0x0000,0x0000,0x0000,0x0000,0x0000,
- 0x0000,0x0000,0x4000,0x2000,0x1800,0x0400,0x1800,0x2000,0x4000,0x0000,0x0000,0x0000,
- 0x0000,0x3800,0x6400,0x4400,0x0400,0x0800,0x1000,0x1000,0x0000,0x1000,0x0000,0x0000,
- 0x0000,0x0f80,0x1040,0x2ea0,0x51a0,0x5120,0x5120,0x5120,0x5320,0x4dc0,0x2020,0x1040,
- 0x0000,0x0800,0x1400,0x1400,0x1400,0x2200,0x3e00,0x2200,0x4100,0x4100,0x0000,0x0000,
- 0x0000,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x0000,0x0000,
- 0x0000,0x0e00,0x1100,0x2100,0x2000,0x2000,0x2000,0x2100,0x1100,0x0e00,0x0000,0x0000,
- 0x0000,0x3c00,0x2200,0x2100,0x2100,0x2100,0x2100,0x2100,0x2200,0x3c00,0x0000,0x0000,
- 0x0000,0x3e00,0x2000,0x2000,0x2000,0x3e00,0x2000,0x2000,0x2000,0x3e00,0x0000,0x0000,
- 0x0000,0x3e00,0x2000,0x2000,0x2000,0x3c00,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000,
- 0x0000,0x0e00,0x1100,0x2100,0x2000,0x2700,0x2100,0x2100,0x1100,0x0e00,0x0000,0x0000,
- 0x0000,0x2100,0x2100,0x2100,0x2100,0x3f00,0x2100,0x2100,0x2100,0x2100,0x0000,0x0000,
- 0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000,
- 0x0000,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x4800,0x4800,0x3000,0x0000,0x0000,
- 0x0000,0x2200,0x2400,0x2800,0x2800,0x3800,0x2800,0x2400,0x2400,0x2200,0x0000,0x0000,
- 0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x3e00,0x0000,0x0000,
- 0x0000,0x2080,0x3180,0x3180,0x3180,0x2a80,0x2a80,0x2a80,0x2a80,0x2480,0x0000,0x0000,
- 0x0000,0x2100,0x3100,0x3100,0x2900,0x2900,0x2500,0x2300,0x2300,0x2100,0x0000,0x0000,
- 0x0000,0x0c00,0x1200,0x2100,0x2100,0x2100,0x2100,0x2100,0x1200,0x0c00,0x0000,0x0000,
- 0x0000,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000,
- 0x0000,0x0c00,0x1200,0x2100,0x2100,0x2100,0x2100,0x2100,0x1600,0x0d00,0x0100,0x0000,
- 0x0000,0x3e00,0x2100,0x2100,0x2100,0x3e00,0x2400,0x2200,0x2100,0x2080,0x0000,0x0000,
- 0x0000,0x1c00,0x2200,0x2200,0x2000,0x1c00,0x0200,0x2200,0x2200,0x1c00,0x0000,0x0000,
- 0x0000,0x3e00,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0000,0x0000,
- 0x0000,0x2100,0x2100,0x2100,0x2100,0x2100,0x2100,0x2100,0x1200,0x0c00,0x0000,0x0000,
- 0x0000,0x4100,0x4100,0x2200,0x2200,0x2200,0x1400,0x1400,0x1400,0x0800,0x0000,0x0000,
- 0x0000,0x4440,0x4a40,0x2a40,0x2a80,0x2a80,0x2a80,0x2a80,0x2a80,0x1100,0x0000,0x0000,
- 0x0000,0x4100,0x2200,0x1400,0x1400,0x0800,0x1400,0x1400,0x2200,0x4100,0x0000,0x0000,
- 0x0000,0x4100,0x2200,0x2200,0x1400,0x0800,0x0800,0x0800,0x0800,0x0800,0x0000,0x0000,
- 0x0000,0x7e00,0x0200,0x0400,0x0800,0x1000,0x1000,0x2000,0x4000,0x7e00,0x0000,0x0000,
- 0x0000,0x3000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,
- 0x0000,0x4000,0x4000,0x2000,0x2000,0x2000,0x2000,0x2000,0x1000,0x1000,0x0000,0x0000,
- 0x0000,0x6000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,
- 0x0000,0x1000,0x2800,0x2800,0x2800,0x4400,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
- 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x7e00,
- 0x4000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
- 0x0000,0x0000,0x0000,0x3800,0x4400,0x0400,0x3c00,0x4400,0x4400,0x3c00,0x0000,0x0000,
- 0x0000,0x4000,0x4000,0x5800,0x6400,0x4400,0x4400,0x4400,0x6400,0x5800,0x0000,0x0000,
- 0x0000,0x0000,0x0000,0x3000,0x4800,0x4000,0x4000,0x4000,0x4800,0x3000,0x0000,0x0000,
- 0x0000,0x0400,0x0400,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0000,0x0000,
- 0x0000,0x0000,0x0000,0x3800,0x4400,0x4400,0x7c00,0x4000,0x4400,0x3800,0x0000,0x0000,
- 0x0000,0x6000,0x4000,0xe000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000,
- 0x0000,0x0000,0x0000,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0400,0x4400,
- 0x0000,0x4000,0x4000,0x5800,0x6400,0x4400,0x4400,0x4400,0x4400,0x4400,0x0000,0x0000,
- 0x0000,0x4000,0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000,
- 0x0000,0x4000,0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,
- 0x0000,0x4000,0x4000,0x4800,0x5000,0x6000,0x5000,0x5000,0x4800,0x4800,0x0000,0x0000,
- 0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000,
- 0x0000,0x0000,0x0000,0x5200,0x6d00,0x4900,0x4900,0x4900,0x4900,0x4900,0x0000,0x0000,
- 0x0000,0x0000,0x0000,0x5800,0x6400,0x4400,0x4400,0x4400,0x4400,0x4400,0x0000,0x0000,
- 0x0000,0x0000,0x0000,0x3800,0x4400,0x4400,0x4400,0x4400,0x4400,0x3800,0x0000,0x0000,
- 0x0000,0x0000,0x0000,0x5800,0x6400,0x4400,0x4400,0x4400,0x6400,0x5800,0x4000,0x4000,
- 0x0000,0x0000,0x0000,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0400,0x0400,
- 0x0000,0x0000,0x0000,0x5000,0x6000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000,
- 0x0000,0x0000,0x0000,0x3000,0x4800,0x4000,0x3000,0x0800,0x4800,0x3000,0x0000,0x0000,
- 0x0000,0x4000,0x4000,0xe000,0x4000,0x4000,0x4000,0x4000,0x4000,0x6000,0x0000,0x0000,
- 0x0000,0x0000,0x0000,0x4400,0x4400,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0000,0x0000,
- 0x0000,0x0000,0x0000,0x4400,0x4400,0x2800,0x2800,0x2800,0x2800,0x1000,0x0000,0x0000,
- 0x0000,0x0000,0x0000,0x4900,0x4900,0x5500,0x5500,0x5500,0x5500,0x2200,0x0000,0x0000,
- 0x0000,0x0000,0x0000,0x4400,0x2800,0x2800,0x1000,0x2800,0x2800,0x4400,0x0000,0x0000,
- 0x0000,0x0000,0x0000,0x4400,0x4400,0x2800,0x2800,0x2800,0x1000,0x1000,0x1000,0x1000,
- 0x0000,0x0000,0x0000,0x7800,0x0800,0x1000,0x2000,0x2000,0x4000,0x7800,0x0000,0x0000,
- 0x0000,0x1000,0x2000,0x2000,0x2000,0x2000,0x4000,0x2000,0x2000,0x2000,0x2000,0x2000,
- 0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,
- 0x0000,0x4000,0x2000,0x2000,0x2000,0x2000,0x1000,0x2000,0x2000,0x2000,0x2000,0x2000,
- 0x0000,0x0000,0x0000,0x0000,0x7400,0x5800,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
- 0x0000,0x0000,0x7000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x7000,0x0000,0x0000};
-
-const uint16_t ASCII8x12_Table [] = {
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x10,0x00,
- 0x00,0x00,0x00,0x28,0x28,0x28,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x14,0x14,0x3e,0x14,0x28,0x7c,0x28,0x28,0x00,
- 0x00,0x00,0x10,0x38,0x54,0x50,0x38,0x14,0x14,0x54,0x38,0x10,
- 0x00,0x00,0x00,0x44,0xa8,0xa8,0x50,0x14,0x1a,0x2a,0x24,0x00,
- 0x00,0x00,0x00,0x20,0x50,0x50,0x20,0xe8,0x98,0x98,0x60,0x00,
- 0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x40,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,
- 0x00,0x00,0x00,0x80,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,
- 0x00,0x00,0x00,0x40,0xe0,0x40,0xa0,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x20,0x20,0xf8,0x20,0x20,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x40,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,
- 0x00,0x00,0x00,0x20,0x20,0x20,0x40,0x40,0x80,0x80,0x80,0x00,
- 0x00,0x00,0x00,0x60,0x90,0x90,0x90,0x90,0x90,0x90,0x60,0x00,
- 0x00,0x00,0x00,0x20,0x60,0xa0,0x20,0x20,0x20,0x20,0x20,0x00,
- 0x00,0x00,0x00,0x60,0x90,0x10,0x10,0x20,0x40,0x80,0xf0,0x00,
- 0x00,0x00,0x00,0x60,0x90,0x10,0x60,0x10,0x10,0x90,0x60,0x00,
- 0x00,0x00,0x00,0x10,0x30,0x50,0x50,0x90,0xf8,0x10,0x10,0x00,
- 0x00,0x00,0x00,0x70,0x40,0x80,0xe0,0x10,0x10,0x90,0x60,0x00,
- 0x00,0x00,0x00,0x60,0x90,0x80,0xa0,0xd0,0x90,0x90,0x60,0x00,
- 0x00,0x00,0x00,0xf0,0x10,0x20,0x20,0x20,0x40,0x40,0x40,0x00,
- 0x00,0x00,0x00,0x60,0x90,0x90,0x60,0x90,0x90,0x90,0x60,0x00,
- 0x00,0x00,0x00,0x60,0x90,0x90,0xb0,0x50,0x10,0x90,0x60,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x40,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x40,0x40,
- 0x00,0x00,0x00,0x00,0x00,0x10,0x60,0x80,0x60,0x10,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0xf0,0x00,0xf0,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x80,0x60,0x10,0x60,0x80,0x00,0x00,
- 0x00,0x00,0x00,0x60,0x90,0x10,0x20,0x40,0x40,0x00,0x40,0x00,
- 0x00,0x00,0x00,0x1c,0x22,0x5b,0xa5,0xa5,0xa5,0xa5,0x9e,0x41,
- 0x00,0x00,0x00,0x20,0x50,0x50,0x50,0x50,0x70,0x88,0x88,0x00,
- 0x00,0x00,0x00,0xf0,0x88,0x88,0xf0,0x88,0x88,0x88,0xf0,0x00,
- 0x00,0x00,0x00,0x38,0x44,0x84,0x80,0x80,0x84,0x44,0x38,0x00,
- 0x00,0x00,0x00,0xe0,0x90,0x88,0x88,0x88,0x88,0x90,0xe0,0x00,
- 0x00,0x00,0x00,0xf8,0x80,0x80,0xf8,0x80,0x80,0x80,0xf8,0x00,
- 0x00,0x00,0x00,0x78,0x40,0x40,0x70,0x40,0x40,0x40,0x40,0x00,
- 0x00,0x00,0x00,0x38,0x44,0x84,0x80,0x9c,0x84,0x44,0x38,0x00,
- 0x00,0x00,0x00,0x88,0x88,0x88,0xf8,0x88,0x88,0x88,0x88,0x00,
- 0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,
- 0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x90,0x90,0x60,0x00,
- 0x00,0x00,0x00,0x88,0x90,0xa0,0xe0,0xa0,0x90,0x90,0x88,0x00,
- 0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0xf0,0x00,
- 0x00,0x00,0x00,0x82,0xc6,0xc6,0xaa,0xaa,0xaa,0xaa,0x92,0x00,
- 0x00,0x00,0x00,0x84,0xc4,0xa4,0xa4,0x94,0x94,0x8c,0x84,0x00,
- 0x00,0x00,0x00,0x30,0x48,0x84,0x84,0x84,0x84,0x48,0x30,0x00,
- 0x00,0x00,0x00,0xf0,0x88,0x88,0x88,0xf0,0x80,0x80,0x80,0x00,
- 0x00,0x00,0x00,0x30,0x48,0x84,0x84,0x84,0x84,0x58,0x34,0x04,
- 0x00,0x00,0x00,0x78,0x44,0x44,0x78,0x50,0x48,0x44,0x42,0x00,
- 0x00,0x00,0x00,0x70,0x88,0x80,0x70,0x08,0x88,0x88,0x70,0x00,
- 0x00,0x00,0x00,0xf8,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,
- 0x00,0x00,0x00,0x84,0x84,0x84,0x84,0x84,0x84,0x48,0x30,0x00,
- 0x00,0x00,0x00,0x88,0x88,0x50,0x50,0x50,0x50,0x50,0x20,0x00,
- 0x00,0x00,0x00,0x92,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0x44,0x00,
- 0x00,0x00,0x00,0x84,0x48,0x48,0x30,0x30,0x48,0x48,0x84,0x00,
- 0x00,0x00,0x00,0x88,0x50,0x50,0x20,0x20,0x20,0x20,0x20,0x00,
- 0x00,0x00,0x00,0xf8,0x08,0x10,0x20,0x20,0x40,0x80,0xf8,0x00,
- 0x00,0x00,0x00,0xc0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,
- 0x00,0x00,0x00,0x80,0x80,0x40,0x40,0x40,0x40,0x20,0x20,0x00,
- 0x00,0x00,0x00,0xc0,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,
- 0x00,0x00,0x00,0x40,0xa0,0xa0,0xa0,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf8,
- 0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0xe0,0x10,0x70,0x90,0x90,0x70,0x00,
- 0x00,0x00,0x00,0x80,0x80,0xa0,0xd0,0x90,0x90,0xd0,0xa0,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x60,0x90,0x80,0x80,0x90,0x60,0x00,
- 0x00,0x00,0x00,0x10,0x10,0x50,0xb0,0x90,0x90,0xb0,0x50,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x60,0x90,0xf0,0x80,0x90,0x60,0x00,
- 0x00,0x00,0x00,0xc0,0x80,0xc0,0x80,0x80,0x80,0x80,0x80,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x50,0xb0,0x90,0x90,0xb0,0x50,0x10,
- 0x00,0x00,0x00,0x80,0x80,0xa0,0xd0,0x90,0x90,0x90,0x90,0x00,
- 0x00,0x00,0x00,0x80,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x00,
- 0x00,0x00,0x00,0x80,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,
- 0x00,0x00,0x00,0x80,0x80,0x90,0xa0,0xc0,0xa0,0x90,0x90,0x00,
- 0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,
- 0x00,0x00,0x00,0x00,0x00,0xa6,0xda,0x92,0x92,0x92,0x92,0x00,
- 0x00,0x00,0x00,0x00,0x00,0xa0,0xd0,0x90,0x90,0x90,0x90,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x60,0x90,0x90,0x90,0x90,0x60,0x00,
- 0x00,0x00,0x00,0x00,0x00,0xa0,0xd0,0x90,0x90,0xd0,0xa0,0x80,
- 0x00,0x00,0x00,0x00,0x00,0x50,0xb0,0x90,0x90,0xb0,0x50,0x10,
- 0x00,0x00,0x00,0x00,0x00,0xa0,0xc0,0x80,0x80,0x80,0x80,0x00,
- 0x00,0x00,0x00,0x00,0x00,0xe0,0x90,0x40,0x20,0x90,0x60,0x00,
- 0x00,0x00,0x00,0x80,0x80,0xc0,0x80,0x80,0x80,0x80,0xc0,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x90,0x90,0x90,0x90,0xb0,0x50,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x88,0x88,0x50,0x50,0x50,0x20,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x92,0xaa,0xaa,0xaa,0xaa,0x44,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x88,0x50,0x20,0x20,0x50,0x88,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x88,0x50,0x50,0x50,0x20,0x20,0x20,
- 0x00,0x00,0x00,0x00,0x00,0xf0,0x10,0x20,0x40,0x80,0xf0,0x00,
- 0x00,0x00,0x00,0xc0,0x80,0x80,0x80,0x00,0x80,0x80,0x80,0x80,
- 0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,
- 0x00,0x00,0x00,0xc0,0x40,0x40,0x40,0x20,0x40,0x40,0x40,0x40,
- 0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0xb0,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,0xe0,0xa0,0xa0,0xa0,0xa0,0xa0,0xe0,0x00};
-
-const uint16_t ASCII8x8_Table [] = {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x40,
- 0xa0, 0xa0, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x24, 0x24, 0xfe, 0x48, 0xfc, 0x48, 0x48,
- 0x38, 0x54, 0x50, 0x38, 0x14, 0x14, 0x54, 0x38,
- 0x44, 0xa8, 0xa8, 0x50, 0x14, 0x1a, 0x2a, 0x24,
- 0x10, 0x28, 0x28, 0x10, 0x74, 0x4c, 0x4c, 0x30,
- 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x08, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x08,
- 0x10, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x10,
- 0x00, 0x00, 0x24, 0x18, 0x3c, 0x18, 0x24, 0x00,
- 0x00, 0x00, 0x10, 0x10, 0x7c, 0x10, 0x10, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x10,
- 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18,
- 0x08, 0x08, 0x08, 0x10, 0x10, 0x20, 0x20, 0x20,
- 0x18, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x18,
- 0x08, 0x18, 0x28, 0x08, 0x08, 0x08, 0x08, 0x08,
- 0x38, 0x44, 0x00, 0x04, 0x08, 0x10, 0x20, 0x7c,
- 0x18, 0x24, 0x04, 0x18, 0x04, 0x04, 0x24, 0x18,
- 0x04, 0x0c, 0x14, 0x24, 0x44, 0x7e, 0x04, 0x04,
- 0x3c, 0x20, 0x20, 0x38, 0x04, 0x04, 0x24, 0x18,
- 0x18, 0x24, 0x20, 0x38, 0x24, 0x24, 0x24, 0x18,
- 0x3c, 0x04, 0x08, 0x08, 0x08, 0x10, 0x10, 0x10,
- 0x18, 0x24, 0x24, 0x18, 0x24, 0x24, 0x24, 0x18,
- 0x18, 0x24, 0x24, 0x24, 0x1c, 0x04, 0x24, 0x18,
- 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00,
- 0x00, 0x00, 0x08, 0x00, 0x00, 0x08, 0x10, 0x00,
- 0x00, 0x00, 0x04, 0x18, 0x20, 0x18, 0x04, 0x00,
- 0x00, 0x00, 0x00, 0x3c, 0x00, 0x3c, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x18, 0x04, 0x18, 0x20, 0x00,
- 0x18, 0x24, 0x04, 0x08, 0x10, 0x10, 0x00, 0x10,
- 0x3c, 0x42, 0x99, 0xa5, 0xa5, 0x9d, 0x42, 0x38,
- 0x38, 0x44, 0x44, 0x44, 0x7c, 0x44, 0x44, 0x44,
- 0x78, 0x44, 0x44, 0x78, 0x44, 0x44, 0x44, 0x78,
- 0x1c, 0x22, 0x42, 0x40, 0x40, 0x42, 0x22, 0x1c,
- 0x70, 0x48, 0x44, 0x44, 0x44, 0x44, 0x48, 0x70,
- 0x7c, 0x40, 0x40, 0x7c, 0x40, 0x40, 0x40, 0x7c,
- 0x3c, 0x20, 0x20, 0x38, 0x20, 0x20, 0x20, 0x20,
- 0x1c, 0x22, 0x42, 0x40, 0x4e, 0x42, 0x22, 0x1c,
- 0x44, 0x44, 0x44, 0x7c, 0x44, 0x44, 0x44, 0x44,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
- 0x04, 0x04, 0x04, 0x04, 0x04, 0x24, 0x24, 0x18,
- 0x44, 0x48, 0x50, 0x70, 0x50, 0x48, 0x48, 0x44,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x3c,
- 0x82, 0xc6, 0xc6, 0xaa, 0xaa, 0xaa, 0xaa, 0x92,
- 0x42, 0x62, 0x52, 0x52, 0x4a, 0x4a, 0x46, 0x42,
- 0x18, 0x24, 0x42, 0x42, 0x42, 0x42, 0x24, 0x18,
- 0x78, 0x44, 0x44, 0x44, 0x78, 0x40, 0x40, 0x40,
- 0x18, 0x24, 0x42, 0x42, 0x42, 0x42, 0x2c, 0x1a,
- 0x78, 0x44, 0x44, 0x78, 0x50, 0x48, 0x44, 0x42,
- 0x38, 0x44, 0x40, 0x38, 0x04, 0x44, 0x44, 0x38,
- 0x7c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
- 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x24, 0x18,
- 0x44, 0x44, 0x28, 0x28, 0x28, 0x28, 0x28, 0x10,
- 0x92, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x44,
- 0x42, 0x24, 0x24, 0x18, 0x18, 0x24, 0x24, 0x42,
- 0x44, 0x28, 0x28, 0x10, 0x10, 0x10, 0x10, 0x10,
- 0x7c, 0x04, 0x08, 0x10, 0x10, 0x20, 0x40, 0x7c,
- 0x1c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x1c,
- 0x10, 0x10, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04,
- 0x1c, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x1c,
- 0x10, 0x28, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x20, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x18, 0x04, 0x1c, 0x24, 0x24, 0x1c,
- 0x20, 0x20, 0x28, 0x34, 0x24, 0x24, 0x34, 0x28,
- 0x00, 0x00, 0x18, 0x24, 0x20, 0x20, 0x24, 0x18,
- 0x04, 0x04, 0x14, 0x2c, 0x24, 0x24, 0x2c, 0x14,
- 0x00, 0x00, 0x18, 0x24, 0x3c, 0x20, 0x24, 0x18,
- 0x00, 0x18, 0x10, 0x10, 0x18, 0x10, 0x10, 0x10,
- 0x00, 0x18, 0x24, 0x24, 0x18, 0x04, 0x24, 0x18,
- 0x20, 0x20, 0x28, 0x34, 0x24, 0x24, 0x24, 0x24,
- 0x10, 0x00, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
- 0x08, 0x00, 0x08, 0x08, 0x08, 0x08, 0x28, 0x10,
- 0x20, 0x20, 0x24, 0x28, 0x30, 0x28, 0x24, 0x24,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
- 0x00, 0x00, 0xa6, 0xda, 0x92, 0x92, 0x92, 0x92,
- 0x00, 0x00, 0x28, 0x34, 0x24, 0x24, 0x24, 0x24,
- 0x00, 0x00, 0x18, 0x24, 0x24, 0x24, 0x24, 0x18,
- 0x00, 0x28, 0x34, 0x24, 0x38, 0x20, 0x20, 0x20,
- 0x00, 0x14, 0x2c, 0x24, 0x1c, 0x04, 0x04, 0x04,
- 0x00, 0x00, 0x2c, 0x30, 0x20, 0x20, 0x20, 0x20,
- 0x00, 0x00, 0x18, 0x24, 0x10, 0x08, 0x24, 0x18,
- 0x00, 0x10, 0x38, 0x10, 0x10, 0x10, 0x10, 0x18,
- 0x00, 0x00, 0x24, 0x24, 0x24, 0x24, 0x2c, 0x14,
- 0x00, 0x00, 0x44, 0x44, 0x28, 0x28, 0x28, 0x10,
- 0x00, 0x00, 0x92, 0xaa, 0xaa, 0xaa, 0xaa, 0x44,
- 0x00, 0x00, 0x44, 0x28, 0x10, 0x10, 0x28, 0x44,
- 0x00, 0x28, 0x28, 0x28, 0x10, 0x10, 0x10, 0x10,
- 0x00, 0x00, 0x3c, 0x04, 0x08, 0x10, 0x20, 0x3c,
- 0x00, 0x08, 0x10, 0x10, 0x20, 0x10, 0x10, 0x08,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
- 0x00, 0x10, 0x08, 0x08, 0x04, 0x08, 0x08, 0x10,
- 0x00, 0x00, 0x00, 0x60, 0x92, 0x0c, 0x00, 0x00,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-
-
-sFONT Font16x24 = {
- ASCII16x24_Table,
- 16, /* Width */
- 24, /* Height */
-};
-
-sFONT Font12x12 = {
- ASCII12x12_Table,
- 12, /* Width */
- 12, /* Height */
-};
-
-sFONT Font8x12 = {
- ASCII8x12_Table,
- 8, /* Width */
- 12, /* Height */
-};
-
-
-sFONT Font8x8 = {
- ASCII8x8_Table,
- 8, /* Width */
- 8, /* Height */
-};
-
-/**
- * @}
- */
-
-
-/** @defgroup FONTS_Private_Function_Prototypes
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup FONTS_Private_Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/Common/fonts.h b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/Common/fonts.h
deleted file mode 100644
index 00fa116..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/Common/fonts.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/**
- ******************************************************************************
- * @file fonts.h
- * @author MCD Application Team
- * @version V4.4.0RC1
- * @date 07/02/2010
- * @brief Header for fonts.c
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __FONTS_H
-#define __FONTS_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include <stdint.h>
-
-/** @addtogroup Utilities
- * @{
- */
-
-/** @addtogroup STM32_EVAL
- * @{
- */
-
-/** @addtogroup Common
- * @{
- */
-
-/** @addtogroup FONTS
- * @{
- */
-
-/** @defgroup FONTS_Exported_Types
- * @{
- */
-typedef struct _tFont
-{
- const uint16_t *table;
- uint16_t Width;
- uint16_t Height;
-
-} sFONT;
-
-extern sFONT Font16x24;
-extern sFONT Font12x12;
-extern sFONT Font8x12;
-extern sFONT Font8x8;
-
-/**
- * @}
- */
-
-/** @defgroup FONTS_Exported_Constants
- * @{
- */
-#define LINE(x) ((x) * (((sFONT *)LCD_GetFont())->Height))
-
-/**
- * @}
- */
-
-/** @defgroup FONTS_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup FONTS_Exported_Functions
- * @{
- */
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __FONTS_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.c b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.c
deleted file mode 100644
index 1f087a7..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.c
+++ /dev/null
@@ -1,584 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l152_eval.c
- * @author MCD Application Team
- * @version V4.4.0RC1
- * @date 07/02/2010
- * @brief This file provides
- * - set of firmware functions to manage Leds, push-button and COM ports
- * - low level initialization functions for SD card (on SPI) and
- * temperature sensor (LM75)
- * available on STM32L152-EVAL evaluation board from STMicroelectronics.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l152_eval.h"
-#include "stm32l1xx_spi.h"
-#include "stm32l1xx_i2c.h"
-
-/** @addtogroup Utilities
- * @{
- */
-
-/** @addtogroup STM32_EVAL
- * @{
- */
-
-/** @addtogroup STM32L152_EVAL
- * @{
- */
-
-/** @defgroup STM32L152_EVAL_LOW_LEVEL
- * @brief This file provides firmware functions to manage Leds, push-buttons,
- * COM ports, SD card on SPI and temperature sensor (LM75) available on
- * STM32L152-EVAL evaluation board from STMicroelectronics.
- * @{
- */
-
-/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Variables
- * @{
- */
-GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
- LED4_GPIO_PORT};
-const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,
- LED4_PIN};
-const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
- LED4_GPIO_CLK};
-
-GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT,
- KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT,
- LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT,
- DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT};
-
-const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN,
- KEY_BUTTON_PIN, RIGHT_BUTTON_PIN,
- LEFT_BUTTON_PIN, UP_BUTTON_PIN,
- DOWN_BUTTON_PIN, SEL_BUTTON_PIN};
-
-const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK,
- KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK,
- LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK,
- DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK};
-
-const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE,
- TAMPER_BUTTON_EXTI_LINE,
- KEY_BUTTON_EXTI_LINE,
- RIGHT_BUTTON_EXTI_LINE,
- LEFT_BUTTON_EXTI_LINE,
- UP_BUTTON_EXTI_LINE,
- DOWN_BUTTON_EXTI_LINE,
- SEL_BUTTON_EXTI_LINE};
-
-const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE,
- TAMPER_BUTTON_EXTI_PORT_SOURCE,
- KEY_BUTTON_EXTI_PORT_SOURCE,
- RIGHT_BUTTON_EXTI_PORT_SOURCE,
- LEFT_BUTTON_EXTI_PORT_SOURCE,
- UP_BUTTON_EXTI_PORT_SOURCE,
- DOWN_BUTTON_EXTI_PORT_SOURCE,
- SEL_BUTTON_EXTI_PORT_SOURCE};
-
-const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE,
- TAMPER_BUTTON_EXTI_PIN_SOURCE,
- KEY_BUTTON_EXTI_PIN_SOURCE,
- RIGHT_BUTTON_EXTI_PIN_SOURCE,
- LEFT_BUTTON_EXTI_PIN_SOURCE,
- UP_BUTTON_EXTI_PIN_SOURCE,
- DOWN_BUTTON_EXTI_PIN_SOURCE,
- SEL_BUTTON_EXTI_PIN_SOURCE};
-
-const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn,
- KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn,
- LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,
- DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn};
-
-USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2};
-
-GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT};
-
-GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT};
-
-const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK};
-
-const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK};
-
-const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK};
-
-const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN};
-
-const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN};
-
-const uint16_t COM_TX_PIN_SOURCE[COMn] = {EVAL_COM1_TX_SOURCE, EVAL_COM2_TX_SOURCE};
-
-const uint16_t COM_RX_PIN_SOURCE[COMn] = {EVAL_COM1_RX_SOURCE, EVAL_COM2_RX_SOURCE};
-
-const uint16_t COM_TX_AF[COMn] = {EVAL_COM1_TX_AF, EVAL_COM2_TX_AF};
-
-const uint16_t COM_RX_AF[COMn] = {EVAL_COM1_RX_AF, EVAL_COM2_RX_AF};
-
-/**
- * @}
- */
-
-
-/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Functions
- * @{
- */
-
-/**
- * @brief Configures LED GPIO.
- * @param Led: Specifies the Led to be configured.
- * This parameter can be one of following parameters:
- * @arg LED1
- * @arg LED2
- * @arg LED3
- * @arg LED4
- * @retval None
- */
-void STM_EVAL_LEDInit(Led_TypeDef Led)
-{
- GPIO_InitTypeDef GPIO_InitStructure;
-
- /* Enable the GPIO_LED Clock */
- RCC_AHBPeriphClockCmd(GPIO_CLK[Led], ENABLE);
-
- /* Configure the GPIO_LED pin */
- GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
- GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
- GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led];
-}
-
-/**
- * @brief Turns selected LED On.
- * @param Led: Specifies the Led to be set on.
- * This parameter can be one of following parameters:
- * @arg LED1
- * @arg LED2
- * @arg LED3
- * @arg LED4
- * @retval None
- */
-void STM_EVAL_LEDOn(Led_TypeDef Led)
-{
- GPIO_PORT[Led]->BSRRH = GPIO_PIN[Led];
-}
-
-/**
- * @brief Turns selected LED Off.
- * @param Led: Specifies the Led to be set off.
- * This parameter can be one of following parameters:
- * @arg LED1
- * @arg LED2
- * @arg LED3
- * @arg LED4
- * @retval None
- */
-void STM_EVAL_LEDOff(Led_TypeDef Led)
-{
- GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led];
-}
-
-/**
- * @brief Toggles the selected LED.
- * @param Led: Specifies the Led to be toggled.
- * This parameter can be one of following parameters:
- * @arg LED1
- * @arg LED2
- * @arg LED3
- * @arg LED4
- * @retval None
- */
-void STM_EVAL_LEDToggle(Led_TypeDef Led)
-{
- GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
-}
-
-/**
- * @brief Configures Button GPIO and EXTI Line.
- * @param Button: Specifies the Button to be configured.
- * This parameter can be one of following parameters:
- * @arg BUTTON_WAKEUP: Wakeup Push Button
- * @arg BUTTON_TAMPER: Tamper Push Button
- * @arg BUTTON_KEY: Key Push Button
- * @arg BUTTON_RIGHT: Joystick Right Push Button
- * @arg BUTTON_LEFT: Joystick Left Push Button
- * @arg BUTTON_UP: Joystick Up Push Button
- * @arg BUTTON_DOWN: Joystick Down Push Button
- * @arg BUTTON_SEL: Joystick Sel Push Button
- * @param Button_Mode: Specifies Button mode.
- * This parameter can be one of following parameters:
- * @arg BUTTON_MODE_GPIO: Button will be used as simple IO
- * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
- * generation capability
- * @retval None
- */
-void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
-{
- GPIO_InitTypeDef GPIO_InitStructure;
- EXTI_InitTypeDef EXTI_InitStructure;
- NVIC_InitTypeDef NVIC_InitStructure;
-
- /* Enable the BUTTON Clock */
- RCC_AHBPeriphClockCmd(BUTTON_CLK[Button], ENABLE);
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
-
- /* Configure Button pin as input */
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
- GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
-
-
- if (Button_Mode == BUTTON_MODE_EXTI)
- {
- /* Connect Button EXTI Line to Button GPIO Pin */
- SYSCFG_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
-
- /* Configure Button EXTI line */
- EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
- EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
-
- if((Button != BUTTON_WAKEUP) && (Button != BUTTON_KEY) && (Button != BUTTON_TAMPER))
- {
- EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
- }
- else
- {
- EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
- }
- EXTI_InitStructure.EXTI_LineCmd = ENABLE;
- EXTI_Init(&EXTI_InitStructure);
-
- /* Enable and set Button EXTI Interrupt to the lowest priority */
- NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-
- NVIC_Init(&NVIC_InitStructure);
- }
-}
-
-/**
- * @brief Returns the selected Button state.
- * @param Button: Specifies the Button to be checked.
- * This parameter can be one of following parameters:
- * @arg BUTTON_WAKEUP: Wakeup Push Button
- * @arg BUTTON_TAMPER: Tamper Push Button
- * @arg BUTTON_KEY: Key Push Button
- * @arg BUTTON_RIGHT: Joystick Right Push Button
- * @arg BUTTON_LEFT: Joystick Left Push Button
- * @arg BUTTON_UP: Joystick Up Push Button
- * @arg BUTTON_DOWN: Joystick Down Push Button
- * @arg BUTTON_SEL: Joystick Sel Push Button
- * @retval The Button GPIO pin value.
- */
-uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
-{
- return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
-}
-
-
-/**
- * @brief Configures COM port.
- * @param COM: Specifies the COM port to be configured.
- * This parameter can be one of following parameters:
- * @arg COM1
- * @arg COM2
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that
- * contains the configuration information for the specified USART peripheral.
- * @retval None
- */
-void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
-{
- GPIO_InitTypeDef GPIO_InitStructure;
-
- /* Enable GPIO clock */
- RCC_AHBPeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM], ENABLE);
-
- /* Enable UART clock */
- RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
-
- /* Connect PXx to USARTx_Tx*/
- GPIO_PinAFConfig(COM_TX_PORT[COM], COM_TX_PIN_SOURCE[COM], COM_TX_AF[COM]);
-
- /* Connect PXx to USARTx_Rx*/
- GPIO_PinAFConfig(COM_RX_PORT[COM], COM_RX_PIN_SOURCE[COM], COM_RX_AF[COM]);
-
- /* Configure USART Tx as alternate function push-pull */
- GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
- GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);
-
- /* Configure USART Rx as input floating */
- GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];
- GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);
-
- /* USART configuration */
- USART_Init(COM_USART[COM], USART_InitStruct);
-
- /* Enable USART */
- USART_Cmd(COM_USART[COM], ENABLE);
-}
-
-/**
- * @brief DeInitializes the SPI interface.
- * @param None
- * @retval None
- */
-void SD_LowLevel_DeInit(void)
-{
- GPIO_InitTypeDef GPIO_InitStructure;
-
- SPI_Cmd(SD_SPI, DISABLE); /*!< SD_SPI disable */
- SPI_DeInit(SD_SPI); /*!< DeInitializes the SD_SPI */
-
- /*!< SD_SPI Periph clock disable */
- RCC_APB1PeriphClockCmd(SD_SPI_CLK, DISABLE);
-
- /*!< Configure SD_SPI pins: SCK */
- GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
- /*!< Configure SD_SPI pins: MISO */
- GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
- GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-
- /*!< Configure SD_SPI pins: MOSI */
- GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
- GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
- /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
- GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
- GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
-
- /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
- GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
- GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
- * @brief Initializes the SD Card and put it into StandBy State (Ready for
- * data transfer).
- * @param None
- * @retval None
- */
-void SD_LowLevel_Init(void)
-{
- GPIO_InitTypeDef GPIO_InitStructure;
- SPI_InitTypeDef SPI_InitStructure;
-
- /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO
- and SD_SPI_SCK_GPIO Periph clock enable */
- RCC_AHBPeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK |
- SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE);
-
- /*!< SD_SPI Periph clock enable */
- RCC_APB1PeriphClockCmd(SD_SPI_CLK, ENABLE);
-
- /*!< Configure SD_SPI pins: SCK */
- GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
- GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
- /*!< Configure SD_SPI pins: MISO */
- GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
- GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-
- /*!< Configure SD_SPI pins: MOSI */
- GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
- GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
- /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
- GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
- GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
-
- /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
- GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
- GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
-
- /* Connect PXx to SD_SPI_SCK */
- GPIO_PinAFConfig(SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_SOURCE, SD_SPI_SCK_AF);
-
- /* Connect PXx to SD_SPI_MISO */
- GPIO_PinAFConfig(SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_SOURCE, SD_SPI_MISO_AF);
-
- /* Connect PXx to SD_SPI_MOSI */
- GPIO_PinAFConfig(SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_SOURCE, SD_SPI_MOSI_AF);
-
- /*!< SD_SPI Config */
- SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
- SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
- SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
- SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
- SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
- SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
- SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
-
- SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
- SPI_InitStructure.SPI_CRCPolynomial = 7;
- SPI_Init(SD_SPI, &SPI_InitStructure);
-
- SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */
-}
-
-/**
- * @brief DeInitializes the LM75_I2C.
- * @param None
- * @retval None
- */
-void LM75_LowLevel_DeInit(void)
-{
- GPIO_InitTypeDef GPIO_InitStructure;
-
- /*!< Disable LM75_I2C */
- I2C_Cmd(LM75_I2C, DISABLE);
-
- /*!< DeInitializes the LM75_I2C */
- I2C_DeInit(LM75_I2C);
-
- /*!< LM75_I2C Periph clock disable */
- RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE);
-
- /*!< Configure LM75_I2C pins: SCL */
- GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
-
- /*!< Configure LM75_I2C pins: SDA */
- GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
- GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
-
- /*!< Configure LM75_I2C pin: SMBUS ALERT */
- GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
- GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
- * @brief Initializes the LM75_I2C.
- * @param None
- * @retval None
- */
-void LM75_LowLevel_Init(void)
-{
- GPIO_InitTypeDef GPIO_InitStructure;
-
- /*!< LM75_I2C Periph clock enable */
- RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE);
-
- /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK
- and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */
- RCC_AHBPeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK |
- LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE);
-
- /*!< Configure LM75_I2C pins: SCL */
- GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
-
- /*!< Configure LM75_I2C pins: SDA */
- GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
- GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
-
- /*!< Configure LM75_I2C pin: SMBUS ALERT */
- GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
- GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
-
-
- /* Connect PXx to I2C_SCL */
- GPIO_PinAFConfig(LM75_I2C_SCL_GPIO_PORT, LM75_I2C_SCL_SOURCE, LM75_I2C_SCL_AF);
-
- /* Connect PXx to I2C_SDA */
- GPIO_PinAFConfig(LM75_I2C_SDA_GPIO_PORT, LM75_I2C_SDA_SOURCE, LM75_I2C_SDA_AF);
-
- /* Connect PXx to I2C_SMBUSALER */
- GPIO_PinAFConfig(LM75_I2C_SMBUSALERT_GPIO_PORT, LM75_I2C_SMBUSALERT_SOURCE, LM75_I2C_SMBUSALERT_AF);
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.h b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.h
deleted file mode 100644
index 56df0fb..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l152_eval.h
- * @author MCD Application Team
- * @version V4.4.0RC1
- * @date 07/02/2010
- * @brief This file contains definitions for STM32L152_EVAL's Leds, push-buttons
- * and COM ports hardware resources.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L152_EVAL_H
-#define __STM32L152_EVAL_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval.h"
-
-/** @addtogroup Utilities
- * @{
- */
-
-/** @addtogroup STM32_EVAL
- * @{
- */
-
-/** @addtogroup STM32L152_EVAL
- * @{
- */
-
-/** @addtogroup STM32L152_EVAL_LOW_LEVEL
- * @{
- */
-
-/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Types
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Constants
- * @{
- */
-
-/** @addtogroup STM32L152_EVAL_LOW_LEVEL_LED
- * @{
- */
-#define LEDn 4
-
-#define LED1_PIN GPIO_Pin_0
-#define LED1_GPIO_PORT GPIOD
-#define LED1_GPIO_CLK RCC_AHBPeriph_GPIOD
-
-#define LED2_PIN GPIO_Pin_1
-#define LED2_GPIO_PORT GPIOD
-#define LED2_GPIO_CLK RCC_AHBPeriph_GPIOD
-
-#define LED3_PIN GPIO_Pin_4
-#define LED3_GPIO_PORT GPIOD
-#define LED3_GPIO_CLK RCC_AHBPeriph_GPIOD
-
-#define LED4_PIN GPIO_Pin_5
-#define LED4_GPIO_PORT GPIOD
-#define LED4_GPIO_CLK RCC_AHBPeriph_GPIOD
-
-/**
- * @}
- */
-
-/** @addtogroup STM32L152_EVAL_LOW_LEVEL_BUTTON
- * @{
- */
-#define BUTTONn 8
-
-/**
- * @brief Wakeup push-button
- */
-#define WAKEUP_BUTTON_PIN GPIO_Pin_13
-#define WAKEUP_BUTTON_GPIO_PORT GPIOC
-#define WAKEUP_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOC
-#define WAKEUP_BUTTON_EXTI_LINE EXTI_Line13
-#define WAKEUP_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOC
-#define WAKEUP_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource13
-#define WAKEUP_BUTTON_EXTI_IRQn EXTI15_10_IRQn
-
-/**
- * @brief Tamper push-button
- */
-#define TAMPER_BUTTON_PIN GPIO_Pin_13
-#define TAMPER_BUTTON_GPIO_PORT GPIOC
-#define TAMPER_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOC
-#define TAMPER_BUTTON_EXTI_LINE EXTI_Line13
-#define TAMPER_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOC
-#define TAMPER_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource13
-#define TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn
-
-/**
- * @brief Key push-button
- */
-#define KEY_BUTTON_PIN GPIO_Pin_13
-#define KEY_BUTTON_GPIO_PORT GPIOC
-#define KEY_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOC
-#define KEY_BUTTON_EXTI_LINE EXTI_Line13
-#define KEY_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOC
-#define KEY_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource13
-#define KEY_BUTTON_EXTI_IRQn EXTI15_10_IRQn
-
-/**
- * @brief Joystick Right push-button
- */
-#define RIGHT_BUTTON_PIN GPIO_Pin_11
-#define RIGHT_BUTTON_GPIO_PORT GPIOE
-#define RIGHT_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE
-#define RIGHT_BUTTON_EXTI_LINE EXTI_Line11
-#define RIGHT_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE
-#define RIGHT_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource11
-#define RIGHT_BUTTON_EXTI_IRQn EXTI15_10_IRQn
-
-/**
- * @brief Joystick Left push-button
- */
-#define LEFT_BUTTON_PIN GPIO_Pin_12
-#define LEFT_BUTTON_GPIO_PORT GPIOE
-#define LEFT_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE
-#define LEFT_BUTTON_EXTI_LINE EXTI_Line12
-#define LEFT_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE
-#define LEFT_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource12
-#define LEFT_BUTTON_EXTI_IRQn EXTI15_10_IRQn
-
-/**
- * @brief Joystick Up push-button
- */
-#define UP_BUTTON_PIN GPIO_Pin_9
-#define UP_BUTTON_GPIO_PORT GPIOE
-#define UP_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE
-#define UP_BUTTON_EXTI_LINE EXTI_Line9
-#define UP_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE
-#define UP_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource9
-#define UP_BUTTON_EXTI_IRQn EXTI9_5_IRQn
-
-/**
- * @brief Joystick Down push-button
- */
-#define DOWN_BUTTON_PIN GPIO_Pin_10
-#define DOWN_BUTTON_GPIO_PORT GPIOE
-#define DOWN_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE
-#define DOWN_BUTTON_EXTI_LINE EXTI_Line10
-#define DOWN_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE
-#define DOWN_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource10
-#define DOWN_BUTTON_EXTI_IRQn EXTI15_10_IRQn
-
-/**
- * @brief Joystick Sel push-button
- */
-#define SEL_BUTTON_PIN GPIO_Pin_8
-#define SEL_BUTTON_GPIO_PORT GPIOE
-#define SEL_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE
-#define SEL_BUTTON_EXTI_LINE EXTI_Line8
-#define SEL_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE
-#define SEL_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource8
-#define SEL_BUTTON_EXTI_IRQn EXTI9_5_IRQn
-
-/**
- * @}
- */
-
-/** @addtogroup STM32L152_EVAL_LOW_LEVEL_COM
- * @{
- */
-#define COMn 2
-
-/**
- * @brief Definition for COM port1, connected to USART2
- */
-#define EVAL_COM1 USART2
-#define EVAL_COM1_CLK RCC_APB1Periph_USART2
-#define EVAL_COM1_TX_PIN GPIO_Pin_5
-#define EVAL_COM1_TX_GPIO_PORT GPIOD
-#define EVAL_COM1_TX_GPIO_CLK RCC_AHBPeriph_GPIOD
-#define EVAL_COM1_TX_SOURCE GPIO_PinSource5
-#define EVAL_COM1_TX_AF GPIO_AF_USART2
-#define EVAL_COM1_RX_PIN GPIO_Pin_6
-#define EVAL_COM1_RX_GPIO_PORT GPIOD
-#define EVAL_COM1_RX_GPIO_CLK RCC_AHBPeriph_GPIOD
-#define EVAL_COM1_RX_SOURCE GPIO_PinSource6
-#define EVAL_COM1_RX_AF GPIO_AF_USART2
-#define EVAL_COM1_IRQn USART2_IRQn
-
-/**
- * @brief Definition for COM port2, connected to USART3
- */
-#define EVAL_COM2 USART3
-#define EVAL_COM2_CLK RCC_APB1Periph_USART3
-
-#define EVAL_COM2_TX_PIN GPIO_Pin_10
-#define EVAL_COM2_TX_GPIO_PORT GPIOC
-#define EVAL_COM2_TX_GPIO_CLK RCC_AHBPeriph_GPIOC
-#define EVAL_COM2_TX_SOURCE GPIO_PinSource10
-#define EVAL_COM2_TX_AF GPIO_AF_USART3
-
-#define EVAL_COM2_RX_PIN GPIO_Pin_11
-#define EVAL_COM2_RX_GPIO_PORT GPIOC
-#define EVAL_COM2_RX_GPIO_CLK RCC_AHBPeriph_GPIOC
-#define EVAL_COM2_RX_SOURCE GPIO_PinSource11
-#define EVAL_COM2_RX_AF GPIO_AF_USART3
-#define EVAL_COM2_IRQn USART3_IRQn
-
-/**
- * @}
- */
-
-/** @addtogroup STM32L152_EVAL_LOW_LEVEL_SD_FLASH
- * @{
- */
-/**
- * @brief SD Card SPI Interface
- */
-#define SD_SPI SPI2
-#define SD_SPI_CLK RCC_APB1Periph_SPI2
-#define SD_SPI_SCK_PIN GPIO_Pin_13 /* PB.13 */
-#define SD_SPI_SCK_GPIO_PORT GPIOB /* GPIOB */
-#define SD_SPI_SCK_GPIO_CLK RCC_AHBPeriph_GPIOB
-#define SD_SPI_SCK_SOURCE GPIO_PinSource13
-#define SD_SPI_SCK_AF GPIO_AF_SPI2
-#define SD_SPI_MISO_PIN GPIO_Pin_14 /* PB.14 */
-#define SD_SPI_MISO_GPIO_PORT GPIOB /* GPIOB */
-#define SD_SPI_MISO_GPIO_CLK RCC_AHBPeriph_GPIOB
-#define SD_SPI_MISO_SOURCE GPIO_PinSource14
-#define SD_SPI_MISO_AF GPIO_AF_SPI2
-#define SD_SPI_MOSI_PIN GPIO_Pin_15 /* PB.15 */
-#define SD_SPI_MOSI_GPIO_PORT GPIOB /* GPIOB */
-#define SD_SPI_MOSI_GPIO_CLK RCC_AHBPeriph_GPIOB
-#define SD_SPI_MOSI_SOURCE GPIO_PinSource15
-#define SD_SPI_MOSI_AF GPIO_AF_SPI2
-#define SD_CS_PIN GPIO_Pin_7 /* PD.07 */
-#define SD_CS_GPIO_PORT GPIOD /* GPIOD */
-#define SD_CS_GPIO_CLK RCC_AHBPeriph_GPIOD
-#define SD_DETECT_PIN GPIO_Pin_7 /* PE.07 */
-#define SD_DETECT_GPIO_PORT GPIOE /* GPIOE */
-#define SD_DETECT_GPIO_CLK RCC_AHBPeriph_GPIOE
-/**
- * @}
- */
-
-/** @addtogroup STM32L152_EVAL_LOW_LEVEL_TSENSOR_I2C
- * @{
- */
-/**
- * @brief LM75 Temperature Sensor I2C Interface pins
- */
-#define LM75_I2C I2C1
-#define LM75_I2C_CLK RCC_APB1Periph_I2C1
-#define LM75_I2C_SCL_PIN GPIO_Pin_6 /* PB.06 */
-#define LM75_I2C_SCL_GPIO_PORT GPIOB /* GPIOB */
-#define LM75_I2C_SCL_GPIO_CLK RCC_AHBPeriph_GPIOB
-#define LM75_I2C_SCL_SOURCE GPIO_PinSource6
-#define LM75_I2C_SCL_AF GPIO_AF_I2C1
-#define LM75_I2C_SDA_PIN GPIO_Pin_7 /* PB.07 */
-#define LM75_I2C_SDA_GPIO_PORT GPIOB /* GPIOB */
-#define LM75_I2C_SDA_GPIO_CLK RCC_AHBPeriph_GPIOB
-#define LM75_I2C_SDA_SOURCE GPIO_PinSource7
-#define LM75_I2C_SDA_AF GPIO_AF_I2C1
-#define LM75_I2C_SMBUSALERT_PIN GPIO_Pin_5 /* PB.05 */
-#define LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB /* GPIOB */
-#define LM75_I2C_SMBUSALERT_GPIO_CLK RCC_AHBPeriph_GPIOB
-#define LM75_I2C_SMBUSALERT_SOURCE GPIO_PinSource5
-#define LM75_I2C_SMBUSALERT_AF GPIO_AF_I2C1
-/**
- * @}
- */
-/**
- * @}
- */
-
-/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Functions
- * @{
- */
-void STM_EVAL_LEDInit(Led_TypeDef Led);
-void STM_EVAL_LEDOn(Led_TypeDef Led);
-void STM_EVAL_LEDOff(Led_TypeDef Led);
-void STM_EVAL_LEDToggle(Led_TypeDef Led);
-void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
-uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
-void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct);
-void SD_LowLevel_DeInit(void);
-void SD_LowLevel_Init(void);
-void LM75_LowLevel_DeInit(void);
-void LM75_LowLevel_Init(void);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L152_EVAL_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.c b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.c
deleted file mode 100644
index 8c3f05a..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.c
+++ /dev/null
@@ -1,1528 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l152_eval_lcd.c
- * @author MCD Application Team
- * @version V4.4.0RC1
- * @date 07/02/2010
- * @brief This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320),
- * AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module
- * of STM32L152-EVAL board.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l152_eval_lcd.h"
-#include "../Common/fonts.c"
-
-/** @addtogroup Utilities
- * @{
- */
-
-/** @addtogroup STM32_EVAL
- * @{
- */
-
-/** @addtogroup STM32L152_EVAL
- * @{
- */
-
-/** @defgroup STM32L152_EVAL_LCD
- * @brief This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320),
- * AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module
- * of STM32L152-EVAL board.
- * @{
- */
-
-/** @defgroup STM32L152_EVAL_LCD_Private_Types
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup STM32L152_EVAL_LCD_Private_Defines
- * @{
- */
-#define LCD_ILI9320 0x9320
-#define LCD_SPFD5408 0x5408
-#define START_BYTE 0x70
-#define SET_INDEX 0x00
-#define READ_STATUS 0x01
-#define LCD_WRITE_REG 0x02
-#define LCD_READ_REG 0x03
-#define MAX_POLY_CORNERS 200
-#define POLY_Y(Z) ((int32_t)((Points + Z)->X))
-#define POLY_X(Z) ((int32_t)((Points + Z)->Y))
-/**
- * @}
- */
-
-/** @defgroup STM32L152_EVAL_LCD_Private_Macros
- * @{
- */
-#define ABS(X) ((X) > 0 ? (X) : -(X))
-/**
- * @}
- */
-
-/** @defgroup STM32L152_EVAL_LCD_Private_Variables
- * @{
- */
-static sFONT *LCD_Currentfonts;
-/* Global variables to set the written text color */
-static __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF;
-static __IO uint32_t LCDType = LCD_SPFD5408;
-/**
- * @}
- */
-
-/** @defgroup STM32L152_EVAL_LCD_Private_Function_Prototypes
- * @{
- */
-#ifndef USE_Delay
-static void delay(__IO uint32_t nCount);
-#endif /* USE_Delay*/
-
-static void PutPixel(int16_t x, int16_t y);
-static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed);
-
-/**
- * @}
- */
-
-/** @defgroup STM32L152_EVAL_LCD_Private_Functions
- * @{
- */
-
-/**
- * @brief DeInitializes the LCD.
- * @param None
- * @retval None
- */
-void STM32L152_LCD_DeInit(void)
-{
- GPIO_InitTypeDef GPIO_InitStructure;
-
- /*!< LCD Display Off */
- LCD_DisplayOff();
-
- /*!< LCD_SPI disable */
- SPI_Cmd(LCD_SPI, DISABLE);
-
- /*!< LCD_SPI DeInit */
- SPI_DeInit(LCD_SPI);
-
- /*!< Disable SPI clock */
- RCC_APB1PeriphClockCmd(LCD_SPI_CLK, DISABLE);
-
- /* Configure NCS in Output Push-Pull mode */
- GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
-
- /* Configure SPI pins: SCK, MISO and MOSI */
- GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;
- GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
- GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;
- GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-
- GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;
- GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
- * @brief Setups the LCD.
- * @param None
- * @retval None
- */
-void LCD_Setup(void)
-{
-/* Configure the LCD Control pins --------------------------------------------*/
- LCD_CtrlLinesConfig();
-
-/* Configure the LCD_SPI interface ----------------------------------------------*/
- LCD_SPIConfig();
-
- if(LCDType == LCD_SPFD5408)
- {
- /* Start Initial Sequence --------------------------------------------------*/
- LCD_WriteReg(LCD_REG_227, 0x3008); /* Set internal timing */
- LCD_WriteReg(LCD_REG_231, 0x0012); /* Set internal timing */
- LCD_WriteReg(LCD_REG_239, 0x1231); /* Set internal timing */
- LCD_WriteReg(LCD_REG_1, 0x0100); /* Set SS and SM bit */
- LCD_WriteReg(LCD_REG_2, 0x0700); /* Set 1 line inversion */
- LCD_WriteReg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */
- LCD_WriteReg(LCD_REG_4, 0x0000); /* Resize register */
- LCD_WriteReg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */
- LCD_WriteReg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */
- LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
- LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
- LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
- LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
- /* Power On sequence -------------------------------------------------------*/
- LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
- LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
- LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
- LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
- _delay_(20); /* Dis-charge capacitor power voltage (200ms) */
- LCD_WriteReg(LCD_REG_17, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */
- _delay_(5); /* Delay 50 ms */
- LCD_WriteReg(LCD_REG_16, 0x12B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
- _delay_(5); /* Delay 50 ms */
- LCD_WriteReg(LCD_REG_18, 0x01BD); /* External reference voltage= Vci */
- _delay_(5); /* Delay 50 ms */
- LCD_WriteReg(LCD_REG_19, 0x1400); /* VDV[4:0] for VCOM amplitude */
- LCD_WriteReg(LCD_REG_41, 0x000E); /* VCM[4:0] for VCOMH */
- _delay_(5); /* Delay 50 ms */
- LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
- LCD_WriteReg(LCD_REG_33, 0x013F); /* GRAM Vertical Address */
- /* Adjust the Gamma Curve --------------------------------------------------*/
- LCD_WriteReg(LCD_REG_48, 0x0007);
- LCD_WriteReg(LCD_REG_49, 0x0302);
- LCD_WriteReg(LCD_REG_50, 0x0105);
- LCD_WriteReg(LCD_REG_53, 0x0206);
- LCD_WriteReg(LCD_REG_54, 0x0808);
- LCD_WriteReg(LCD_REG_55, 0x0206);
- LCD_WriteReg(LCD_REG_56, 0x0504);
- LCD_WriteReg(LCD_REG_57, 0x0007);
- LCD_WriteReg(LCD_REG_60, 0x0105);
- LCD_WriteReg(LCD_REG_61, 0x0808);
- /* Set GRAM area -----------------------------------------------------------*/
- LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
- LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
- LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
- LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
- LCD_WriteReg(LCD_REG_96, 0xA700); /* Gate Scan Line */
- LCD_WriteReg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */
- LCD_WriteReg(LCD_REG_106, 0x0000); /* Set scrolling line */
- /* Partial Display Control -------------------------------------------------*/
- LCD_WriteReg(LCD_REG_128, 0x0000);
- LCD_WriteReg(LCD_REG_129, 0x0000);
- LCD_WriteReg(LCD_REG_130, 0x0000);
- LCD_WriteReg(LCD_REG_131, 0x0000);
- LCD_WriteReg(LCD_REG_132, 0x0000);
- LCD_WriteReg(LCD_REG_133, 0x0000);
- /* Panel Control -----------------------------------------------------------*/
- LCD_WriteReg(LCD_REG_144, 0x0010);
- LCD_WriteReg(LCD_REG_146, 0x0000);
- LCD_WriteReg(LCD_REG_147, 0x0003);
- LCD_WriteReg(LCD_REG_149, 0x0110);
- LCD_WriteReg(LCD_REG_151, 0x0000);
- LCD_WriteReg(LCD_REG_152, 0x0000);
- /* Set GRAM write direction and BGR = 1
- I/D=01 (Horizontal : increment, Vertical : decrement)
- AM=1 (address is updated in vertical writing direction) */
- LCD_WriteReg(LCD_REG_3, 0x1018);
- LCD_WriteReg(LCD_REG_7, 0x0112); /* 262K color and display ON */
- }
- else if(LCDType == LCD_ILI9320)
- {
- _delay_(5); /* Delay 50 ms */
- /* Start Initial Sequence ------------------------------------------------*/
- LCD_WriteReg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */
- LCD_WriteReg(LCD_REG_0, 0x0001); /* Start internal OSC. */
- LCD_WriteReg(LCD_REG_1, 0x0100); /* set SS and SM bit */
- LCD_WriteReg(LCD_REG_2, 0x0700); /* set 1 line inversion */
- LCD_WriteReg(LCD_REG_3, 0x1030); /* set GRAM write direction and BGR=1. */
- LCD_WriteReg(LCD_REG_4, 0x0000); /* Resize register */
- LCD_WriteReg(LCD_REG_8, 0x0202); /* set the back porch and front porch */
- LCD_WriteReg(LCD_REG_9, 0x0000); /* set non-display area refresh cycle ISC[3:0] */
- LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
- LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
- LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
- LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
- /* Power On sequence -----------------------------------------------------*/
- LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
- LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
- LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
- LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
- _delay_(20); /* Dis-charge capacitor power voltage (200ms) */
- LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
- LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
- _delay_(5); /* Delay 50 ms */
- LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
- _delay_(5); /* Delay 50 ms */
- LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
- LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
- _delay_(5); /* Delay 50 ms */
- LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
- LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
- /* Adjust the Gamma Curve ------------------------------------------------*/
- LCD_WriteReg(LCD_REG_48, 0x0006);
- LCD_WriteReg(LCD_REG_49, 0x0101);
- LCD_WriteReg(LCD_REG_50, 0x0003);
- LCD_WriteReg(LCD_REG_53, 0x0106);
- LCD_WriteReg(LCD_REG_54, 0x0b02);
- LCD_WriteReg(LCD_REG_55, 0x0302);
- LCD_WriteReg(LCD_REG_56, 0x0707);
- LCD_WriteReg(LCD_REG_57, 0x0007);
- LCD_WriteReg(LCD_REG_60, 0x0600);
- LCD_WriteReg(LCD_REG_61, 0x020b);
-
- /* Set GRAM area ---------------------------------------------------------*/
- LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
- LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
- LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
- LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
- LCD_WriteReg(LCD_REG_96, 0x2700); /* Gate Scan Line */
- LCD_WriteReg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */
- LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
- /* Partial Display Control -----------------------------------------------*/
- LCD_WriteReg(LCD_REG_128, 0x0000);
- LCD_WriteReg(LCD_REG_129, 0x0000);
- LCD_WriteReg(LCD_REG_130, 0x0000);
- LCD_WriteReg(LCD_REG_131, 0x0000);
- LCD_WriteReg(LCD_REG_132, 0x0000);
- LCD_WriteReg(LCD_REG_133, 0x0000);
- /* Panel Control ---------------------------------------------------------*/
- LCD_WriteReg(LCD_REG_144, 0x0010);
- LCD_WriteReg(LCD_REG_146, 0x0000);
- LCD_WriteReg(LCD_REG_147, 0x0003);
- LCD_WriteReg(LCD_REG_149, 0x0110);
- LCD_WriteReg(LCD_REG_151, 0x0000);
- LCD_WriteReg(LCD_REG_152, 0x0000);
- /* Set GRAM write direction and BGR = 1 */
- /* I/D=01 (Horizontal : increment, Vertical : decrement) */
- /* AM=1 (address is updated in vertical writing direction) */
- LCD_WriteReg(LCD_REG_3, 0x1018);
- LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
- }
-}
-
-
-/**
- * @brief Initializes the LCD.
- * @param None
- * @retval None
- */
-void STM32L152_LCD_Init(void)
-{
- /* Setups the LCD */
- LCD_Setup();
-
- /* Try to read new LCD controller ID 0x5408 */
- if (LCD_ReadReg(LCD_REG_0) == LCD_SPFD5408)
- {
- LCDType = LCD_SPFD5408;
- }
- else
- {
- LCDType = LCD_ILI9320;
- /* Setups the LCD */
- LCD_Setup();
- }
-
- LCD_SetFont(&LCD_DEFAULT_FONT);
-}
-
-/**
- * @brief Sets the LCD Text and Background colors.
- * @param _TextColor: specifies the Text Color.
- * @param _BackColor: specifies the Background Color.
- * @retval None
- */
-void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor)
-{
- TextColor = _TextColor;
- BackColor = _BackColor;
-}
-
-/**
- * @brief Gets the LCD Text and Background colors.
- * @param _TextColor: pointer to the variable that will contain the Text
- Color.
- * @param _BackColor: pointer to the variable that will contain the Background
- Color.
- * @retval None
- */
-void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
-{
- *_TextColor = TextColor; *_BackColor = BackColor;
-}
-
-/**
- * @brief Sets the Text color.
- * @param Color: specifies the Text color code RGB(5-6-5).
- * @retval None
- */
-void LCD_SetTextColor(__IO uint16_t Color)
-{
- TextColor = Color;
-}
-
-
-/**
- * @brief Sets the Background color.
- * @param Color: specifies the Background color code RGB(5-6-5).
- * @retval None
- */
-void LCD_SetBackColor(__IO uint16_t Color)
-{
- BackColor = Color;
-}
-
-/**
- * @brief Sets the Text Font.
- * @param fonts: specifies the font to be used.
- * @retval None
- */
-void LCD_SetFont(sFONT *fonts)
-{
- LCD_Currentfonts = fonts;
-}
-
-/**
- * @brief Gets the Text Font.
- * @param None.
- * @retval the used font.
- */
-sFONT *LCD_GetFont(void)
-{
- return LCD_Currentfonts;
-}
-
-/**
- * @brief Clears the selected line.
- * @param Line: the Line to be cleared.
- * This parameter can be one of the following values:
- * @arg Linex: where x can be 0..n
- * @retval None
- */
-void LCD_ClearLine(uint8_t Line)
-{
- uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
-
- /* Send the string character by character on lCD */
- while (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width)
- {
- /* Display one character on LCD */
- LCD_DisplayChar(Line, refcolumn, ' ');
- /* Decrement the column position by 16 */
- refcolumn -= LCD_Currentfonts->Width;
- }
-}
-
-
-/**
- * @brief Clears the hole LCD.
- * @param Color: the color of the background.
- * @retval None
- */
-void LCD_Clear(uint16_t Color)
-{
- uint32_t index = 0;
-
- LCD_SetCursor(0x00, 0x013F);
-
- LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-
- for(index = 0; index < 76800; index++)
- {
- LCD_WriteRAM(Color);
- }
-
- LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-
-}
-
-
-/**
- * @brief Sets the cursor position.
- * @param Xpos: specifies the X position.
- * @param Ypos: specifies the Y position.
- * @retval None
- */
-void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos)
-{
- LCD_WriteReg(LCD_REG_32, Xpos);
- LCD_WriteReg(LCD_REG_33, Ypos);
-}
-
-
-/**
- * @brief Draws a character on LCD.
- * @param Xpos: the Line where to display the character shape.
- * @param Ypos: start column address.
- * @param c: pointer to the character data.
- * @retval None
- */
-void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
-{
- uint32_t index = 0, i = 0;
- uint8_t Xaddress = 0;
-
- Xaddress = Xpos;
-
- LCD_SetCursor(Xaddress, Ypos);
-
- for(index = 0; index < LCD_Currentfonts->Height; index++)
- {
- LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-
- for(i = 0; i < LCD_Currentfonts->Width; i++)
- {
- if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))||
- (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 )))
-
- {
- LCD_WriteRAM(BackColor);
- }
- else
- {
- LCD_WriteRAM(TextColor);
- }
- }
-
- LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
- Xaddress++;
- LCD_SetCursor(Xaddress, Ypos);
- }
-}
-
-
-/**
- * @brief Displays one character (16dots width, 24dots height).
- * @param Line: the Line where to display the character shape .
- * This parameter can be one of the following values:
- * @arg Linex: where x can be 0..9
- * @param Column: start column address.
- * @param Ascii: character ascii code, must be between 0x20 and 0x7E.
- * @retval None
- */
-void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii)
-{
- Ascii -= 32;
- LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]);
-}
-
-
-/**
- * @brief Displays a maximum of 20 char on the LCD.
- * @param Line: the Line where to display the character shape .
- * This parameter can be one of the following values:
- * @arg Linex: where x can be 0..9
- * @param *ptr: pointer to string to display on LCD.
- * @retval None
- */
-void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr)
-{
- uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
-
- /* Send the string character by character on lCD */
- while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width))
- {
- /* Display one character on LCD */
- LCD_DisplayChar(Line, refcolumn, *ptr);
- /* Decrement the column position by 16 */
- refcolumn -= LCD_Currentfonts->Width;
- /* Point on the next character */
- ptr++;
- }
-}
-
-
-/**
- * @brief Sets a display window
- * @param Xpos: specifies the X buttom left position.
- * @param Ypos: specifies the Y buttom left position.
- * @param Height: display window height.
- * @param Width: display window width.
- * @retval None
- */
-void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
-{
- /* Horizontal GRAM Start Address */
- if(Xpos >= Height)
- {
- LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1));
- }
- else
- {
- LCD_WriteReg(LCD_REG_80, 0);
- }
- /* Horizontal GRAM End Address */
- LCD_WriteReg(LCD_REG_81, Xpos);
- /* Vertical GRAM Start Address */
- if(Ypos >= Width)
- {
- LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1));
- }
- else
- {
- LCD_WriteReg(LCD_REG_82, 0);
- }
- /* Vertical GRAM End Address */
- LCD_WriteReg(LCD_REG_83, Ypos);
-
- LCD_SetCursor(Xpos, Ypos);
-}
-
-
-/**
- * @brief Disables LCD Window mode.
- * @param None
- * @retval None
- */
-void LCD_WindowModeDisable(void)
-{
- LCD_SetDisplayWindow(239, 0x13F, 240, 320);
- LCD_WriteReg(LCD_REG_3, 0x1018);
-}
-
-/**
- * @brief Displays a line.
- * @param Xpos: specifies the X position.
- * @param Ypos: specifies the Y position.
- * @param Length: line length.
- * @param Direction: line direction.
- * This parameter can be one of the following values: Vertical or Horizontal.
- * @retval None
- */
-void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
-{
- uint32_t i = 0;
-
- LCD_SetCursor(Xpos, Ypos);
-
- if(Direction == LCD_DIR_HORIZONTAL)
- {
- LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-
- for(i = 0; i < Length; i++)
- {
- LCD_WriteRAM(TextColor);
- }
- LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
- }
- else
- {
- for(i = 0; i < Length; i++)
- {
- LCD_WriteRAMWord(TextColor);
- Xpos++;
- LCD_SetCursor(Xpos, Ypos);
- }
- }
-}
-
-
-/**
- * @brief Displays a rectangle.
- * @param Xpos: specifies the X position.
- * @param Ypos: specifies the Y position.
- * @param Height: display rectangle height.
- * @param Width: display rectangle width.
- * @retval None
- */
-void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
-{
- LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
- LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
-
- LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
- LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
-}
-
-
-/**
- * @brief Displays a circle.
- * @param Xpos: specifies the X position.
- * @param Ypos: specifies the Y position.
- * @param Radius
- * @retval None
- */
-void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
-{
- int32_t D;/* Decision Variable */
- uint32_t CurX;/* Current X Value */
- uint32_t CurY;/* Current Y Value */
-
- D = 3 - (Radius << 1);
- CurX = 0;
- CurY = Radius;
-
- while (CurX <= CurY)
- {
- LCD_SetCursor(Xpos + CurX, Ypos + CurY);
- LCD_WriteRAMWord(TextColor);
- LCD_SetCursor(Xpos + CurX, Ypos - CurY);
- LCD_WriteRAMWord(TextColor);
-
- LCD_SetCursor(Xpos - CurX, Ypos + CurY);
- LCD_WriteRAMWord(TextColor);
-
- LCD_SetCursor(Xpos - CurX, Ypos - CurY);
- LCD_WriteRAMWord(TextColor);
-
- LCD_SetCursor(Xpos + CurY, Ypos + CurX);
- LCD_WriteRAMWord(TextColor);
-
- LCD_SetCursor(Xpos + CurY, Ypos - CurX);
- LCD_WriteRAMWord(TextColor);
-
- LCD_SetCursor(Xpos - CurY, Ypos + CurX);
- LCD_WriteRAMWord(TextColor);
-
- LCD_SetCursor(Xpos - CurY, Ypos - CurX);
- LCD_WriteRAMWord(TextColor);
-
- if (D < 0)
- {
- D += (CurX << 2) + 6;
- }
- else
- {
- D += ((CurX - CurY) << 2) + 10;
- CurY--;
- }
- CurX++;
- }
-}
-
-
-/**
- * @brief Displays a monocolor picture.
- * @param Pict: pointer to the picture array.
- * @retval None
- */
-void LCD_DrawMonoPict(const uint32_t *Pict)
-{
- uint32_t index = 0, i = 0;
- LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1));
-
- LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-
- for(index = 0; index < 2400; index++)
- {
- for(i = 0; i < 32; i++)
- {
- if((Pict[index] & (1 << i)) == 0x00)
- {
- LCD_WriteRAM(BackColor);
- }
- else
- {
- LCD_WriteRAM(TextColor);
- }
- }
- }
-
- LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-#ifdef USE_LCD_DrawBMP
-/**
- * @brief Displays a bitmap picture loaded in the SPI Flash.
- * @param BmpAddress: Bmp picture address in the SPI Flash.
- * @retval None
- */
-void LCD_DrawBMP(uint32_t BmpAddress)
-{
- uint32_t i = 0, size = 0;
- /* Read bitmap size */
- SPI_FLASH_BufferRead((uint8_t*)&size, BmpAddress + 2, 4);
- /* get bitmap data address offset */
- SPI_FLASH_BufferRead((uint8_t*)&i, BmpAddress + 10, 4);
-
- size = (size - i)/2;
- SPI_FLASH_StartReadSequence(BmpAddress + i);
- /* Disable SPI1 */
- SPI_Cmd(SPI1, DISABLE);
- /* SPI in 16-bit mode */
- SPI_DataSizeConfig(SPI1, SPI_DataSize_16b);
- /* Enable SPI1 */
- SPI_Cmd(SPI1, ENABLE);
-
- if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
- {
- /* Set GRAM write direction and BGR = 1 */
- /* I/D=00 (Horizontal : decrement, Vertical : decrement) */
- /* AM=1 (address is updated in vertical writing direction) */
- LCD_WriteReg(LCD_REG_3, 0x1008);
- LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
- }
-
- /* Read bitmap data from SPI Flash and send them to LCD */
- for(i = 0; i < size; i++)
- {
- LCD_WriteRAM(__REV16(SPI_FLASH_SendHalfWord(0xA5A5)));
- }
- if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
- {
- LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
- }
-
- /* Deselect the FLASH: Chip Select high */
- SPI_FLASH_CS_HIGH();
- /* Disable SPI1 */
- SPI_Cmd(SPI1, DISABLE);
- /* SPI in 8-bit mode */
- SPI_DataSizeConfig(SPI1, SPI_DataSize_8b);
- /* Enable SPI1 */
- SPI_Cmd(SPI1, ENABLE);
-
- if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
- {
- /* Set GRAM write direction and BGR = 1 */
- /* I/D = 01 (Horizontal : increment, Vertical : decrement) */
- /* AM = 1 (address is updated in vertical writing direction) */
- LCD_WriteReg(LCD_REG_3, 0x1018);
- }
-}
-#endif /* USE_LCD_DrawBMP */
-
-/**
- * @brief Displays a full rectangle.
- * @param Xpos: specifies the X position.
- * @param Ypos: specifies the Y position.
- * @param Height: rectangle height.
- * @param Width: rectangle width.
- * @retval None
- */
-void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
-{
- LCD_SetTextColor(TextColor);
-
- LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
- LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
-
- LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
- LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
-
- Width -= 2;
- Height--;
- Ypos--;
-
- LCD_SetTextColor(BackColor);
-
- while(Height--)
- {
- LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
- }
-
- LCD_SetTextColor(TextColor);
-}
-
-/**
- * @brief Displays a full circle.
- * @param Xpos: specifies the X position.
- * @param Ypos: specifies the Y position.
- * @param Radius
- * @retval None
- */
-void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
-{
- int32_t D; /* Decision Variable */
- uint32_t CurX;/* Current X Value */
- uint32_t CurY;/* Current Y Value */
-
- D = 3 - (Radius << 1);
-
- CurX = 0;
- CurY = Radius;
-
- LCD_SetTextColor(BackColor);
-
- while (CurX <= CurY)
- {
- if(CurY > 0)
- {
- LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
- LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
- }
-
- if(CurX > 0)
- {
- LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
- LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
- }
- if (D < 0)
- {
- D += (CurX << 2) + 6;
- }
- else
- {
- D += ((CurX - CurY) << 2) + 10;
- CurY--;
- }
- CurX++;
- }
-
- LCD_SetTextColor(TextColor);
- LCD_DrawCircle(Xpos, Ypos, Radius);
-}
-
-/**
- * @brief Displays an uni line (between two points).
- * @param x1: specifies the point 1 x position.
- * @param y1: specifies the point 1 y position.
- * @param x2: specifies the point 2 x position.
- * @param y2: specifies the point 2 y position.
- * @retval None
- */
-void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
-{
- int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0,
- yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0,
- curpixel = 0;
-
- deltax = ABS(x2 - x1); /* The difference between the x's */
- deltay = ABS(y2 - y1); /* The difference between the y's */
- x = x1; /* Start x off at the first pixel */
- y = y1; /* Start y off at the first pixel */
-
- if (x2 >= x1) /* The x-values are increasing */
- {
- xinc1 = 1;
- xinc2 = 1;
- }
- else /* The x-values are decreasing */
- {
- xinc1 = -1;
- xinc2 = -1;
- }
-
- if (y2 >= y1) /* The y-values are increasing */
- {
- yinc1 = 1;
- yinc2 = 1;
- }
- else /* The y-values are decreasing */
- {
- yinc1 = -1;
- yinc2 = -1;
- }
-
- if (deltax >= deltay) /* There is at least one x-value for every y-value */
- {
- xinc1 = 0; /* Don't change the x when numerator >= denominator */
- yinc2 = 0; /* Don't change the y for every iteration */
- den = deltax;
- num = deltax / 2;
- numadd = deltay;
- numpixels = deltax; /* There are more x-values than y-values */
- }
- else /* There is at least one y-value for every x-value */
- {
- xinc2 = 0; /* Don't change the x for every iteration */
- yinc1 = 0; /* Don't change the y when numerator >= denominator */
- den = deltay;
- num = deltay / 2;
- numadd = deltax;
- numpixels = deltay; /* There are more y-values than x-values */
- }
-
- for (curpixel = 0; curpixel <= numpixels; curpixel++)
- {
- PutPixel(x, y); /* Draw the current pixel */
- num += numadd; /* Increase the numerator by the top of the fraction */
- if (num >= den) /* Check if numerator >= denominator */
- {
- num -= den; /* Calculate the new numerator value */
- x += xinc1; /* Change the x as appropriate */
- y += yinc1; /* Change the y as appropriate */
- }
- x += xinc2; /* Change the x as appropriate */
- y += yinc2; /* Change the y as appropriate */
- }
-}
-
-/**
- * @brief Displays an polyline (between many points).
- * @param Points: pointer to the points array.
- * @param PointCount: Number of points.
- * @retval None
- */
-void LCD_PolyLine(pPoint Points, uint16_t PointCount)
-{
- int16_t X = 0, Y = 0;
-
- if(PointCount < 2)
- {
- return;
- }
-
- while(--PointCount)
- {
- X = Points->X;
- Y = Points->Y;
- Points++;
- LCD_DrawUniLine(X, Y, Points->X, Points->Y);
- }
-}
-
-/**
- * @brief Displays an relative polyline (between many points).
- * @param Points: pointer to the points array.
- * @param PointCount: Number of points.
- * @param Closed: specifies if the draw is closed or not.
- * 1: closed, 0 : not closed.
- * @retval None
- */
-static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed)
-{
- int16_t X = 0, Y = 0;
- pPoint First = Points;
-
- if(PointCount < 2)
- {
- return;
- }
- X = Points->X;
- Y = Points->Y;
- while(--PointCount)
- {
- Points++;
- LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y);
- X = X + Points->X;
- Y = Y + Points->Y;
- }
- if(Closed)
- {
- LCD_DrawUniLine(First->X, First->Y, X, Y);
- }
-}
-
-/**
- * @brief Displays a closed polyline (between many points).
- * @param Points: pointer to the points array.
- * @param PointCount: Number of points.
- * @retval None
- */
-void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount)
-{
- LCD_PolyLine(Points, PointCount);
- LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y);
-}
-
-/**
- * @brief Displays a relative polyline (between many points).
- * @param Points: pointer to the points array.
- * @param PointCount: Number of points.
- * @retval None
- */
-void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount)
-{
- LCD_PolyLineRelativeClosed(Points, PointCount, 0);
-}
-
-/**
- * @brief Displays a closed relative polyline (between many points).
- * @param Points: pointer to the points array.
- * @param PointCount: Number of points.
- * @retval None
- */
-void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount)
-{
- LCD_PolyLineRelativeClosed(Points, PointCount, 1);
-}
-
-
-/**
- * @brief Displays a full polyline (between many points).
- * @param Points: pointer to the points array.
- * @param PointCount: Number of points.
- * @retval None
- */
-void LCD_FillPolyLine(pPoint Points, uint16_t PointCount)
-{
- /* public-domain code by Darel Rex Finley, 2007 */
- uint16_t nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0,
- j = 0, swap = 0;
- uint16_t IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0;
-
- IMAGE_LEFT = IMAGE_RIGHT = Points->X;
- IMAGE_TOP= IMAGE_BOTTOM = Points->Y;
-
- for(i = 1; i < PointCount; i++)
- {
- pixelX = POLY_X(i);
- if(pixelX < IMAGE_LEFT)
- {
- IMAGE_LEFT = pixelX;
- }
- if(pixelX > IMAGE_RIGHT)
- {
- IMAGE_RIGHT = pixelX;
- }
-
- pixelY = POLY_Y(i);
- if(pixelY < IMAGE_TOP)
- {
- IMAGE_TOP = pixelY;
- }
- if(pixelY > IMAGE_BOTTOM)
- {
- IMAGE_BOTTOM = pixelY;
- }
- }
-
- LCD_SetTextColor(BackColor);
-
- /* Loop through the rows of the image. */
- for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++)
- {
- /* Build a list of nodes. */
- nodes = 0; j = PointCount-1;
-
- for (i = 0; i < PointCount; i++)
- {
- if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY)
- {
- nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i)));
- }
- j = i;
- }
-
- /* Sort the nodes, via a simple “Bubble” sort. */
- i = 0;
- while (i < nodes-1)
- {
- if (nodeX[i]>nodeX[i+1])
- {
- swap = nodeX[i];
- nodeX[i] = nodeX[i+1];
- nodeX[i+1] = swap;
- if(i)
- {
- i--;
- }
- }
- else
- {
- i++;
- }
- }
-
- /* Fill the pixels between node pairs. */
- for (i = 0; i < nodes; i+=2)
- {
- if(nodeX[i] >= IMAGE_RIGHT)
- {
- break;
- }
- if(nodeX[i+1] > IMAGE_LEFT)
- {
- if (nodeX[i] < IMAGE_LEFT)
- {
- nodeX[i]=IMAGE_LEFT;
- }
- if(nodeX[i+1] > IMAGE_RIGHT)
- {
- nodeX[i+1] = IMAGE_RIGHT;
- }
- LCD_SetTextColor(BackColor);
- LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL);
- LCD_SetTextColor(TextColor);
- PutPixel(pixelY, nodeX[i+1]);
- PutPixel(pixelY, nodeX[i]);
- /* for (j=nodeX[i]; j<nodeX[i+1]; j++) PutPixel(j,pixelY); */
- }
- }
- }
-
- /* draw the edges */
- LCD_SetTextColor(TextColor);
-}
-
-/**
- * @brief Reset LCD control line(/CS) and Send Start-Byte
- * @param Start_Byte: the Start-Byte to be sent
- * @retval None
- */
-void LCD_nCS_StartByte(uint8_t Start_Byte)
-{
- LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
-
- SPI_SendData(LCD_SPI, Start_Byte);
-
- while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
- {
- }
-}
-
-
-/**
- * @brief Writes index to select the LCD register.
- * @param LCD_Reg: address of the selected register.
- * @retval None
- */
-void LCD_WriteRegIndex(uint8_t LCD_Reg)
-{
- /* Reset LCD control line(/CS) and Send Start-Byte */
- LCD_nCS_StartByte(START_BYTE | SET_INDEX);
-
- /* Write 16-bit Reg Index (High Byte is 0) */
- SPI_SendData(LCD_SPI, 0x00);
-
- while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
- {
- }
-
- SPI_SendData(LCD_SPI, LCD_Reg);
-
- while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
- {
- }
-
- LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-
-/**
- * @brief Writes to the selected LCD ILI9320 register.
- * @param LCD_Reg: address of the selected register.
- * @param LCD_RegValue: value to write to the selected register.
- * @retval None
- */
-void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)
-{
- /* Write 16-bit Index (then Write Reg) */
- LCD_WriteRegIndex(LCD_Reg);
-
- /* Write 16-bit Reg */
- /* Reset LCD control line(/CS) and Send Start-Byte */
- LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
-
- SPI_SendData(LCD_SPI, LCD_RegValue >> 8);
-
- while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
- {
- }
-
- SPI_SendData(LCD_SPI, (LCD_RegValue & 0xFF));
-
- while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
- {
- }
-
- LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-
-/**
- * @brief Reads the selected LCD Register.
- * @param LCD_Reg: address of the selected register.
- * @retval LCD Register Value.
- */
-uint16_t LCD_ReadReg(uint8_t LCD_Reg)
-{
- uint16_t tmp = 0;
- uint8_t i = 0;
-
- /* LCD_SPI prescaler: 4 */
- LCD_SPI->CR1 &= 0xFFC7;
- LCD_SPI->CR1 |= 0x0008;
- /* Write 16-bit Index (then Read Reg) */
- LCD_WriteRegIndex(LCD_Reg);
- /* Read 16-bit Reg */
- /* Reset LCD control line(/CS) and Send Start-Byte */
- LCD_nCS_StartByte(START_BYTE | LCD_READ_REG);
-
- for(i = 0; i < 5; i++)
- {
- SPI_SendData(LCD_SPI, 0xFF);
- while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
- {
- }
- /* One byte of invalid dummy data read after the start byte */
- while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET)
- {
- }
- SPI_ReceiveData(LCD_SPI);
- }
-
- SPI_SendData(LCD_SPI, 0xFF);
-
- /* Read upper byte */
- while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
- {
- }
-
- /* Read lower byte */
- while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET)
- {
- }
- tmp = SPI_ReceiveData(LCD_SPI);
-
-
- SPI_SendData(LCD_SPI, 0xFF);
- while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
- {
- }
-
- /* Read lower byte */
- while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET)
- {
- }
-
- tmp = ((tmp & 0xFF) << 8) | SPI_ReceiveData(LCD_SPI);
- LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-
- /* LCD_SPI prescaler: 2 */
- LCD_SPI->CR1 &= 0xFFC7;
-
- return tmp;
-}
-
-
-/**
- * @brief Prepare to write to the LCD RAM.
- * @param None
- * @retval None
- */
-void LCD_WriteRAM_Prepare(void)
-{
- LCD_WriteRegIndex(LCD_REG_34); /* Select GRAM Reg */
-
- /* Reset LCD control line(/CS) and Send Start-Byte */
- LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
-}
-
-
-/**
- * @brief Writes 1 word to the LCD RAM.
- * @param RGB_Code: the pixel color in RGB mode (5-6-5).
- * @retval None
- */
-void LCD_WriteRAMWord(uint16_t RGB_Code)
-{
- LCD_WriteRAM_Prepare();
-
- LCD_WriteRAM(RGB_Code);
-
- LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-/**
- * @brief Writes to the LCD RAM.
- * @param RGB_Code: the pixel color in RGB mode (5-6-5).
- * @retval None
- */
-void LCD_WriteRAM(uint16_t RGB_Code)
-{
- SPI_SendData(LCD_SPI, RGB_Code >> 8);
- while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
- {
- }
- SPI_SendData(LCD_SPI, RGB_Code & 0xFF);
- while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
- {
- }
-}
-
-
-/**
- * @brief Power on the LCD.
- * @param None
- * @retval None
- */
-void LCD_PowerOn(void)
-{
- /* Power On sequence ---------------------------------------------------------*/
- LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
- LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
- LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
- LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
- _delay_(20); /* Dis-charge capacitor power voltage (200ms) */
- LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
- LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
- _delay_(5); /* Delay 50 ms */
- LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
- _delay_(5); /* delay 50 ms */
- LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
- LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
- _delay_(5); /* delay 50 ms */
- LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
-}
-
-
-/**
- * @brief Enables the Display.
- * @param None
- * @retval None
- */
-void LCD_DisplayOn(void)
-{
- /* Display On */
- LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
-}
-
-
-/**
- * @brief Disables the Display.
- * @param None
- * @retval None
- */
-void LCD_DisplayOff(void)
-{
- /* Display Off */
- LCD_WriteReg(LCD_REG_7, 0x0);
-}
-
-
-/**
- * @brief Configures LCD control lines in Output Push-Pull mode.
- * @param None
- * @retval None
- */
-void LCD_CtrlLinesConfig(void)
-{
- GPIO_InitTypeDef GPIO_InitStructure;
-
- RCC_AHBPeriphClockCmd(LCD_NCS_GPIO_CLK, ENABLE);
-
- /* Configure NCS (PF.02) in Output Push-Pull mode */
- GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
-
- LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-
-/**
- * @brief Sets or reset LCD control lines.
- * @param GPIOx: where x can be B or D to select the GPIO peripheral.
- * @param CtrlPins: the Control line.
- * This parameter can be:
- * @arg LCD_NCS_PIN: Chip Select pin
- * @arg LCD_NWR_PIN: Read/Write Selection pin
- * @arg LCD_RS_PIN: Register/RAM Selection pin
- * @param BitVal: specifies the value to be written to the selected bit.
- * This parameter can be:
- * @arg Bit_RESET: to clear the port pin
- * @arg Bit_SET: to set the port pin
- * @retval None
- */
-void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal)
-{
- /* Set or Reset the control line */
- GPIO_WriteBit(GPIOx, CtrlPins, BitVal);
-}
-
-
-/**
- * @brief Configures the LCD_SPI interface.
- * @param None
- * @retval None
- */
-void LCD_SPIConfig(void)
-{
- SPI_InitTypeDef SPI_InitStructure;
- GPIO_InitTypeDef GPIO_InitStructure;
-
- /* Enable LCD_SPI_SCK_GPIO_CLK, LCD_SPI_MISO_GPIO_CLK and LCD_SPI_MOSI_GPIO_CLK clock */
- RCC_AHBPeriphClockCmd(LCD_SPI_SCK_GPIO_CLK | LCD_SPI_MISO_GPIO_CLK | LCD_SPI_MOSI_GPIO_CLK, ENABLE);
-
- /* Enable LCD_SPI and SYSCFG clock */
- RCC_APB2PeriphClockCmd(LCD_SPI_CLK | RCC_APB2Periph_SYSCFG, ENABLE);
-
- /* Configure LCD_SPI SCK pin */
- GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
- /* Configure LCD_SPI MISO pin */
- GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;
- GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-
- /* Configure LCD_SPI MOSI pin */
- GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;
- GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
- /* Connect PE.13 to SPI SCK */
- GPIO_PinAFConfig(LCD_SPI_SCK_GPIO_PORT, LCD_SPI_SCK_SOURCE, LCD_SPI_SCK_AF);
-
- /* Connect PE.14 to SPI MISO */
- GPIO_PinAFConfig(LCD_SPI_MISO_GPIO_PORT, LCD_SPI_MISO_SOURCE, LCD_SPI_MISO_AF);
-
- /* Connect PE.15 to SPI MOSI */
- GPIO_PinAFConfig(LCD_SPI_MOSI_GPIO_PORT, LCD_SPI_MOSI_SOURCE, LCD_SPI_MOSI_AF);
-
- SPI_DeInit(LCD_SPI);
-
- /* SPI Config */
- SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
- SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
- SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
- SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
- SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
- SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
- SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
- SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
- SPI_InitStructure.SPI_CRCPolynomial = 7;
- SPI_Init(LCD_SPI, &SPI_InitStructure);
-
- /* SPI enable */
- SPI_Cmd(LCD_SPI, ENABLE);
-}
-
-/**
- * @brief Displays a pixel.
- * @param x: pixel x.
- * @param y: pixel y.
- * @retval None
- */
-static void PutPixel(int16_t x, int16_t y)
-{
- if(x < 0 || x > 239 || y < 0 || y > 319)
- {
- return;
- }
- LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL);
-}
-
-#ifndef USE_Delay
-/**
- * @brief Inserts a delay time.
- * @param nCount: specifies the delay time length.
- * @retval None
- */
-static void delay(__IO uint32_t nCount)
-{
- __IO uint32_t index = 0;
- for(index = (34000 * nCount); index != 0; index--)
- {
- }
-}
-#endif /* USE_Delay*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.h b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.h
deleted file mode 100644
index e3c06a1..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.h
+++ /dev/null
@@ -1,391 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l152_eval_lcd.h
- * @author MCD Application Team
- * @version V4.4.0RC1
- * @date 07/02/2010
- * @brief This file contains all the functions prototypes for the stm32l152_eval_lcd
- * firmware driver.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L152_EVAL_LCD_H
-#define __STM32L152_EVAL_LCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-#include "../Common/fonts.h"
-
-/** @addtogroup Utilities
- * @{
- */
-
-/** @addtogroup STM32_EVAL
- * @{
- */
-
-/** @addtogroup STM32L152_EVAL
- * @{
- */
-
-/** @addtogroup STM32L152_EVAL_LCD
- * @{
- */
-
-
-/** @defgroup STM32L152_EVAL_LCD_Exported_Types
- * @{
- */
-typedef struct
-{
- int16_t X;
- int16_t Y;
-} Point, * pPoint;
-/**
- * @}
- */
-
-/** @defgroup STM32L152_EVAL_LCD_Exported_Constants
- * @{
- */
-
-/**
- * @brief Uncomment the line below if you want to use LCD_DrawBMP function to
- * display a bitmap picture on the LCD. This function assumes that the bitmap
- * file is loaded in the SPI Flash (mounted on STM32L152-EVAL board), however
- * user can tailor it according to his application hardware requirement.
- */
-/*#define USE_LCD_DrawBMP*/
-
-/**
- * @brief Uncomment the line below if you want to use user defined Delay function
- * (for precise timing), otherwise default _delay_ function defined within
- * this driver is used (less precise timing).
- */
-/* #define USE_Delay */
-
-#ifdef USE_Delay
-#include "main.h"
-
- #define _delay_ Delay /* !< User can provide more timing precise _delay_ function
- (with 10ms time base), using SysTick for example */
-#else
- #define _delay_ delay /* !< Default _delay_ function with less precise timing */
-#endif
-
-
-/**
- * @brief LCD Control pins
- */
-#define LCD_NCS_PIN GPIO_Pin_2
-#define LCD_NCS_GPIO_PORT GPIOH
-#define LCD_NCS_GPIO_CLK RCC_AHBPeriph_GPIOH
-
-/**
- * @brief LCD SPI Interface pins
- */
-#define LCD_SPI_SCK_PIN GPIO_Pin_13 /* PE.13 */
-#define LCD_SPI_SCK_GPIO_PORT GPIOE /* GPIOE */
-#define LCD_SPI_SCK_GPIO_CLK RCC_AHBPeriph_GPIOE
-#define LCD_SPI_SCK_SOURCE GPIO_PinSource13
-#define LCD_SPI_SCK_AF GPIO_AF_SPI1
-#define LCD_SPI_MISO_PIN GPIO_Pin_14 /* PE.14 */
-#define LCD_SPI_MISO_GPIO_PORT GPIOE /* GPIOE */
-#define LCD_SPI_MISO_GPIO_CLK RCC_AHBPeriph_GPIOE
-#define LCD_SPI_MISO_SOURCE GPIO_PinSource14
-#define LCD_SPI_MISO_AF GPIO_AF_SPI1
-#define LCD_SPI_MOSI_PIN GPIO_Pin_15 /* PE.15 */
-#define LCD_SPI_MOSI_GPIO_PORT GPIOE /* GPIOE */
-#define LCD_SPI_MOSI_GPIO_CLK RCC_AHBPeriph_GPIOE
-#define LCD_SPI_MOSI_SOURCE GPIO_PinSource15
-#define LCD_SPI_MOSI_AF GPIO_AF_SPI1
-#define LCD_SPI SPI1
-#define LCD_SPI_CLK RCC_APB2Periph_SPI1
-
-
-/**
- * @brief LCD Registers
- */
-#define LCD_REG_0 0x00
-#define LCD_REG_1 0x01
-#define LCD_REG_2 0x02
-#define LCD_REG_3 0x03
-#define LCD_REG_4 0x04
-#define LCD_REG_5 0x05
-#define LCD_REG_6 0x06
-#define LCD_REG_7 0x07
-#define LCD_REG_8 0x08
-#define LCD_REG_9 0x09
-#define LCD_REG_10 0x0A
-#define LCD_REG_12 0x0C
-#define LCD_REG_13 0x0D
-#define LCD_REG_14 0x0E
-#define LCD_REG_15 0x0F
-#define LCD_REG_16 0x10
-#define LCD_REG_17 0x11
-#define LCD_REG_18 0x12
-#define LCD_REG_19 0x13
-#define LCD_REG_20 0x14
-#define LCD_REG_21 0x15
-#define LCD_REG_22 0x16
-#define LCD_REG_23 0x17
-#define LCD_REG_24 0x18
-#define LCD_REG_25 0x19
-#define LCD_REG_26 0x1A
-#define LCD_REG_27 0x1B
-#define LCD_REG_28 0x1C
-#define LCD_REG_29 0x1D
-#define LCD_REG_30 0x1E
-#define LCD_REG_31 0x1F
-#define LCD_REG_32 0x20
-#define LCD_REG_33 0x21
-#define LCD_REG_34 0x22
-#define LCD_REG_36 0x24
-#define LCD_REG_37 0x25
-#define LCD_REG_40 0x28
-#define LCD_REG_41 0x29
-#define LCD_REG_43 0x2B
-#define LCD_REG_45 0x2D
-#define LCD_REG_48 0x30
-#define LCD_REG_49 0x31
-#define LCD_REG_50 0x32
-#define LCD_REG_51 0x33
-#define LCD_REG_52 0x34
-#define LCD_REG_53 0x35
-#define LCD_REG_54 0x36
-#define LCD_REG_55 0x37
-#define LCD_REG_56 0x38
-#define LCD_REG_57 0x39
-#define LCD_REG_59 0x3B
-#define LCD_REG_60 0x3C
-#define LCD_REG_61 0x3D
-#define LCD_REG_62 0x3E
-#define LCD_REG_63 0x3F
-#define LCD_REG_64 0x40
-#define LCD_REG_65 0x41
-#define LCD_REG_66 0x42
-#define LCD_REG_67 0x43
-#define LCD_REG_68 0x44
-#define LCD_REG_69 0x45
-#define LCD_REG_70 0x46
-#define LCD_REG_71 0x47
-#define LCD_REG_72 0x48
-#define LCD_REG_73 0x49
-#define LCD_REG_74 0x4A
-#define LCD_REG_75 0x4B
-#define LCD_REG_76 0x4C
-#define LCD_REG_77 0x4D
-#define LCD_REG_78 0x4E
-#define LCD_REG_79 0x4F
-#define LCD_REG_80 0x50
-#define LCD_REG_81 0x51
-#define LCD_REG_82 0x52
-#define LCD_REG_83 0x53
-#define LCD_REG_96 0x60
-#define LCD_REG_97 0x61
-#define LCD_REG_106 0x6A
-#define LCD_REG_118 0x76
-#define LCD_REG_128 0x80
-#define LCD_REG_129 0x81
-#define LCD_REG_130 0x82
-#define LCD_REG_131 0x83
-#define LCD_REG_132 0x84
-#define LCD_REG_133 0x85
-#define LCD_REG_134 0x86
-#define LCD_REG_135 0x87
-#define LCD_REG_136 0x88
-#define LCD_REG_137 0x89
-#define LCD_REG_139 0x8B
-#define LCD_REG_140 0x8C
-#define LCD_REG_141 0x8D
-#define LCD_REG_143 0x8F
-#define LCD_REG_144 0x90
-#define LCD_REG_145 0x91
-#define LCD_REG_146 0x92
-#define LCD_REG_147 0x93
-#define LCD_REG_148 0x94
-#define LCD_REG_149 0x95
-#define LCD_REG_150 0x96
-#define LCD_REG_151 0x97
-#define LCD_REG_152 0x98
-#define LCD_REG_153 0x99
-#define LCD_REG_154 0x9A
-#define LCD_REG_157 0x9D
-#define LCD_REG_192 0xC0
-#define LCD_REG_193 0xC1
-#define LCD_REG_227 0xE3
-#define LCD_REG_229 0xE5
-#define LCD_REG_231 0xE7
-#define LCD_REG_239 0xEF
-
-
-/**
- * @brief LCD color
- */
-#define LCD_COLOR_WHITE 0xFFFF
-#define LCD_COLOR_BLACK 0x0000
-#define LCD_COLOR_GREY 0xF7DE
-#define LCD_COLOR_BLUE 0x001F
-#define LCD_COLOR_BLUE2 0x051F
-#define LCD_COLOR_RED 0xF800
-#define LCD_COLOR_MAGENTA 0xF81F
-#define LCD_COLOR_GREEN 0x07E0
-#define LCD_COLOR_CYAN 0x7FFF
-#define LCD_COLOR_YELLOW 0xFFE0
-
-/**
- * @brief LCD Lines depending on the chosen fonts.
- */
-#define LCD_LINE_0 LINE(0)
-#define LCD_LINE_1 LINE(1)
-#define LCD_LINE_2 LINE(2)
-#define LCD_LINE_3 LINE(3)
-#define LCD_LINE_4 LINE(4)
-#define LCD_LINE_5 LINE(5)
-#define LCD_LINE_6 LINE(6)
-#define LCD_LINE_7 LINE(7)
-#define LCD_LINE_8 LINE(8)
-#define LCD_LINE_9 LINE(9)
-#define LCD_LINE_10 LINE(10)
-#define LCD_LINE_11 LINE(11)
-#define LCD_LINE_12 LINE(12)
-#define LCD_LINE_13 LINE(13)
-#define LCD_LINE_14 LINE(14)
-#define LCD_LINE_15 LINE(15)
-#define LCD_LINE_16 LINE(16)
-#define LCD_LINE_17 LINE(17)
-#define LCD_LINE_18 LINE(18)
-#define LCD_LINE_19 LINE(19)
-#define LCD_LINE_20 LINE(20)
-#define LCD_LINE_21 LINE(21)
-#define LCD_LINE_22 LINE(22)
-#define LCD_LINE_23 LINE(23)
-#define LCD_LINE_24 LINE(24)
-#define LCD_LINE_25 LINE(25)
-#define LCD_LINE_26 LINE(26)
-#define LCD_LINE_27 LINE(27)
-#define LCD_LINE_28 LINE(28)
-#define LCD_LINE_29 LINE(29)
-
-
-/**
- * @brief LCD default font
- */
-#define LCD_DEFAULT_FONT Font16x24
-
-/**
- * @brief LCD Direction
- */
-#define LCD_DIR_HORIZONTAL 0x0000
-#define LCD_DIR_VERTICAL 0x0001
-
-/**
- * @brief LCD Size (Width and Height)
- */
-#define LCD_PIXEL_WIDTH 0x0140
-#define LCD_PIXEL_HEIGHT 0x00F0
-
-/**
- * @}
- */
-
-/** @defgroup STM32L152_EVAL_LCD_Exported_Macros
- * @{
- */
-#define ASSEMBLE_RGB(R, G, B) ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))
-
-/**
- * @}
- */
-
-/** @defgroup STM32L152_EVAL_LCD_Exported_Functions
- * @{
- */
-void STM32L152_LCD_DeInit(void);
-void LCD_Setup(void);
-void STM32L152_LCD_Init(void);
-void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor);
-void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor);
-void LCD_SetTextColor(__IO uint16_t Color);
-void LCD_SetBackColor(__IO uint16_t Color);
-void LCD_ClearLine(uint8_t Line);
-void LCD_Clear(uint16_t Color);
-void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos);
-void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c);
-void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii);
-void LCD_SetFont(sFONT *fonts);
-sFONT *LCD_GetFont(void);
-void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr);
-void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
-void LCD_WindowModeDisable(void);
-void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);
-void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
-void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius);
-void LCD_DrawMonoPict(const uint32_t *Pict);
-void LCD_DrawBMP(uint32_t BmpAddress);
-void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
-void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
-void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
-void LCD_PolyLine(pPoint Points, uint16_t PointCount);
-void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount);
-void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount);
-void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount);
-void LCD_FillPolyLine(pPoint Points, uint16_t PointCount);
-void LCD_nCS_StartByte(uint8_t Start_Byte);
-void LCD_WriteRegIndex(uint8_t LCD_Reg);
-void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue);
-void LCD_WriteRAM_Prepare(void);
-void LCD_WriteRAMWord(uint16_t RGB_Code);
-uint16_t LCD_ReadReg(uint8_t LCD_Reg);
-void LCD_WriteRAM(uint16_t RGB_Code);
-void LCD_PowerOn(void);
-void LCD_DisplayOn(void);
-void LCD_DisplayOff(void);
-
-void LCD_CtrlLinesConfig(void);
-void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal);
-void LCD_SPIConfig(void);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L152_EVAL_LCD_H */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/misc.h b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/misc.h
deleted file mode 100644
index 6ae338d..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/misc.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/**
- ******************************************************************************
- * @file misc.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief This file contains all the functions prototypes for the miscellaneous
- * firmware library functions (add-on to CMSIS functions).
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __MISC_H
-#define __MISC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup MISC
- * @{
- */
-
-/** @defgroup MISC_Exported_Types
- * @{
- */
-
-/**
- * @brief NVIC Init Structure definition
- */
-
-typedef struct
-{
- uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
- This parameter can be a value of @ref IRQn_Type
- (For the complete STM32 Devices IRQ Channels list, please
- refer to stm32l1xx.h file) */
-
- uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
- specified in NVIC_IRQChannel. This parameter can be a value
- between 0 and 15 as described in the table @ref NVIC_Priority_Table */
-
- uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
- in NVIC_IRQChannel. This parameter can be a value
- between 0 and 15 as described in the table @ref NVIC_Priority_Table */
-
- FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
- will be enabled or disabled.
- This parameter can be set either to ENABLE or DISABLE */
-} NVIC_InitTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup NVIC_Priority_Table
- * @{
- */
-
-/**
-@code
- The table below gives the allowed values of the pre-emption priority and subpriority according
- to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
- ============================================================================================================================
- NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
- ============================================================================================================================
- NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
- | | | 4 bits for subpriority
- ----------------------------------------------------------------------------------------------------------------------------
- NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
- | | | 3 bits for subpriority
- ----------------------------------------------------------------------------------------------------------------------------
- NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
- | | | 2 bits for subpriority
- ----------------------------------------------------------------------------------------------------------------------------
- NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
- | | | 1 bits for subpriority
- ----------------------------------------------------------------------------------------------------------------------------
- NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
- | | | 0 bits for subpriority
- ============================================================================================================================
-@endcode
-*/
-
-/**
- * @}
- */
-
-/** @defgroup MISC_Exported_Constants
- * @{
- */
-
-/** @defgroup Vector_Table_Base
- * @{
- */
-
-#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
-#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
-#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
- ((VECTTAB) == NVIC_VectTab_FLASH))
-/**
- * @}
- */
-
-/** @defgroup System_Low_Power
- * @{
- */
-
-#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
-#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
-#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
-#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
- ((LP) == NVIC_LP_SLEEPDEEP) || \
- ((LP) == NVIC_LP_SLEEPONEXIT))
-/**
- * @}
- */
-
-/** @defgroup Preemption_Priority_Group
- * @{
- */
-
-#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
- 4 bits for subpriority */
-#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
- 3 bits for subpriority */
-#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
- 2 bits for subpriority */
-#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
- 1 bits for subpriority */
-#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
- 0 bits for subpriority */
-
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
- ((GROUP) == NVIC_PriorityGroup_1) || \
- ((GROUP) == NVIC_PriorityGroup_2) || \
- ((GROUP) == NVIC_PriorityGroup_3) || \
- ((GROUP) == NVIC_PriorityGroup_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
-
-#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0001FFFF)
-
-/**
- * @}
- */
-
-/** @defgroup SysTick_clock_source
- * @{
- */
-
-#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
-#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
- ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup MISC_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup MISC_Exported_Functions
- * @{
- */
-
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __MISC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_exti.h b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_exti.h
deleted file mode 100644
index 769e4fc..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_exti.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l1xx_exti.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief This file contains all the functions prototypes for the EXTI firmware
- * library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_EXTI_H
-#define __STM32L1xx_EXTI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup EXTI
- * @{
- */
-
-/** @defgroup EXTI_Exported_Types
- * @{
- */
-
-/**
- * @brief EXTI mode enumeration
- */
-
-typedef enum
-{
- EXTI_Mode_Interrupt = 0x00,
- EXTI_Mode_Event = 0x04
-}EXTIMode_TypeDef;
-
-#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
-
-/**
- * @brief EXTI Trigger enumeration
- */
-
-typedef enum
-{
- EXTI_Trigger_Rising = 0x08,
- EXTI_Trigger_Falling = 0x0C,
- EXTI_Trigger_Rising_Falling = 0x10
-}EXTITrigger_TypeDef;
-
-#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
- ((TRIGGER) == EXTI_Trigger_Falling) || \
- ((TRIGGER) == EXTI_Trigger_Rising_Falling))
-/**
- * @brief EXTI Init Structure definition
- */
-
-typedef struct
-{
- uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
- This parameter can be any combination of @ref EXTI_Lines */
-
- EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
- This parameter can be a value of @ref EXTIMode_TypeDef */
-
- EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
- This parameter can be a value of @ref EXTIMode_TypeDef */
-
- FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
- This parameter can be set either to ENABLE or DISABLE */
-}EXTI_InitTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_Exported_Constants
- * @{
- */
-
-/** @defgroup EXTI_Lines
- * @{
- */
-
-#define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */
-#define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */
-#define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */
-#define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */
-#define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */
-#define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */
-#define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */
-#define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */
-#define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */
-#define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */
-#define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */
-#define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */
-#define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */
-#define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */
-#define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */
-#define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */
-#define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16
- Connected to the PVD Output */
-#define EXTI_Line17 ((uint32_t)0x00020000) /*!< External interrupt line 17
- Connected to the RTC Alarm
- event */
-#define EXTI_Line18 ((uint32_t)0x00040000) /*!< External interrupt line 18
- Connected to the USB Device
- FS Wakeup from suspend event */
-#define EXTI_Line19 ((uint32_t)0x00080000) /*!< External interrupt line 19
- Connected to the RTC Tamper
- and Time Stamp events */
-#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20
- Connected to the RTC Wakeup
- event */
-#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21
- Connected to the Comparator 1
- event */
-
-#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22
- Connected to the Comparator 2
- event */
-
-#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))
-
-#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
- ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
- ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
- ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
- ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
- ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
- ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
- ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
- ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
- ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
- ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
- ((LINE) == EXTI_Line22))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_Exported_Functions
- * @{
- */
-
-void EXTI_DeInit(void);
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
-void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
-FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
-void EXTI_ClearFlag(uint32_t EXTI_Line);
-ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
-void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_EXTI_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_gpio.h b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_gpio.h
deleted file mode 100644
index 189be5a..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_gpio.h
+++ /dev/null
@@ -1,369 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l1xx_gpio.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief This file contains all the functions prototypes for the GPIO
- * firmware library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_GPIO_H
-#define __STM32L1xx_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup GPIO
- * @{
- */
-
-/** @defgroup GPIO_Exported_Types
- * @{
- */
-#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
- ((PERIPH) == GPIOB) || \
- ((PERIPH) == GPIOC) || \
- ((PERIPH) == GPIOD) || \
- ((PERIPH) == GPIOE) || \
- ((PERIPH) == GPIOH))
-
-/** @defgroup Configuration_Mode_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
- GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
- GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
- GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */
-}GPIOMode_TypeDef;
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \
- ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
-/**
- * @}
- */
-
-/** @defgroup Output_type_enumeration
- * @{
- */
-typedef enum
-{ GPIO_OType_PP = 0x00,
- GPIO_OType_OD = 0x01
-}GPIOOType_TypeDef;
-#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
-
-/**
- * @}
- */
-
-/** @defgroup Output_Maximum_frequency_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_Speed_400KHz = 0x00, /*!< Very Low Speed */
- GPIO_Speed_2MHz = 0x01, /*!< Low Speed */
- GPIO_Speed_10MHz = 0x02, /*!< Medium Speed */
- GPIO_Speed_40MHz = 0x03 /*!< High Speed */
-}GPIOSpeed_TypeDef;
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_400KHz) || ((SPEED) == GPIO_Speed_2MHz) || \
- ((SPEED) == GPIO_Speed_10MHz)|| ((SPEED) == GPIO_Speed_40MHz))
-/**
- * @}
- */
-
-/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
- * @{
- */
-typedef enum
-{ GPIO_PuPd_NOPULL = 0x00,
- GPIO_PuPd_UP = 0x01,
- GPIO_PuPd_DOWN = 0x02
-}GPIOPuPd_TypeDef;
-#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
- ((PUPD) == GPIO_PuPd_DOWN))
-/**
- * @}
- */
-
-/** @defgroup Bit_SET_and_Bit_RESET_enumeration
- * @{
- */
-typedef enum
-{ Bit_RESET = 0,
- Bit_SET
-}BitAction;
-#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
-
-/**
- * @}
- */
-
-/**
- * @brief GPIO Init structure definition
- */
-typedef struct
-{
- uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
- This parameter can be any value of @ref GPIO_pins_define */
-
- GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref GPIOMode_TypeDef */
-
- GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
- This parameter can be a value of @ref GPIOSpeed_TypeDef */
-
- GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
- This parameter can be a value of @ref GPIOOType_TypeDef */
-
- GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
- This parameter can be a value of @ref GPIOPuPd_TypeDef */
-}GPIO_InitTypeDef;
-/**
- * @}
- */
-
-/** @defgroup GPIO_Exported_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_pins_define
- * @{
- */
-#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
-#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
-#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
-#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
-#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
-#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
-#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
-#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
-#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
-#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
-#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
-#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
-#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
-#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
-#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
-#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
-#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
-
-#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
-#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
- ((PIN) == GPIO_Pin_1) || \
- ((PIN) == GPIO_Pin_2) || \
- ((PIN) == GPIO_Pin_3) || \
- ((PIN) == GPIO_Pin_4) || \
- ((PIN) == GPIO_Pin_5) || \
- ((PIN) == GPIO_Pin_6) || \
- ((PIN) == GPIO_Pin_7) || \
- ((PIN) == GPIO_Pin_8) || \
- ((PIN) == GPIO_Pin_9) || \
- ((PIN) == GPIO_Pin_10) || \
- ((PIN) == GPIO_Pin_11) || \
- ((PIN) == GPIO_Pin_12) || \
- ((PIN) == GPIO_Pin_13) || \
- ((PIN) == GPIO_Pin_14) || \
- ((PIN) == GPIO_Pin_15))
-/**
- * @}
- */
-
-/** @defgroup GPIO_Pin_sources
- * @{
- */
-#define GPIO_PinSource0 ((uint8_t)0x00)
-#define GPIO_PinSource1 ((uint8_t)0x01)
-#define GPIO_PinSource2 ((uint8_t)0x02)
-#define GPIO_PinSource3 ((uint8_t)0x03)
-#define GPIO_PinSource4 ((uint8_t)0x04)
-#define GPIO_PinSource5 ((uint8_t)0x05)
-#define GPIO_PinSource6 ((uint8_t)0x06)
-#define GPIO_PinSource7 ((uint8_t)0x07)
-#define GPIO_PinSource8 ((uint8_t)0x08)
-#define GPIO_PinSource9 ((uint8_t)0x09)
-#define GPIO_PinSource10 ((uint8_t)0x0A)
-#define GPIO_PinSource11 ((uint8_t)0x0B)
-#define GPIO_PinSource12 ((uint8_t)0x0C)
-#define GPIO_PinSource13 ((uint8_t)0x0D)
-#define GPIO_PinSource14 ((uint8_t)0x0E)
-#define GPIO_PinSource15 ((uint8_t)0x0F)
-
-#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
- ((PINSOURCE) == GPIO_PinSource1) || \
- ((PINSOURCE) == GPIO_PinSource2) || \
- ((PINSOURCE) == GPIO_PinSource3) || \
- ((PINSOURCE) == GPIO_PinSource4) || \
- ((PINSOURCE) == GPIO_PinSource5) || \
- ((PINSOURCE) == GPIO_PinSource6) || \
- ((PINSOURCE) == GPIO_PinSource7) || \
- ((PINSOURCE) == GPIO_PinSource8) || \
- ((PINSOURCE) == GPIO_PinSource9) || \
- ((PINSOURCE) == GPIO_PinSource10) || \
- ((PINSOURCE) == GPIO_PinSource11) || \
- ((PINSOURCE) == GPIO_PinSource12) || \
- ((PINSOURCE) == GPIO_PinSource13) || \
- ((PINSOURCE) == GPIO_PinSource14) || \
- ((PINSOURCE) == GPIO_PinSource15))
-/**
- * @}
- */
-
-/** @defgroup GPIO_Alternat_function_selection_define
- * @{
- */
-
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /*!< RTC 50/60 Hz Alternate Function mapping */
-#define GPIO_AF_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */
-#define GPIO_AF_RTC_AF1 ((uint8_t)0x00) /*!< RTC_AF1 Alternate Function mapping */
-#define GPIO_AF_WKUP ((uint8_t)0x00) /*!< Wakeup (WKUP1, WKUP2 and WKUP3) Alternate Function mapping */
-#define GPIO_AF_SWJ ((uint8_t)0x00) /*!< SWJ (SW and JTAG) Alternate Function mapping */
-#define GPIO_AF_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */
-#define GPIO_AF_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF_TIM9 ((uint8_t)0x03) /*!< TIM9 Alternate Function mapping */
-#define GPIO_AF_TIM10 ((uint8_t)0x03) /*!< TIM10 Alternate Function mapping */
-#define GPIO_AF_TIM11 ((uint8_t)0x03) /*!< TIM11 Alternate Function mapping */
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */
-#define GPIO_AF_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */
-#define GPIO_AF_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */
-#define GPIO_AF_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */
-#define GPIO_AF_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF_USB ((uint8_t)0xA) /*!< USB Full speed device Alternate Function mapping */
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF_LCD ((uint8_t)0x0B) /*!< LCD Alternate Function mapping */
-/**
- * @brief AF 14 selection
- */
-#define GPIO_AF_RI ((uint8_t)0x0E) /*!< RI Alternate Function mapping */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_MCO) || \
- ((AF) == GPIO_AF_RTC_AF1) || ((AF) == GPIO_AF_WKUP) || \
- ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
- ((AF) == GPIO_AF_TIM2) || ((AF)== GPIO_AF_TIM3) || \
- ((AF) == GPIO_AF_TIM4) || ((AF)== GPIO_AF_TIM9) || \
- ((AF) == GPIO_AF_TIM10) || ((AF)== GPIO_AF_TIM11) || \
- ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
- ((AF) == GPIO_AF_SPI1) || ((AF) == GPIO_AF_SPI2) || \
- ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
- ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_USB) || \
- ((AF) == GPIO_AF_LCD) || ((AF) == GPIO_AF_RI) || \
- ((AF) == GPIO_AF_EVENTOUT))
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Legacy
- * @{
- */
-
-#define GPIO_Mode_AIN GPIO_Mode_AN
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Exported_Functions
- * @{
- */
-void GPIO_DeInit(GPIO_TypeDef* GPIOx);
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32L1xx_GPIO_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_i2c.h b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_i2c.h
deleted file mode 100644
index d4d2997..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_i2c.h
+++ /dev/null
@@ -1,670 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l1xx_i2c.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief This file contains all the functions prototypes for the I2C firmware
- * library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_I2C_H
-#define __STM32L1xx_I2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup I2C
- * @{
- */
-
-/** @defgroup I2C_Exported_Types
- * @{
- */
-
-/**
- * @brief I2C Init structure definition
- */
-
-typedef struct
-{
- uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
- This parameter must be set to a value lower than 400kHz */
-
- uint16_t I2C_Mode; /*!< Specifies the I2C mode.
- This parameter can be a value of @ref I2C_mode */
-
- uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
- This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
-
- uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
- This parameter can be a 7-bit or 10-bit address. */
-
- uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
- This parameter can be a value of @ref I2C_acknowledgement */
-
- uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
- This parameter can be a value of @ref I2C_acknowledged_address */
-}I2C_InitTypeDef;
-
-/**
- * @}
- */
-
-
-/** @defgroup I2C_Exported_Constants
- * @{
- */
-
-#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
- ((PERIPH) == I2C2))
-/** @defgroup I2C_mode
- * @{
- */
-
-#define I2C_Mode_I2C ((uint16_t)0x0000)
-#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
-#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
-#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
- ((MODE) == I2C_Mode_SMBusDevice) || \
- ((MODE) == I2C_Mode_SMBusHost))
-/**
- * @}
- */
-
-/** @defgroup I2C_duty_cycle_in_fast_mode
- * @{
- */
-
-#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
-#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
- ((CYCLE) == I2C_DutyCycle_2))
-/**
- * @}
- */
-
-/** @defgroup I2C_acknowledgement
- * @{
- */
-
-#define I2C_Ack_Enable ((uint16_t)0x0400)
-#define I2C_Ack_Disable ((uint16_t)0x0000)
-#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
- ((STATE) == I2C_Ack_Disable))
-/**
- * @}
- */
-
-/** @defgroup I2C_transfer_direction
- * @{
- */
-
-#define I2C_Direction_Transmitter ((uint8_t)0x00)
-#define I2C_Direction_Receiver ((uint8_t)0x01)
-#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
- ((DIRECTION) == I2C_Direction_Receiver))
-/**
- * @}
- */
-
-/** @defgroup I2C_acknowledged_address
- * @{
- */
-
-#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
-#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
-#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
- ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
-/**
- * @}
- */
-
-/** @defgroup I2C_registers
- * @{
- */
-
-#define I2C_Register_CR1 ((uint8_t)0x00)
-#define I2C_Register_CR2 ((uint8_t)0x04)
-#define I2C_Register_OAR1 ((uint8_t)0x08)
-#define I2C_Register_OAR2 ((uint8_t)0x0C)
-#define I2C_Register_DR ((uint8_t)0x10)
-#define I2C_Register_SR1 ((uint8_t)0x14)
-#define I2C_Register_SR2 ((uint8_t)0x18)
-#define I2C_Register_CCR ((uint8_t)0x1C)
-#define I2C_Register_TRISE ((uint8_t)0x20)
-#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
- ((REGISTER) == I2C_Register_CR2) || \
- ((REGISTER) == I2C_Register_OAR1) || \
- ((REGISTER) == I2C_Register_OAR2) || \
- ((REGISTER) == I2C_Register_DR) || \
- ((REGISTER) == I2C_Register_SR1) || \
- ((REGISTER) == I2C_Register_SR2) || \
- ((REGISTER) == I2C_Register_CCR) || \
- ((REGISTER) == I2C_Register_TRISE))
-/**
- * @}
- */
-
-/** @defgroup I2C_SMBus_alert_pin_level
- * @{
- */
-
-#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
-#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
-#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
- ((ALERT) == I2C_SMBusAlert_High))
-/**
- * @}
- */
-
-/** @defgroup I2C_PEC_position
- * @{
- */
-
-#define I2C_PECPosition_Next ((uint16_t)0x0800)
-#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
-#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
- ((POSITION) == I2C_PECPosition_Current))
-/**
- * @}
- */
-
-/** @defgroup I2C_interrupts_definition
- * @{
- */
-
-#define I2C_IT_BUF ((uint16_t)0x0400)
-#define I2C_IT_EVT ((uint16_t)0x0200)
-#define I2C_IT_ERR ((uint16_t)0x0100)
-#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup I2C_interrupts_definition
- * @{
- */
-
-#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
-#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
-#define I2C_IT_PECERR ((uint32_t)0x01001000)
-#define I2C_IT_OVR ((uint32_t)0x01000800)
-#define I2C_IT_AF ((uint32_t)0x01000400)
-#define I2C_IT_ARLO ((uint32_t)0x01000200)
-#define I2C_IT_BERR ((uint32_t)0x01000100)
-#define I2C_IT_TXE ((uint32_t)0x06000080)
-#define I2C_IT_RXNE ((uint32_t)0x06000040)
-#define I2C_IT_STOPF ((uint32_t)0x02000010)
-#define I2C_IT_ADD10 ((uint32_t)0x02000008)
-#define I2C_IT_BTF ((uint32_t)0x02000004)
-#define I2C_IT_ADDR ((uint32_t)0x02000002)
-#define I2C_IT_SB ((uint32_t)0x02000001)
-
-#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
-
-#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
- ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
- ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
- ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
- ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
- ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
- ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
-/**
- * @}
- */
-
-/** @defgroup I2C_flags_definition
- * @{
- */
-
-/**
- * @brief SR2 register flags
- */
-
-#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
-#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
-#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
-#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
-#define I2C_FLAG_TRA ((uint32_t)0x00040000)
-#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
-#define I2C_FLAG_MSL ((uint32_t)0x00010000)
-
-/**
- * @brief SR1 register flags
- */
-
-#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
-#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
-#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
-#define I2C_FLAG_OVR ((uint32_t)0x10000800)
-#define I2C_FLAG_AF ((uint32_t)0x10000400)
-#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
-#define I2C_FLAG_BERR ((uint32_t)0x10000100)
-#define I2C_FLAG_TXE ((uint32_t)0x10000080)
-#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
-#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
-#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
-#define I2C_FLAG_BTF ((uint32_t)0x10000004)
-#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
-#define I2C_FLAG_SB ((uint32_t)0x10000001)
-
-#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
-
-#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
- ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
- ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
- ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
- ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
- ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
- ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
- ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
- ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
- ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
- ((FLAG) == I2C_FLAG_SB))
-/**
- * @}
- */
-
-/** @defgroup I2C_Events
- * @{
- */
-
-/*========================================
-
- I2C Master Events (Events grouped in order of communication)
- ==========================================*/
-/**
- * @brief Communication start
- *
- * After sending the START condition (I2C_GenerateSTART() function) the master
- * has to wait for this event. It means that the Start condition has been correctly
- * released on the I2C bus (the bus is free, no other devices is communicating).
- *
- */
-/* --EV5 */
-#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
-
-/**
- * @brief Address Acknowledge
- *
- * After checking on EV5 (start condition correctly released on the bus), the
- * master sends the address of the slave(s) with which it will communicate
- * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
- * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
- * his address. If an acknowledge is sent on the bus, one of the following events will
- * be set:
- *
- * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
- * event is set.
- *
- * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
- * is set
- *
- * 3) In case of 10-Bit addressing mode, the master (just after generating the START
- * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
- * function). Then master should wait on EV9. It means that the 10-bit addressing
- * header has been correctly sent on the bus. Then master should send the second part of
- * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
- * should wait for event EV6.
- *
- */
-
-/* --EV6 */
-#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
-#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
-/* --EV9 */
-#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
-
-/**
- * @brief Communication events
- *
- * If a communication is established (START condition generated and slave address
- * acknowledged) then the master has to check on one of the following events for
- * communication procedures:
- *
- * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
- * the data received from the slave (I2C_ReceiveData() function).
- *
- * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
- * function) then to wait on event EV8 or EV8_2.
- * These two events are similar:
- * - EV8 means that the data has been written in the data register and is
- * being shifted out.
- * - EV8_2 means that the data has been physically shifted out and output
- * on the bus.
- * In most cases, using EV8 is sufficient for the application.
- * Using EV8_2 leads to a slower communication but ensure more reliable test.
- * EV8_2 is also more suitable than EV8 for testing on the last data transmission
- * (before Stop condition generation).
- *
- * @note In case the user software does not guarantee that this event EV7 is
- * managed before the current byte end of transfer, then user may check on EV7
- * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
- * In this case the communication may be slower.
- *
- */
-
-/* Master RECEIVER mode -----------------------------*/
-/* --EV7 */
-#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
-
-/* Master TRANSMITTER mode --------------------------*/
-/* --EV8 */
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
-/* --EV8_2 */
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
-
-
-/*========================================
-
- I2C Slave Events (Events grouped in order of communication)
- ==========================================*/
-
-/**
- * @brief Communication start events
- *
- * Wait on one of these events at the start of the communication. It means that
- * the I2C peripheral detected a Start condition on the bus (generated by master
- * device) followed by the peripheral address. The peripheral generates an ACK
- * condition on the bus (if the acknowledge feature is enabled through function
- * I2C_AcknowledgeConfig()) and the events listed above are set :
- *
- * 1) In normal case (only one address managed by the slave), when the address
- * sent by the master matches the own address of the peripheral (configured by
- * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
- * (where XXX could be TRANSMITTER or RECEIVER).
- *
- * 2) In case the address sent by the master matches the second address of the
- * peripheral (configured by the function I2C_OwnAddress2Config() and enabled
- * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
- * (where XXX could be TRANSMITTER or RECEIVER) are set.
- *
- * 3) In case the address sent by the master is General Call (address 0x00) and
- * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
- * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
- *
- */
-
-/* --EV1 (all the events below are variants of EV1) */
-/* 1) Case of One Single Address managed by the slave */
-#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
-#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
-
-/* 2) Case of Dual address managed by the slave */
-#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
-#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
-
-/* 3) Case of General Call enabled for the slave */
-#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
-
-/**
- * @brief Communication events
- *
- * Wait on one of these events when EV1 has already been checked and:
- *
- * - Slave RECEIVER mode:
- * - EV2: When the application is expecting a data byte to be received.
- * - EV4: When the application is expecting the end of the communication: master
- * sends a stop condition and data transmission is stopped.
- *
- * - Slave Transmitter mode:
- * - EV3: When a byte has been transmitted by the slave and the application is expecting
- * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
- * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
- * used when the user software doesn't guarantee the EV3 is managed before the
- * current byte end of tranfer.
- * - EV3_2: When the master sends a NACK in order to tell slave that data transmission
- * shall end (before sending the STOP condition). In this case slave has to stop sending
- * data bytes and expect a Stop condition on the bus.
- *
- * @note In case the user software does not guarantee that the event EV2 is
- * managed before the current byte end of transfer, then user may check on EV2
- * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
- * In this case the communication may be slower.
- *
- */
-
-/* Slave RECEIVER mode --------------------------*/
-/* --EV2 */
-#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
-/* --EV4 */
-#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
-
-/* Slave TRANSMITTER mode -----------------------*/
-/* --EV3 */
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
-/* --EV3_2 */
-#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
-
-/*=========================== End of Events Description ==========================================*/
-
-#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
- ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
- ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
- ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
- ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
- ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
- ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
- ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
-/**
- * @}
- */
-
-/** @defgroup I2C_own_address1
- * @{
- */
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
-/**
- * @}
- */
-
-/** @defgroup I2C_clock_speed
- * @{
- */
-
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Exported_Functions
- * @{
- */
-
-void I2C_DeInit(I2C_TypeDef* I2Cx);
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
-
-/**
- * @brief
- ****************************************************************************************
- *
- * I2C State Monitoring Functions
- *
- ****************************************************************************************
- * This I2C driver provides three different ways for I2C state monitoring
- * depending on the application requirements and constraints:
- *
- *
- * 1) Basic state monitoring:
- * Using I2C_CheckEvent() function:
- * It compares the status registers (SR1 and SR2) content to a given event
- * (can be the combination of one or more flags).
- * It returns SUCCESS if the current status includes the given flags
- * and returns ERROR if one or more flags are missing in the current status.
- * - When to use:
- * - This function is suitable for most applications as well as for startup
- * activity since the events are fully described in the product reference manual
- * (RM0008).
- * - It is also suitable for users who need to define their own events.
- * - Limitations:
- * - If an error occurs (ie. error flags are set besides to the monitored flags),
- * the I2C_CheckEvent() function may return SUCCESS despite the communication
- * hold or corrupted real state.
- * In this case, it is advised to use error interrupts to monitor the error
- * events and handle them in the interrupt IRQ handler.
- *
- * @note
- * For error management, it is advised to use the following functions:
- * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
- * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs.
- * Where x is the peripheral instance (I2C1, I2C2 ...)
- * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the I2Cx_ER_IRQHandler() function
- * in order to determine which error occured.
- * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() and/or I2C_GenerateStop()
- * in order to clear the error flag and source and return to correct
- * communication status.
- *
- *
- * 2) Advanced state monitoring:
- * Using the function I2C_GetLastEvent() which returns the image of both status
- * registers in a single word (uint32_t) (Status Register 2 value is shifted left
- * by 16 bits and concatenated to Status Register 1).
- * - When to use:
- * - This function is suitable for the same applications above but it allows to
- * overcome the limitations of I2C_GetFlagStatus() function (see below).
- * The returned value could be compared to events already defined in the
- * library (stm32f10x_i2c.h) or to custom values defined by user.
- * - This function is suitable when multiple flags are monitored at the same time.
- * - At the opposite of I2C_CheckEvent() function, this function allows user to
- * choose when an event is accepted (when all events flags are set and no
- * other flags are set or just when the needed flags are set like
- * I2C_CheckEvent() function).
- * - Limitations:
- * - User may need to define his own events.
- * - Same remark concerning the error management is applicable for this
- * function if user decides to check only regular communication flags (and
- * ignores error flags).
- *
- *
- * 3) Flag-based state monitoring:
- * Using the function I2C_GetFlagStatus() which simply returns the status of
- * one single flag (ie. I2C_FLAG_RXNE ...).
- * - When to use:
- * - This function could be used for specific applications or in debug phase.
- * - It is suitable when only one flag checking is needed (most I2C events
- * are monitored through multiple flags).
- * - Limitations:
- * - When calling this function, the Status register is accessed. Some flags are
- * cleared when the status register is accessed. So checking the status
- * of one Flag, may clear other ones.
- * - Function may need to be called twice or more in order to monitor one
- * single event.
- *
- */
-
-/**
- *
- * 1) Basic state monitoring
- *******************************************************************************
- */
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
-/**
- *
- * 2) Advanced state monitoring
- *******************************************************************************
- */
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
-/**
- *
- * 3) Flag-based state monitoring
- *******************************************************************************
- */
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-/**
- *
- *******************************************************************************
- */
-
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32L1xx_I2C_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_pwr.h b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_pwr.h
deleted file mode 100644
index d96aa9e..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_pwr.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l1xx_pwr.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief This file contains all the functions prototypes for the PWR firmware
- * library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_PWR_H
-#define __STM32L1xx_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup PWR
- * @{
- */
-
-/** @defgroup PWR_Exported_Types
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Exported_Constants
- * @{
- */
-
-/** @defgroup PVD_detection_level
- * @{
- */
-
-#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
-#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
-#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
-#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
-#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
-#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
-#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
-#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 /* External input analog voltage
- (Compare internally to VREFINT) */
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
- ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
- ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
- ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
-/**
- * @}
- */
-
-/** @defgroup WakeUp_Pins
- * @{
- */
-
-#define PWR_WakeUpPin_1 ((uint32_t)0x00000000)
-#define PWR_WakeUpPin_2 ((uint32_t)0x00000004)
-#define PWR_WakeUpPin_3 ((uint32_t)0x00000008)
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \
- ((PIN) == PWR_WakeUpPin_2) || \
- ((PIN) == PWR_WakeUpPin_3))
-/**
- * @}
- */
-
-
-/** @defgroup Voltage_Scaling_Ranges
- * @{
- */
-
-#define PWR_VoltageScaling_Range1 PWR_CR_VOS_0
-#define PWR_VoltageScaling_Range2 PWR_CR_VOS_1
-#define PWR_VoltageScaling_Range3 PWR_CR_VOS
-
-#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_VoltageScaling_Range1) || \
- ((RANGE) == PWR_VoltageScaling_Range2) || \
- ((RANGE) == PWR_VoltageScaling_Range3))
-/**
- * @}
- */
-
-/** @defgroup Regulator_state_is_Sleep_STOP_mode
- * @{
- */
-
-#define PWR_Regulator_ON ((uint32_t)0x00000000)
-#define PWR_Regulator_LowPower PWR_CR_LPSDSR
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
- ((REGULATOR) == PWR_Regulator_LowPower))
-/**
- * @}
- */
-
-/** @defgroup SLEEP_mode_entry
- * @{
- */
-
-#define PWR_SLEEPEntry_WFI ((uint8_t)0x01)
-#define PWR_SLEEPEntry_WFE ((uint8_t)0x02)
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
-
-/**
- * @}
- */
-
-/** @defgroup STOP_mode_entry
- * @{
- */
-
-#define PWR_STOPEntry_WFI ((uint8_t)0x01)
-#define PWR_STOPEntry_WFE ((uint8_t)0x02)
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Flag
- * @{
- */
-
-#define PWR_FLAG_WU PWR_CSR_WUF
-#define PWR_FLAG_SB PWR_CSR_SBF
-#define PWR_FLAG_PVDO PWR_CSR_PVDO
-#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
-#define PWR_FLAG_VOS PWR_CSR_VOSF
-#define PWR_FLAG_REGLP PWR_CSR_REGLPF
-
-#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
- ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY) || \
- ((FLAG) == PWR_FLAG_VOS) || ((FLAG) == PWR_FLAG_REGLP))
-
-#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Exported_Functions
- * @{
- */
-
-void PWR_DeInit(void);
-void PWR_RTCAccessCmd(FunctionalState NewState);
-void PWR_PVDCmd(FunctionalState NewState);
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
-void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
-void PWR_FastWakeUpCmd(FunctionalState NewState);
-void PWR_UltraLowPowerCmd(FunctionalState NewState);
-void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling);
-void PWR_EnterLowPowerRunMode(FunctionalState NewState);
-void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry);
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
-void PWR_EnterSTANDBYMode(void);
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
-void PWR_ClearFlag(uint32_t PWR_FLAG);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_PWR_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_rcc.h b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_rcc.h
deleted file mode 100644
index a9b949c..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_rcc.h
+++ /dev/null
@@ -1,471 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l1xx_rcc.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief This file contains all the functions prototypes for the RCC
- * firmware library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_RCC_H
-#define __STM32L1xx_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup RCC
- * @{
- */
-
-/** @defgroup RCC_Exported_Types
- * @{
- */
-
-typedef struct
-{
- uint32_t SYSCLK_Frequency;
- uint32_t HCLK_Frequency;
- uint32_t PCLK1_Frequency;
- uint32_t PCLK2_Frequency;
-}RCC_ClocksTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Exported_Constants
- * @{
- */
-
-/** @defgroup HSE_configuration
- * @{
- */
-
-#define RCC_HSE_OFF ((uint8_t)0x00)
-#define RCC_HSE_ON ((uint8_t)0x01)
-#define RCC_HSE_Bypass ((uint8_t)0x05)
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
- ((HSE) == RCC_HSE_Bypass))
-
-/**
- * @}
- */
-
-/** @defgroup MSI_Clock_Range
- * @{
- */
-
-#define RCC_MSIRange_64KHz RCC_ICSCR_MSIRANGE_64KHz
-#define RCC_MSIRange_128KHz RCC_ICSCR_MSIRANGE_128KHz
-#define RCC_MSIRange_256KHz RCC_ICSCR_MSIRANGE_256KHz
-#define RCC_MSIRange_512KHz RCC_ICSCR_MSIRANGE_512KHz
-#define RCC_MSIRange_1MHz RCC_ICSCR_MSIRANGE_1MHz
-#define RCC_MSIRange_2MHz RCC_ICSCR_MSIRANGE_2MHz
-#define RCC_MSIRange_4MHz RCC_ICSCR_MSIRANGE_4MHz
-
-#define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRange_64KHz) || \
- ((RANGE) == RCC_MSIRange_128KHz) || \
- ((RANGE) == RCC_MSIRange_256KHz) || \
- ((RANGE) == RCC_MSIRange_512KHz) || \
- ((RANGE) == RCC_MSIRange_1MHz) || \
- ((RANGE) == RCC_MSIRange_2MHz) || \
- ((RANGE) == RCC_MSIRange_4MHz))
-
-/**
- * @}
- */
-
-/** @defgroup PLL_Clock_Source
- * @{
- */
-
-#define RCC_PLLSource_HSI ((uint8_t)0x00)
-#define RCC_PLLSource_HSE ((uint8_t)0x01)
-
-#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
- ((SOURCE) == RCC_PLLSource_HSE))
-/**
- * @}
- */
-
-/** @defgroup PLL_Multiplication_Factor
- * @{
- */
-
-#define RCC_PLLMul_3 ((uint8_t)0x00)
-#define RCC_PLLMul_4 ((uint8_t)0x04)
-#define RCC_PLLMul_6 ((uint8_t)0x08)
-#define RCC_PLLMul_8 ((uint8_t)0x0C)
-#define RCC_PLLMul_12 ((uint8_t)0x10)
-#define RCC_PLLMul_16 ((uint8_t)0x14)
-#define RCC_PLLMul_24 ((uint8_t)0x18)
-#define RCC_PLLMul_32 ((uint8_t)0x1C)
-#define RCC_PLLMul_48 ((uint8_t)0x20)
-
-
-#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_3) || ((MUL) == RCC_PLLMul_4) || \
- ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_8) || \
- ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_16) || \
- ((MUL) == RCC_PLLMul_24) || ((MUL) == RCC_PLLMul_32) || \
- ((MUL) == RCC_PLLMul_48))
-/**
- * @}
- */
-
-/** @defgroup PLL_Divider_Factor
- * @{
- */
-
-#define RCC_PLLDiv_2 ((uint8_t)0x40)
-#define RCC_PLLDiv_3 ((uint8_t)0x80)
-#define RCC_PLLDiv_4 ((uint8_t)0xC0)
-
-
-#define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDiv_2) || ((DIV) == RCC_PLLDiv_3) || \
- ((DIV) == RCC_PLLDiv_4))
-/**
- * @}
- */
-
-/** @defgroup System_Clock_Source
- * @{
- */
-
-#define RCC_SYSCLKSource_MSI RCC_CFGR_SW_MSI
-#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
-#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
-#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
-#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_MSI) || \
- ((SOURCE) == RCC_SYSCLKSource_HSI) || \
- ((SOURCE) == RCC_SYSCLKSource_HSE) || \
- ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
-/**
- * @}
- */
-
-/** @defgroup AHB_Clock_Source
- * @{
- */
-
-#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
-#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
-#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
-#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
-#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
-#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
-#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
-#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
-#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
-#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
- ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
- ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
- ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
- ((HCLK) == RCC_SYSCLK_Div512))
-/**
- * @}
- */
-
-/** @defgroup APB1_APB2_Clock_Source
- * @{
- */
-
-#define RCC_HCLK_Div1 RCC_CFGR_PPRE1_DIV1
-#define RCC_HCLK_Div2 RCC_CFGR_PPRE1_DIV2
-#define RCC_HCLK_Div4 RCC_CFGR_PPRE1_DIV4
-#define RCC_HCLK_Div8 RCC_CFGR_PPRE1_DIV8
-#define RCC_HCLK_Div16 RCC_CFGR_PPRE1_DIV16
-#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
- ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
- ((PCLK) == RCC_HCLK_Div16))
-/**
- * @}
- */
-
-
-/** @defgroup RCC_Interrupt_Source
- * @{
- */
-
-#define RCC_IT_LSIRDY ((uint8_t)0x01)
-#define RCC_IT_LSERDY ((uint8_t)0x02)
-#define RCC_IT_HSIRDY ((uint8_t)0x04)
-#define RCC_IT_HSERDY ((uint8_t)0x08)
-#define RCC_IT_PLLRDY ((uint8_t)0x10)
-#define RCC_IT_MSIRDY ((uint8_t)0x20)
-#define RCC_IT_CSS ((uint8_t)0x80)
-
-#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
-
-#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
- ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
- ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \
- ((IT) == RCC_IT_CSS))
-
-#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
-
-/**
- * @}
- */
-
-/** @defgroup LSE_Configuration
- * @{
- */
-
-#define RCC_LSE_OFF ((uint8_t)0x00)
-#define RCC_LSE_ON ((uint8_t)0x01)
-#define RCC_LSE_Bypass ((uint8_t)0x05)
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
- ((LSE) == RCC_LSE_Bypass))
-/**
- * @}
- */
-
-/** @defgroup RTC_Clock_Source
- * @{
- */
-
-#define RCC_RTCCLKSource_LSE RCC_CSR_RTCSEL_LSE
-#define RCC_RTCCLKSource_LSI RCC_CSR_RTCSEL_LSI
-#define RCC_RTCCLKSource_HSE_Div2 RCC_CSR_RTCSEL_HSE
-#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0)
-#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1)
-#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE)
-#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
- ((SOURCE) == RCC_RTCCLKSource_LSI) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div16))
-/**
- * @}
- */
-
-/** @defgroup AHB_Peripherals
- * @{
- */
-
-#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
-#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
-#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
-#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
-#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN
-#define RCC_AHBPeriph_GPIOH RCC_AHBENR_GPIOHEN
-#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
-#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
-#define RCC_AHBPeriph_SRAM RCC_AHBLPENR_SRAMLPEN
-#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
-
-#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFEFF6FC0) == 0x00) && ((PERIPH) != 0x00))
-#define IS_RCC_AHB_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0xFEFE6FC0) == 0x00) && ((PERIPH) != 0x00))
-
-/**
- * @}
- */
-
-/** @defgroup APB2_Peripherals
- * @{
- */
-
-#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
-#define RCC_APB2Periph_TIM9 RCC_APB2ENR_TIM9EN
-#define RCC_APB2Periph_TIM10 RCC_APB2ENR_TIM10EN
-#define RCC_APB2Periph_TIM11 RCC_APB2ENR_TIM11EN
-#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN
-#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
-#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
-
-#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFADE2) == 0x00) && ((PERIPH) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup APB1_Peripherals
- * @{
- */
-
-#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
-#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
-#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN
-#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
-#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN
-#define RCC_APB1Periph_LCD RCC_APB1ENR_LCDEN
-#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
-#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
-#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
-#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN
-#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
-#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
-#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN
-#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
-#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN
-#define RCC_APB1Periph_COMP RCC_APB1ENR_COMPEN
-
-#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x4F19B5C8) == 0x00) && ((PERIPH) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup MCO_Clock_Source
- * @{
- */
-
-#define RCC_MCOSource_NoClock ((uint8_t)0x00)
-#define RCC_MCOSource_SYSCLK ((uint8_t)0x01)
-#define RCC_MCOSource_HSI ((uint8_t)0x02)
-#define RCC_MCOSource_MSI ((uint8_t)0x03)
-#define RCC_MCOSource_HSE ((uint8_t)0x04)
-#define RCC_MCOSource_PLLCLK ((uint8_t)0x05)
-#define RCC_MCOSource_LSI ((uint8_t)0x06)
-#define RCC_MCOSource_LSE ((uint8_t)0x07)
-
-#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_SYSCLK) || \
- ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_MSI) || \
- ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK) || \
- ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE))
-/**
- * @}
- */
-
-/** @defgroup MCO_Output_Divider
- * @{
- */
-
-#define RCC_MCODiv_1 ((uint8_t)0x00)
-#define RCC_MCODiv_2 ((uint8_t)0x10)
-#define RCC_MCODiv_4 ((uint8_t)0x20)
-#define RCC_MCODiv_8 ((uint8_t)0x30)
-#define RCC_MCODiv_16 ((uint8_t)0x40)
-
-#define IS_RCC_MCO_DIV(DIV) (((DIV) == RCC_MCODiv_1) || ((DIV) == RCC_MCODiv_2) || \
- ((DIV) == RCC_MCODiv_4) || ((DIV) == RCC_MCODiv_8) || \
- ((DIV) == RCC_MCODiv_16))
-/**
- * @}
- */
-
-/** @defgroup RCC_Flag
- * @{
- */
-
-#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
-#define RCC_FLAG_MSIRDY ((uint8_t)0x29)
-#define RCC_FLAG_HSERDY ((uint8_t)0x31)
-#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
-#define RCC_FLAG_LSERDY ((uint8_t)0x49)
-#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
-#define RCC_FLAG_OBLRST ((uint8_t)0x59)
-#define RCC_FLAG_PINRST ((uint8_t)0x5A)
-#define RCC_FLAG_PORRST ((uint8_t)0x5B)
-#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
-#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
-#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
-#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
-
-#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
- ((FLAG) == RCC_FLAG_MSIRDY) || ((FLAG) == RCC_FLAG_PLLRDY) || \
- ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || \
- ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
- ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
- ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
- ((FLAG) == RCC_FLAG_WWDGRST))
-
-#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
-#define IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Exported_Functions
- * @{
- */
-
-void RCC_DeInit(void);
-void RCC_HSEConfig(uint8_t RCC_HSE);
-ErrorStatus RCC_WaitForHSEStartUp(void);
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
-void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue);
-void RCC_MSIRangeConfig(uint32_t RCC_MSIRange);
-void RCC_MSICmd(FunctionalState NewState);
-void RCC_HSICmd(FunctionalState NewState);
-void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv);
-void RCC_PLLCmd(FunctionalState NewState);
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
-uint8_t RCC_GetSYSCLKSource(void);
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
-void RCC_PCLK1Config(uint32_t RCC_HCLK);
-void RCC_PCLK2Config(uint32_t RCC_HCLK);
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
-void RCC_LSEConfig(uint8_t RCC_LSE);
-void RCC_LSICmd(FunctionalState NewState);
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
-void RCC_RTCCLKCmd(FunctionalState NewState);
-void RCC_RTCResetCmd(FunctionalState NewState);
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
-void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
-void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
-void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv);
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
-void RCC_ClearFlag(void);
-ITStatus RCC_GetITStatus(uint8_t RCC_IT);
-void RCC_ClearITPendingBit(uint8_t RCC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_RCC_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_spi.h b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_spi.h
deleted file mode 100644
index 86a2b31..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_spi.h
+++ /dev/null
@@ -1,380 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l1xx_spi.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief This file contains all the functions prototypes for the SPI
- * firmware library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_SPI_H
-#define __STM32L1xx_SPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup SPI
- * @{
- */
-
-/** @defgroup SPI_Exported_Types
- * @{
- */
-
-/**
- * @brief SPI Init structure definition
- */
-
-typedef struct
-{
- uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
- This parameter can be any combination of @ref SPI_data_direction */
-
- uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
- This parameter can be any combination of @ref SPI_mode */
-
- uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
- This parameter can be any combination of @ref SPI_data_size */
-
- uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
- This parameter can be any combination of @ref SPI_Clock_Polarity */
-
- uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
- This parameter can be any combination of @ref SPI_Clock_Phase */
-
- uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
- hardware (NSS pin) or by software using the SSI bit.
- This parameter can be any combination of @ref SPI_Slave_Select_management */
-
- uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
- used to configure the transmit and receive SCK clock.
- This parameter can be any combination of @ref SPI_BaudRate_Prescaler.
- @note The communication clock is derived from the master
- clock. The slave clock does not need to be set. */
-
- uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be any combination of @ref SPI_MSB_LSB_transmission */
-
- uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
-}SPI_InitTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Exported_Constants
- * @{
- */
-
-#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
- ((PERIPH) == SPI2))
-
-/** @defgroup SPI_data_direction
- * @{
- */
-
-#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
-#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
-#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
-#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
-#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
- ((MODE) == SPI_Direction_2Lines_RxOnly) || \
- ((MODE) == SPI_Direction_1Line_Rx) || \
- ((MODE) == SPI_Direction_1Line_Tx))
-/**
- * @}
- */
-
-/** @defgroup SPI_mode
- * @{
- */
-
-#define SPI_Mode_Master ((uint16_t)0x0104)
-#define SPI_Mode_Slave ((uint16_t)0x0000)
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
- ((MODE) == SPI_Mode_Slave))
-/**
- * @}
- */
-
-/** @defgroup SPI_data_size
- * @{
- */
-
-#define SPI_DataSize_16b ((uint16_t)0x0800)
-#define SPI_DataSize_8b ((uint16_t)0x0000)
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
- ((DATASIZE) == SPI_DataSize_8b))
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Polarity
- * @{
- */
-
-#define SPI_CPOL_Low ((uint16_t)0x0000)
-#define SPI_CPOL_High ((uint16_t)0x0002)
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
- ((CPOL) == SPI_CPOL_High))
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Phase
- * @{
- */
-
-#define SPI_CPHA_1Edge ((uint16_t)0x0000)
-#define SPI_CPHA_2Edge ((uint16_t)0x0001)
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
- ((CPHA) == SPI_CPHA_2Edge))
-/**
- * @}
- */
-
-/** @defgroup SPI_Slave_Select_management
- * @{
- */
-
-#define SPI_NSS_Soft ((uint16_t)0x0200)
-#define SPI_NSS_Hard ((uint16_t)0x0000)
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
- ((NSS) == SPI_NSS_Hard))
-/**
- * @}
- */
-
-/** @defgroup SPI_BaudRate_Prescaler
- * @{
- */
-
-#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
-#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
-#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
-#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
-#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
-#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
-#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
-#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_256))
-/**
- * @}
- */
-
-/** @defgroup SPI_MSB_LSB_transmission
- * @{
- */
-
-#define SPI_FirstBit_MSB ((uint16_t)0x0000)
-#define SPI_FirstBit_LSB ((uint16_t)0x0080)
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
- ((BIT) == SPI_FirstBit_LSB))
-/**
- * @}
- */
-
-/** @defgroup SPI_DMA_transfer_requests
- * @{
- */
-
-#define SPI_DMAReq_Tx ((uint16_t)0x0002)
-#define SPI_DMAReq_Rx ((uint16_t)0x0001)
-#define IS_SPI_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup SPI_NSS_internal_software_mangement
- * @{
- */
-
-#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
-#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
-#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
- ((INTERNAL) == SPI_NSSInternalSoft_Reset))
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_Transmit_Receive
- * @{
- */
-
-#define SPI_CRC_Tx ((uint8_t)0x00)
-#define SPI_CRC_Rx ((uint8_t)0x01)
-#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
-/**
- * @}
- */
-
-/** @defgroup SPI_direction_transmit_receive
- * @{
- */
-
-#define SPI_Direction_Rx ((uint16_t)0xBFFF)
-#define SPI_Direction_Tx ((uint16_t)0x4000)
-#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
- ((DIRECTION) == SPI_Direction_Tx))
-/**
- * @}
- */
-
-/** @defgroup SPI_interrupts_definition
- * @{
- */
-
-#define SPI_IT_TXE ((uint8_t)0x71)
-#define SPI_IT_RXNE ((uint8_t)0x60)
-#define SPI_IT_ERR ((uint8_t)0x50)
-#define IS_SPI_CONFIG_IT(IT) (((IT) == SPI_IT_TXE) || \
- ((IT) == SPI_IT_RXNE) || \
- ((IT) == SPI_IT_ERR))
-#define SPI_IT_OVR ((uint8_t)0x56)
-#define SPI_IT_MODF ((uint8_t)0x55)
-#define SPI_IT_CRCERR ((uint8_t)0x54)
-#define IS_SPI_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
-#define IS_SPI_GET_IT(IT) (((IT) == SPI_IT_RXNE) || ((IT) == SPI_IT_TXE) || \
- ((IT) == SPI_IT_CRCERR) || \
- ((IT) == SPI_IT_MODF) || ((IT) == SPI_IT_OVR))
-/**
- * @}
- */
-
-/** @defgroup SPI_flags_definition
- * @{
- */
-
-#define SPI_FLAG_RXNE ((uint16_t)0x0001)
-#define SPI_FLAG_TXE ((uint16_t)0x0002)
-#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
-#define SPI_FLAG_MODF ((uint16_t)0x0020)
-#define SPI_FLAG_OVR ((uint16_t)0x0040)
-#define SPI_FLAG_BSY ((uint16_t)0x0080)
-#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
-#define IS_SPI_GET_FLAG(FLAG) (((FLAG) == SPI_FLAG_BSY) || ((FLAG) == SPI_FLAG_OVR) || \
- ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
- ((FLAG) == SPI_FLAG_TXE) || ((FLAG) == SPI_FLAG_RXNE))
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_polynomial
- * @{
- */
-
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
-/**
- * @}
- */
-
-/** @defgroup SPI_Legacy
- * @{
- */
-
-#define SPI_I2S_DMAReq_Tx SPI_DMAReq_Tx
-#define SPI_I2S_DMAReq_Rx SPI_DMAReq_Rx
-#define SPI_I2S_IT_TXE SPI_IT_TXE
-#define SPI_I2S_IT_RXNE SPI_IT_RXNE
-#define SPI_I2S_IT_ERR SPI_IT_ERR
-#define SPI_I2S_IT_OVR SPI_IT_OVR
-#define SPI_I2S_FLAG_RXNE SPI_FLAG_RXNE
-#define SPI_I2S_FLAG_TXE SPI_FLAG_TXE
-#define SPI_I2S_FLAG_OVR SPI_FLAG_OVR
-#define SPI_I2S_FLAG_BSY SPI_FLAG_BSY
-#define SPI_I2S_DeInit SPI_DeInit
-#define SPI_I2S_ITConfig SPI_ITConfig
-#define SPI_I2S_DMACmd SPI_DMACmd
-#define SPI_I2S_SendData SPI_SendData
-#define SPI_I2S_ReceiveData SPI_ReceiveData
-#define SPI_I2S_GetFlagStatus SPI_GetFlagStatus
-#define SPI_I2S_ClearFlag SPI_ClearFlag
-#define SPI_I2S_GetITStatus SPI_GetITStatus
-#define SPI_I2S_ClearITPendingBit SPI_ClearITPendingBit
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Exported_Functions
- * @{
- */
-
-void SPI_DeInit(SPI_TypeDef* SPIx);
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_IT, FunctionalState NewState);
-void SPI_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_DMAReq, FunctionalState NewState);
-void SPI_SendData(SPI_TypeDef* SPIx, uint16_t Data);
-uint16_t SPI_ReceiveData(SPI_TypeDef* SPIx);
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
-void SPI_TransmitCRC(SPI_TypeDef* SPIx);
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
-FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_FLAG);
-void SPI_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_FLAG);
-ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT);
-void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32l15x_SPI_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_syscfg.h b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_syscfg.h
deleted file mode 100644
index cd51e92..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_syscfg.h
+++ /dev/null
@@ -1,381 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l1xx_syscfg.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief This file contains all the functions prototypes for the SYSCFG
- * firmware library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/*!< Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_SYSCFG_H
-#define __STM32L1xx_SYSCFG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*!< Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup SYSCFG
- * @{
- */
-
-/** @defgroup SYSCFG_Exported_Types
- * @{
- */
-
-/** @defgroup EXTI_Port_Sources
- * @{
- */
-#define EXTI_PortSourceGPIOA ((uint8_t)0x00)
-#define EXTI_PortSourceGPIOB ((uint8_t)0x01)
-#define EXTI_PortSourceGPIOC ((uint8_t)0x02)
-#define EXTI_PortSourceGPIOD ((uint8_t)0x03)
-#define EXTI_PortSourceGPIOE ((uint8_t)0x04)
-#define EXTI_PortSourceGPIOH ((uint8_t)0x05)
-
-#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOH))
-/**
- * @}
- */
-
-/** @defgroup EXTI_Pin_sources
- * @{
- */
-#define EXTI_PinSource0 ((uint8_t)0x00)
-#define EXTI_PinSource1 ((uint8_t)0x01)
-#define EXTI_PinSource2 ((uint8_t)0x02)
-#define EXTI_PinSource3 ((uint8_t)0x03)
-#define EXTI_PinSource4 ((uint8_t)0x04)
-#define EXTI_PinSource5 ((uint8_t)0x05)
-#define EXTI_PinSource6 ((uint8_t)0x06)
-#define EXTI_PinSource7 ((uint8_t)0x07)
-#define EXTI_PinSource8 ((uint8_t)0x08)
-#define EXTI_PinSource9 ((uint8_t)0x09)
-#define EXTI_PinSource10 ((uint8_t)0x0A)
-#define EXTI_PinSource11 ((uint8_t)0x0B)
-#define EXTI_PinSource12 ((uint8_t)0x0C)
-#define EXTI_PinSource13 ((uint8_t)0x0D)
-#define EXTI_PinSource14 ((uint8_t)0x0E)
-#define EXTI_PinSource15 ((uint8_t)0x0F)
-#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
- ((PINSOURCE) == EXTI_PinSource1) || \
- ((PINSOURCE) == EXTI_PinSource2) || \
- ((PINSOURCE) == EXTI_PinSource3) || \
- ((PINSOURCE) == EXTI_PinSource4) || \
- ((PINSOURCE) == EXTI_PinSource5) || \
- ((PINSOURCE) == EXTI_PinSource6) || \
- ((PINSOURCE) == EXTI_PinSource7) || \
- ((PINSOURCE) == EXTI_PinSource8) || \
- ((PINSOURCE) == EXTI_PinSource9) || \
- ((PINSOURCE) == EXTI_PinSource10) || \
- ((PINSOURCE) == EXTI_PinSource11) || \
- ((PINSOURCE) == EXTI_PinSource12) || \
- ((PINSOURCE) == EXTI_PinSource13) || \
- ((PINSOURCE) == EXTI_PinSource14) || \
- ((PINSOURCE) == EXTI_PinSource15))
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_Memory_Remap_Config
- * @{
- */
-#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
-#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)
-#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
-
-#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
- ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
- ((REMAP) == SYSCFG_MemoryRemap_SRAM))
-
-
-/** @defgroup RI_Resistor
- * @{
- */
-
-#define RI_Resistor_10KPU COMP_CSR_10KPU
-#define RI_Resistor_400KPU COMP_CSR_400KPU
-#define RI_Resistor_10KPD COMP_CSR_10KPD
-#define RI_Resistor_400KPD COMP_CSR_400KPD
-
-#define IS_RI_RESISTOR(RESISTOR) (((RESISTOR) == COMP_CSR_10KPU) || \
- ((RESISTOR) == COMP_CSR_400KPU) || \
- ((RESISTOR) == COMP_CSR_10KPD) || \
- ((RESISTOR) == COMP_CSR_400KPD))
-
-/**
- * @}
- */
-
-/** @defgroup RI_InputCapture
- * @{
- */
-
-#define RI_InputCapture_IC1 RI_ICR_IC1 /*!< Input Capture 1 */
-#define RI_InputCapture_IC2 RI_ICR_IC2 /*!< Input Capture 2 */
-#define RI_InputCapture_IC3 RI_ICR_IC3 /*!< Input Capture 3 */
-#define RI_InputCapture_IC4 RI_ICR_IC4 /*!< Input Capture 4 */
-
-#define IS_RI_INPUTCAPTURE(INPUTCAPTURE) ((((INPUTCAPTURE) & (uint32_t)0xFFC2FFFF) == 0x00) && ((INPUTCAPTURE) != (uint32_t)0x00))
-/**
- * @}
- */
-
-/** @defgroup TIM_Select
- * @{
- */
-
-#define TIM_Select_None ((uint32_t)0x00000000) /*!< None selected */
-#define TIM_Select_TIM2 ((uint32_t)0x00010000) /*!< Timer 2 selected */
-#define TIM_Select_TIM3 ((uint32_t)0x00020000) /*!< Timer 3 selected */
-#define TIM_Select_TIM4 ((uint32_t)0x00030000) /*!< Timer 4 selected */
-
-#define IS_RI_TIM(TIM) (((TIM) == TIM_Select_None) || \
- ((TIM) == TIM_Select_TIM2) || \
- ((TIM) == TIM_Select_TIM3) || \
- ((TIM) == TIM_Select_TIM4))
-
-/**
- * @}
- */
-
-/** @defgroup RI_InputCaptureRouting
- * @{
- */
- /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */
-#define RI_InputCaptureRouting_0 ((uint32_t)0x00000000) /* PA0 PA1 PA2 PA3 */
-#define RI_InputCaptureRouting_1 ((uint32_t)0x00000001) /* PA4 PA5 PA6 PA7 */
-#define RI_InputCaptureRouting_2 ((uint32_t)0x00000002) /* PA8 PA9 PA10 PA11 */
-#define RI_InputCaptureRouting_3 ((uint32_t)0x00000003) /* PA12 PA13 PA14 PA15 */
-#define RI_InputCaptureRouting_4 ((uint32_t)0x00000004) /* PC0 PC1 PC2 PC3 */
-#define RI_InputCaptureRouting_5 ((uint32_t)0x00000005) /* PC4 PC5 PC6 PC7 */
-#define RI_InputCaptureRouting_6 ((uint32_t)0x00000006) /* PC8 PC9 PC10 PC11 */
-#define RI_InputCaptureRouting_7 ((uint32_t)0x00000007) /* PC12 PC13 PC14 PC15 */
-#define RI_InputCaptureRouting_8 ((uint32_t)0x00000008) /* PD0 PD1 PD2 PD3 */
-#define RI_InputCaptureRouting_9 ((uint32_t)0x00000009) /* PD4 PD5 PD6 PD7 */
-#define RI_InputCaptureRouting_10 ((uint32_t)0x0000000A) /* PD8 PD9 PD10 PD11 */
-#define RI_InputCaptureRouting_11 ((uint32_t)0x0000000B) /* PD12 PD13 PD14 PD15 */
-#define RI_InputCaptureRouting_12 ((uint32_t)0x0000000C) /* PE0 PE1 PE2 PE3 */
-#define RI_InputCaptureRouting_13 ((uint32_t)0x0000000D) /* PE4 PE5 PE6 PE7 */
-#define RI_InputCaptureRouting_14 ((uint32_t)0x0000000E) /* PE8 PE9 PE10 PE11 */
-#define RI_InputCaptureRouting_15 ((uint32_t)0x0000000F) /* PE12 PE13 PE14 PE15 */
-
-#define IS_RI_INPUTCAPTURE_ROUTING(ROUTING) (((ROUTING) == RI_InputCaptureRouting_0) || \
- ((ROUTING) == RI_InputCaptureRouting_1) || \
- ((ROUTING) == RI_InputCaptureRouting_2) || \
- ((ROUTING) == RI_InputCaptureRouting_3) || \
- ((ROUTING) == RI_InputCaptureRouting_4) || \
- ((ROUTING) == RI_InputCaptureRouting_5) || \
- ((ROUTING) == RI_InputCaptureRouting_6) || \
- ((ROUTING) == RI_InputCaptureRouting_7) || \
- ((ROUTING) == RI_InputCaptureRouting_8) || \
- ((ROUTING) == RI_InputCaptureRouting_9) || \
- ((ROUTING) == RI_InputCaptureRouting_10) || \
- ((ROUTING) == RI_InputCaptureRouting_11) || \
- ((ROUTING) == RI_InputCaptureRouting_12) || \
- ((ROUTING) == RI_InputCaptureRouting_13) || \
- ((ROUTING) == RI_InputCaptureRouting_14) || \
- ((ROUTING) == RI_InputCaptureRouting_15))
-
-/**
- * @}
- */
-
-/** @defgroup RI_IOSwitch
- * @{
- */
-
-/* ASCR1 I/O switch: bit 28 is set to '1' to indicate that the mask is in ASCR1 register */
-#define RI_IOSwitch_CH0 ((uint32_t)0x10000001)
-#define RI_IOSwitch_CH1 ((uint32_t)0x10000002)
-#define RI_IOSwitch_CH2 ((uint32_t)0x10000004)
-#define RI_IOSwitch_CH3 ((uint32_t)0x10000008)
-#define RI_IOSwitch_CH4 ((uint32_t)0x10000010)
-#define RI_IOSwitch_CH5 ((uint32_t)0x10000020)
-#define RI_IOSwitch_CH6 ((uint32_t)0x10000040)
-#define RI_IOSwitch_CH7 ((uint32_t)0x10000080)
-#define RI_IOSwitch_CH8 ((uint32_t)0x10000100)
-#define RI_IOSwitch_CH9 ((uint32_t)0x10000200)
-#define RI_IOSwitch_CH10 ((uint32_t)0x10000400)
-#define RI_IOSwitch_CH11 ((uint32_t)0x10000800)
-#define RI_IOSwitch_CH12 ((uint32_t)0x10001000)
-#define RI_IOSwitch_CH13 ((uint32_t)0x10002000)
-#define RI_IOSwitch_CH14 ((uint32_t)0x10004000)
-#define RI_IOSwitch_CH15 ((uint32_t)0x10008000)
-#define RI_IOSwitch_CH18 ((uint32_t)0x10040000)
-#define RI_IOSwitch_CH19 ((uint32_t)0x10080000)
-#define RI_IOSwitch_CH20 ((uint32_t)0x10100000)
-#define RI_IOSwitch_CH21 ((uint32_t)0x10200000)
-#define RI_IOSwitch_CH22 ((uint32_t)0x10400000)
-#define RI_IOSwitch_CH23 ((uint32_t)0x10800000)
-#define RI_IOSwitch_CH24 ((uint32_t)0x11000000)
-#define RI_IOSwitch_CH25 ((uint32_t)0x12000000)
-#define RI_IOSwitch_VCOMP ((uint32_t)0x14000000) /* VCOMP is an internal switch used to connect
- selected channel to COMP1 non inverting input */
-
-/* ASCR2 IO switch: : bit 28 is set to '0' to indicate that the mask is in ASCR2 register */
-#define RI_IOSwitch_GR10_1 ((uint32_t)0x00000001)
-#define RI_IOSwitch_GR10_2 ((uint32_t)0x00000002)
-#define RI_IOSwitch_GR10_3 ((uint32_t)0x00000004)
-#define RI_IOSwitch_GR10_4 ((uint32_t)0x00000008)
-#define RI_IOSwitch_GR6_1 ((uint32_t)0x00000010)
-#define RI_IOSwitch_GR6_2 ((uint32_t)0x00000020)
-#define RI_IOSwitch_GR5_1 ((uint32_t)0x00000040)
-#define RI_IOSwitch_GR5_2 ((uint32_t)0x00000080)
-#define RI_IOSwitch_GR5_3 ((uint32_t)0x00000100)
-#define RI_IOSwitch_GR4_1 ((uint32_t)0x00000200)
-#define RI_IOSwitch_GR4_2 ((uint32_t)0x00000400)
-#define RI_IOSwitch_GR4_3 ((uint32_t)0x00000800)
-
-#define IS_RI_IOSWITCH(IOSWITCH) (((IOSWITCH) == RI_IOSwitch_CH0) || \
- ((IOSWITCH) == RI_IOSwitch_CH1) || \
- ((IOSWITCH) == RI_IOSwitch_CH2) || \
- ((IOSWITCH) == RI_IOSwitch_CH3) || \
- ((IOSWITCH) == RI_IOSwitch_CH4) || \
- ((IOSWITCH) == RI_IOSwitch_CH5) || \
- ((IOSWITCH) == RI_IOSwitch_CH6) || \
- ((IOSWITCH) == RI_IOSwitch_CH7) || \
- ((IOSWITCH) == RI_IOSwitch_CH8) || \
- ((IOSWITCH) == RI_IOSwitch_CH9) || \
- ((IOSWITCH) == RI_IOSwitch_CH10) || \
- ((IOSWITCH) == RI_IOSwitch_CH11) || \
- ((IOSWITCH) == RI_IOSwitch_CH12) || \
- ((IOSWITCH) == RI_IOSwitch_CH13) || \
- ((IOSWITCH) == RI_IOSwitch_CH14) || \
- ((IOSWITCH) == RI_IOSwitch_CH15) || \
- ((IOSWITCH) == RI_IOSwitch_CH18) || \
- ((IOSWITCH) == RI_IOSwitch_CH19) || \
- ((IOSWITCH) == RI_IOSwitch_CH20) || \
- ((IOSWITCH) == RI_IOSwitch_CH21) || \
- ((IOSWITCH) == RI_IOSwitch_CH22) || \
- ((IOSWITCH) == RI_IOSwitch_CH23) || \
- ((IOSWITCH) == RI_IOSwitch_CH24) || \
- ((IOSWITCH) == RI_IOSwitch_CH25) || \
- ((IOSWITCH) == RI_IOSwitch_VCOMP) || \
- ((IOSWITCH) == RI_IOSwitch_GR10_1) || \
- ((IOSWITCH) == RI_IOSwitch_GR10_2) || \
- ((IOSWITCH) == RI_IOSwitch_GR10_3) || \
- ((IOSWITCH) == RI_IOSwitch_GR10_4) || \
- ((IOSWITCH) == RI_IOSwitch_GR6_1) || \
- ((IOSWITCH) == RI_IOSwitch_GR6_2) || \
- ((IOSWITCH) == RI_IOSwitch_GR5_1) || \
- ((IOSWITCH) == RI_IOSwitch_GR5_2) || \
- ((IOSWITCH) == RI_IOSwitch_GR5_3) || \
- ((IOSWITCH) == RI_IOSwitch_GR4_1) || \
- ((IOSWITCH) == RI_IOSwitch_GR4_2) || \
- ((IOSWITCH) == RI_IOSwitch_GR4_3))
-
-/** @defgroup RI_Port
- * @{
- */
-
-#define RI_PortA ((uint8_t)0x01) /*!< GPIOA selected */
-#define RI_PortB ((uint8_t)0x02) /*!< GPIOB selected */
-#define RI_PortC ((uint8_t)0x03) /*!< GPIOC selected */
-#define RI_PortD ((uint8_t)0x04) /*!< GPIOD selected */
-#define RI_PortE ((uint8_t)0x05) /*!< GPIOE selected */
-
-#define IS_RI_PORT(PORT) (((PORT) == RI_PortA) || \
- ((PORT) == RI_PortB) || \
- ((PORT) == RI_PortC) || \
- ((PORT) == RI_PortD) || \
- ((PORT) == RI_PortE))
-/**
- * @}
- */
-
-/** @defgroup RI_Pin define
- * @{
- */
-#define RI_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
-#define RI_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
-#define RI_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
-#define RI_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
-#define RI_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
-#define RI_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
-#define RI_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
-#define RI_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
-#define RI_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
-#define RI_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
-#define RI_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
-#define RI_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
-#define RI_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
-#define RI_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
-#define RI_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
-#define RI_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
-#define RI_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
-
-#define IS_RI_PIN(PIN) ((PIN) != (uint16_t)0x00)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_Exported_Functions
- * @{
- */
-void SYSCFG_DeInit(void);
-void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);
-void SYSCFG_USBPuCmd(FunctionalState NewState);
-void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
-void SYSCFG_RIDeInit(void);
-void SYSCFG_RITIMSelect(uint32_t TIM_Select);
-void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting);
-void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState);
-void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState);
-void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState);
-void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin,
- FunctionalState NewState);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32L1xx_SYSCFG_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_tim.h b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_tim.h
deleted file mode 100644
index 7541e09..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_tim.h
+++ /dev/null
@@ -1,901 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l1xx_tim.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief This file contains all the functions prototypes for the TIM firmware
- * library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_TIM_H
-#define __STM32L1xx_TIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup TIM
- * @{
- */
-
-/** @defgroup TIM_Exported_Types
- * @{
- */
-
-/**
- * @brief TIM Time Base Init structure definition
- * @note This sturcture is used with all TIMx except for TIM6 and TIM7.
- */
-
-typedef struct
-{
- uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
- This parameter can be a number between 0x0000 and 0xFFFF */
-
- uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
- This parameter can be a value of @ref TIM_Counter_Mode */
-
- uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active
- Auto-Reload Register at the next update event.
- This parameter must be a number between 0x0000 and 0xFFFF. */
-
- uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
- This parameter can be a value of @ref TIM_Clock_Division_CKD */
-
-} TIM_TimeBaseInitTypeDef;
-
-/**
- * @brief TIM Output Compare Init structure definition
- */
-
-typedef struct
-{
- uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
- uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
- This parameter can be a value of @ref TIM_Output_Compare_state */
-
- uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between 0x0000 and 0xFFFF */
-
- uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
-} TIM_OCInitTypeDef;
-
-/**
- * @brief TIM Input Capture Init structure definition
- */
-
-typedef struct
-{
-
- uint16_t TIM_Channel; /*!< Specifies the TIM channel.
- This parameter can be a value of @ref TIM_Channel */
-
- uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint16_t TIM_ICSelection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between 0x0 and 0xF */
-} TIM_ICInitTypeDef;
-
-/**
- * @}
- */
-
-
-/** @defgroup TIM_Exported_constants
- * @{
- */
-
-#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM6) || \
- ((PERIPH) == TIM7) || \
- ((PERIPH) == TIM9) || \
- ((PERIPH) == TIM10) || \
- ((PERIPH) == TIM11))
-
-
-#define IS_TIM_23491011_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM9) || \
- ((PERIPH) == TIM10) || \
- ((PERIPH) == TIM11))
-
-#define IS_TIM_234_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4))
-
-#define IS_TIM_2349_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) ||\
- ((PERIPH) == TIM9))
-
-#define IS_TIM_234679_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) ||\
- ((PERIPH) == TIM6) || \
- ((PERIPH) == TIM7) ||\
- ((PERIPH) == TIM9))
-
-#define IS_TIM_23467_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) ||\
- ((PERIPH) == TIM6) || \
- ((PERIPH) == TIM7))
-
-#define IS_TIM_91011_PERIPH(PERIPH) (((PERIPH) == TIM9) || \
- ((PERIPH) == TIM10) ||\
- ((PERIPH) == TIM11))
-
-
-
-/** @defgroup TIM_Output_Compare_and_PWM_modes
- * @{
- */
-
-#define TIM_OCMode_Timing ((uint16_t)0x0000)
-#define TIM_OCMode_Active ((uint16_t)0x0010)
-#define TIM_OCMode_Inactive ((uint16_t)0x0020)
-#define TIM_OCMode_Toggle ((uint16_t)0x0030)
-#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
-#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
- ((MODE) == TIM_OCMode_Active) || \
- ((MODE) == TIM_OCMode_Inactive) || \
- ((MODE) == TIM_OCMode_Toggle)|| \
- ((MODE) == TIM_OCMode_PWM1) || \
- ((MODE) == TIM_OCMode_PWM2))
-#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
- ((MODE) == TIM_OCMode_Active) || \
- ((MODE) == TIM_OCMode_Inactive) || \
- ((MODE) == TIM_OCMode_Toggle)|| \
- ((MODE) == TIM_OCMode_PWM1) || \
- ((MODE) == TIM_OCMode_PWM2) || \
- ((MODE) == TIM_ForcedAction_Active) || \
- ((MODE) == TIM_ForcedAction_InActive))
-/**
- * @}
- */
-
-/** @defgroup TIM_One_Pulse_Mode
- * @{
- */
-
-#define TIM_OPMode_Single ((uint16_t)0x0008)
-#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
- ((MODE) == TIM_OPMode_Repetitive))
-/**
- * @}
- */
-
-/** @defgroup TIM_Channel
- * @{
- */
-
-#define TIM_Channel_1 ((uint16_t)0x0000)
-#define TIM_Channel_2 ((uint16_t)0x0004)
-#define TIM_Channel_3 ((uint16_t)0x0008)
-#define TIM_Channel_4 ((uint16_t)0x000C)
-
-#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
- ((CHANNEL) == TIM_Channel_2) || \
- ((CHANNEL) == TIM_Channel_3) || \
- ((CHANNEL) == TIM_Channel_4))
-
-#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
- ((CHANNEL) == TIM_Channel_2))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Division_CKD
- * @{
- */
-
-#define TIM_CKD_DIV1 ((uint16_t)0x0000)
-#define TIM_CKD_DIV2 ((uint16_t)0x0100)
-#define TIM_CKD_DIV4 ((uint16_t)0x0200)
-#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
- ((DIV) == TIM_CKD_DIV2) || \
- ((DIV) == TIM_CKD_DIV4))
-/**
- * @}
- */
-
-/** @defgroup TIM_Counter_Mode
- * @{
- */
-
-#define TIM_CounterMode_Up ((uint16_t)0x0000)
-#define TIM_CounterMode_Down ((uint16_t)0x0010)
-#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
-#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
-#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
- ((MODE) == TIM_CounterMode_Down) || \
- ((MODE) == TIM_CounterMode_CenterAligned1) || \
- ((MODE) == TIM_CounterMode_CenterAligned2) || \
- ((MODE) == TIM_CounterMode_CenterAligned3))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Polarity
- * @{
- */
-
-#define TIM_OCPolarity_High ((uint16_t)0x0000)
-#define TIM_OCPolarity_Low ((uint16_t)0x0002)
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
- ((POLARITY) == TIM_OCPolarity_Low))
-/**
- * @}
- */
-
-
-/** @defgroup TIM_Output_Compare_state
- * @{
- */
-
-#define TIM_OutputState_Disable ((uint16_t)0x0000)
-#define TIM_OutputState_Enable ((uint16_t)0x0001)
-#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
- ((STATE) == TIM_OutputState_Enable))
-/**
- * @}
- */
-
-
-/** @defgroup TIM_Capture_Compare_state
- * @{
- */
-
-#define TIM_CCx_Enable ((uint16_t)0x0001)
-#define TIM_CCx_Disable ((uint16_t)0x0000)
-#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
- ((CCX) == TIM_CCx_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Polarity
- * @{
- */
-
-#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
-#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
-#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
- ((POLARITY) == TIM_ICPolarity_Falling)|| \
- ((POLARITY) == TIM_ICPolarity_BothEdge))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Selection
- * @{
- */
-
-#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC2, IC1, IC4 or IC3, respectively. */
-#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
- ((SELECTION) == TIM_ICSelection_IndirectTI) || \
- ((SELECTION) == TIM_ICSelection_TRC))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Prescaler
- * @{
- */
-
-#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
-#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
-#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
-#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
- ((PRESCALER) == TIM_ICPSC_DIV2) || \
- ((PRESCALER) == TIM_ICPSC_DIV4) || \
- ((PRESCALER) == TIM_ICPSC_DIV8))
-/**
- * @}
- */
-
-/** @defgroup TIM_interrupt_sources
- * @{
- */
-
-#define TIM_IT_Update ((uint16_t)0x0001)
-#define TIM_IT_CC1 ((uint16_t)0x0002)
-#define TIM_IT_CC2 ((uint16_t)0x0004)
-#define TIM_IT_CC3 ((uint16_t)0x0008)
-#define TIM_IT_CC4 ((uint16_t)0x0010)
-#define TIM_IT_Trigger ((uint16_t)0x0040)
-#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFFA0) == 0x0000) && ((IT) != 0x0000))
-
-#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
- ((IT) == TIM_IT_CC1) || \
- ((IT) == TIM_IT_CC2) || \
- ((IT) == TIM_IT_CC3) || \
- ((IT) == TIM_IT_CC4) || \
- ((IT) == TIM_IT_Trigger))
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Base_address
- * @{
- */
-
-#define TIM_DMABase_CR1 ((uint16_t)0x0000)
-#define TIM_DMABase_CR2 ((uint16_t)0x0001)
-#define TIM_DMABase_SMCR ((uint16_t)0x0002)
-#define TIM_DMABase_DIER ((uint16_t)0x0003)
-#define TIM_DMABase_SR ((uint16_t)0x0004)
-#define TIM_DMABase_EGR ((uint16_t)0x0005)
-#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
-#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
-#define TIM_DMABase_CCER ((uint16_t)0x0008)
-#define TIM_DMABase_CNT ((uint16_t)0x0009)
-#define TIM_DMABase_PSC ((uint16_t)0x000A)
-#define TIM_DMABase_ARR ((uint16_t)0x000B)
-#define TIM_DMABase_RCR ((uint16_t)0x000C)
-#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
-#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
-#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
-#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
-#define TIM_DMABase_DCR ((uint16_t)0x0012)
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
- ((BASE) == TIM_DMABase_CR2) || \
- ((BASE) == TIM_DMABase_SMCR) || \
- ((BASE) == TIM_DMABase_DIER) || \
- ((BASE) == TIM_DMABase_SR) || \
- ((BASE) == TIM_DMABase_EGR) || \
- ((BASE) == TIM_DMABase_CCMR1) || \
- ((BASE) == TIM_DMABase_CCMR2) || \
- ((BASE) == TIM_DMABase_CCER) || \
- ((BASE) == TIM_DMABase_CNT) || \
- ((BASE) == TIM_DMABase_PSC) || \
- ((BASE) == TIM_DMABase_ARR) || \
- ((BASE) == TIM_DMABase_CCR1) || \
- ((BASE) == TIM_DMABase_CCR2) || \
- ((BASE) == TIM_DMABase_CCR3) || \
- ((BASE) == TIM_DMABase_CCR4) || \
- ((BASE) == TIM_DMABase_DCR))
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Burst_Length
- * @{
- */
-
-#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000)
-#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100)
-#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200)
-#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300)
-#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400)
-#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500)
-#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600)
-#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700)
-#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800)
-#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900)
-#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00)
-#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00)
-#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00)
-#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00)
-#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00)
-#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00)
-#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000)
-#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100)
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \
- ((LENGTH) == TIM_DMABurstLength_2Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_3Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_4Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_5Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_6Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_7Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_8Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_9Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_10Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_11Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_12Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_13Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_14Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_15Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_16Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_17Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_18Bytes))
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_sources
- * @{
- */
-
-#define TIM_DMA_Update ((uint16_t)0x0100)
-#define TIM_DMA_CC1 ((uint16_t)0x0200)
-#define TIM_DMA_CC2 ((uint16_t)0x0400)
-#define TIM_DMA_CC3 ((uint16_t)0x0800)
-#define TIM_DMA_CC4 ((uint16_t)0x1000)
-#define TIM_DMA_Trigger ((uint16_t)0x4000)
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_External_Trigger_Prescaler
- * @{
- */
-
-#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
-#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
-#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
-#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
-#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
- ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
- ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
- ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
-/**
- * @}
- */
-
-/** @defgroup TIM_Internal_Trigger_Selection
- * @{
- */
-
-#define TIM_TS_ITR0 ((uint16_t)0x0000)
-#define TIM_TS_ITR1 ((uint16_t)0x0010)
-#define TIM_TS_ITR2 ((uint16_t)0x0020)
-#define TIM_TS_ITR3 ((uint16_t)0x0030)
-#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
-#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
-#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
-#define TIM_TS_ETRF ((uint16_t)0x0070)
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3) || \
- ((SELECTION) == TIM_TS_TI1F_ED) || \
- ((SELECTION) == TIM_TS_TI1FP1) || \
- ((SELECTION) == TIM_TS_TI2FP2) || \
- ((SELECTION) == TIM_TS_ETRF))
-#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3))
-/**
- * @}
- */
-
-/** @defgroup TIM_TIx_External_Clock_Source
- * @{
- */
-
-#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
-#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
-#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_External_Trigger_Polarity
- * @{
- */
-#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
-#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
-#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
- ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
-/**
- * @}
- */
-
-/** @defgroup TIM_Prescaler_Reload_Mode
- * @{
- */
-
-#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
-#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
-#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
- ((RELOAD) == TIM_PSCReloadMode_Immediate))
-/**
- * @}
- */
-
-/** @defgroup TIM_Forced_Action
- * @{
- */
-
-#define TIM_ForcedAction_Active ((uint16_t)0x0050)
-#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
-#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
- ((ACTION) == TIM_ForcedAction_InActive))
-/**
- * @}
- */
-
-/** @defgroup TIM_Encoder_Mode
- * @{
- */
-
-#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
-#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
-#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
- ((MODE) == TIM_EncoderMode_TI2) || \
- ((MODE) == TIM_EncoderMode_TI12))
-/**
- * @}
- */
-
-
-/** @defgroup TIM_Event_Source
- * @{
- */
-
-#define TIM_EventSource_Update ((uint16_t)0x0001)
-#define TIM_EventSource_CC1 ((uint16_t)0x0002)
-#define TIM_EventSource_CC2 ((uint16_t)0x0004)
-#define TIM_EventSource_CC3 ((uint16_t)0x0008)
-#define TIM_EventSource_CC4 ((uint16_t)0x0010)
-#define TIM_EventSource_Trigger ((uint16_t)0x0040)
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFFA0) == 0x0000) && ((SOURCE) != 0x0000))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Update_Source
- * @{
- */
-
-#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
- or the setting of UG bit, or an update generation
- through the slave mode controller. */
-#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
-#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
- ((SOURCE) == TIM_UpdateSource_Regular))
-/**
- * @}
- */
-
-/** @defgroup TIM_Ouput_Compare_Preload_State
- * @{
- */
-
-#define TIM_OCPreload_Enable ((uint16_t)0x0008)
-#define TIM_OCPreload_Disable ((uint16_t)0x0000)
-#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
- ((STATE) == TIM_OCPreload_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Ouput_Compare_Fast_State
- * @{
- */
-
-#define TIM_OCFast_Enable ((uint16_t)0x0004)
-#define TIM_OCFast_Disable ((uint16_t)0x0000)
-#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
- ((STATE) == TIM_OCFast_Disable))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Ouput_Compare_Clear_State
- * @{
- */
-
-#define TIM_OCClear_Enable ((uint16_t)0x0080)
-#define TIM_OCClear_Disable ((uint16_t)0x0000)
-#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
- ((STATE) == TIM_OCClear_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Output_Source
- * @{
- */
-
-#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
-#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
-#define TIM_TRGOSource_Update ((uint16_t)0x0020)
-#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
-#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
-#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
-#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
-#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
- ((SOURCE) == TIM_TRGOSource_Enable) || \
- ((SOURCE) == TIM_TRGOSource_Update) || \
- ((SOURCE) == TIM_TRGOSource_OC1) || \
- ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
- ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
- ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
- ((SOURCE) == TIM_TRGOSource_OC4Ref))
-/**
- * @}
- */
-
-/** @defgroup TIM_Slave_Mode
- * @{
- */
-
-#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
-#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
-#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
-#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
- ((MODE) == TIM_SlaveMode_Gated) || \
- ((MODE) == TIM_SlaveMode_Trigger) || \
- ((MODE) == TIM_SlaveMode_External1))
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Slave_Mode
- * @{
- */
-
-#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
-#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
- ((STATE) == TIM_MasterSlaveMode_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Flags
- * @{
- */
-
-#define TIM_FLAG_Update ((uint16_t)0x0001)
-#define TIM_FLAG_CC1 ((uint16_t)0x0002)
-#define TIM_FLAG_CC2 ((uint16_t)0x0004)
-#define TIM_FLAG_CC3 ((uint16_t)0x0008)
-#define TIM_FLAG_CC4 ((uint16_t)0x0010)
-#define TIM_FLAG_Trigger ((uint16_t)0x0040)
-#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
-#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
-#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
-#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
-#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
- ((FLAG) == TIM_FLAG_CC1) || \
- ((FLAG) == TIM_FLAG_CC2) || \
- ((FLAG) == TIM_FLAG_CC3) || \
- ((FLAG) == TIM_FLAG_CC4) || \
- ((FLAG) == TIM_FLAG_Trigger) || \
- ((FLAG) == TIM_FLAG_CC1OF) || \
- ((FLAG) == TIM_FLAG_CC2OF) || \
- ((FLAG) == TIM_FLAG_CC3OF) || \
- ((FLAG) == TIM_FLAG_CC4OF))
-#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Filer_Value
- * @{
- */
-
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup TIM_External_Trigger_Filter
- * @{
- */
-
-#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup TIM_OCReferenceClear
- * @{
- */
-#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
-#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)
-#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
- ((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Remap
- * @{
- */
-
-#define TIM9_GPIO ((uint16_t)0x0000)
-#define TIM9_LSE ((uint16_t)0x0001)
-
-#define TIM10_GPIO ((uint16_t)0x0000)
-#define TIM10_LSI ((uint16_t)0x0001)
-#define TIM10_LSE ((uint16_t)0x0002)
-#define TIM10_RTC ((uint16_t)0x0003)
-
-#define TIM11_GPIO ((uint16_t)0x0000)
-#define TIM11_MSI ((uint16_t)0x0001)
-#define TIM11_HSE_RTC ((uint16_t)0x0002)
-
-#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM9_GPIO)||\
- ((TIM_REMAP) == TIM9_LSE)||\
- ((TIM_REMAP) == TIM10_GPIO)||\
- ((TIM_REMAP) == TIM10_LSI)||\
- ((TIM_REMAP) == TIM10_LSE)||\
- ((TIM_REMAP) == TIM10_RTC)||\
- ((TIM_REMAP) == TIM11_GPIO)||\
- ((TIM_REMAP) == TIM11_MSI)||\
- ((TIM_REMAP) == TIM11_HSE_RTC))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions
- * @{
- */
-
-void TIM_DeInit(TIM_TypeDef* TIMx);
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
- uint16_t TIM_ICPolarity, uint16_t ICFilter);
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter);
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter);
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
-uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
-void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
-void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
-
-#ifdef __cplusplus
-}
-#endif
-#endif /*__STM32L1xx_TIM_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_usart.h b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_usart.h
deleted file mode 100644
index c6a1416..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_usart.h
+++ /dev/null
@@ -1,399 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l1xx_usart.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief This file contains all the functions prototypes for the USART
- * firmware library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_USART_H
-#define __STM32L1xx_USART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup USART
- * @{
- */
-
-/** @defgroup USART_Exported_Types
- * @{
- */
-
-/**
- * @brief USART Init Structure definition
- */
-
-typedef struct
-{
- uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
- The baud rate is computed using the following formula:
- - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
- - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
-
- uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref USART_Word_Length */
-
- uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref USART_Stop_Bits */
-
- uint16_t USART_Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref USART_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
-
- uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref USART_Mode */
-
- uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
- or disabled.
- This parameter can be a value of @ref USART_Hardware_Flow_Control */
-} USART_InitTypeDef;
-
-/**
- * @brief USART Clock Init Structure definition
- */
-
-typedef struct
-{
-
- uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
- This parameter can be a value of @ref USART_Clock */
-
- uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.
- This parameter can be a value of @ref USART_Clock_Polarity */
-
- uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref USART_Clock_Phase */
-
- uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.
- This parameter can be a value of @ref USART_Last_Bit */
-} USART_ClockInitTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup USART_Exported_Constants
- * @{
- */
-
-#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
- ((PERIPH) == USART2) || \
- ((PERIPH) == USART3))
-
-/** @defgroup USART_Word_Length
- * @{
- */
-
-#define USART_WordLength_8b ((uint16_t)0x0000)
-#define USART_WordLength_9b ((uint16_t)0x1000)
-
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
- ((LENGTH) == USART_WordLength_9b))
-/**
- * @}
- */
-
-/** @defgroup USART_Stop_Bits
- * @{
- */
-
-#define USART_StopBits_1 ((uint16_t)0x0000)
-#define USART_StopBits_0_5 ((uint16_t)0x1000)
-#define USART_StopBits_2 ((uint16_t)0x2000)
-#define USART_StopBits_1_5 ((uint16_t)0x3000)
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
- ((STOPBITS) == USART_StopBits_0_5) || \
- ((STOPBITS) == USART_StopBits_2) || \
- ((STOPBITS) == USART_StopBits_1_5))
-/**
- * @}
- */
-
-/** @defgroup USART_Parity
- * @{
- */
-
-#define USART_Parity_No ((uint16_t)0x0000)
-#define USART_Parity_Even ((uint16_t)0x0400)
-#define USART_Parity_Odd ((uint16_t)0x0600)
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
- ((PARITY) == USART_Parity_Even) || \
- ((PARITY) == USART_Parity_Odd))
-/**
- * @}
- */
-
-/** @defgroup USART_Mode
- * @{
- */
-
-#define USART_Mode_Rx ((uint16_t)0x0004)
-#define USART_Mode_Tx ((uint16_t)0x0008)
-#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
-/**
- * @}
- */
-
-/** @defgroup USART_Hardware_Flow_Control
- * @{
- */
-#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
-#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
-#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
-#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
-#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
- (((CONTROL) == USART_HardwareFlowControl_None) || \
- ((CONTROL) == USART_HardwareFlowControl_RTS) || \
- ((CONTROL) == USART_HardwareFlowControl_CTS) || \
- ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
-/**
- * @}
- */
-
-/** @defgroup USART_Clock
- * @{
- */
-#define USART_Clock_Disable ((uint16_t)0x0000)
-#define USART_Clock_Enable ((uint16_t)0x0800)
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
- ((CLOCK) == USART_Clock_Enable))
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Polarity
- * @{
- */
-
-#define USART_CPOL_Low ((uint16_t)0x0000)
-#define USART_CPOL_High ((uint16_t)0x0400)
-#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
-
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Phase
- * @{
- */
-
-#define USART_CPHA_1Edge ((uint16_t)0x0000)
-#define USART_CPHA_2Edge ((uint16_t)0x0200)
-#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
-
-/**
- * @}
- */
-
-/** @defgroup USART_Last_Bit
- * @{
- */
-
-#define USART_LastBit_Disable ((uint16_t)0x0000)
-#define USART_LastBit_Enable ((uint16_t)0x0100)
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
- ((LASTBIT) == USART_LastBit_Enable))
-/**
- * @}
- */
-
-/** @defgroup USART_Interrupt_definition
- * @{
- */
-
-#define USART_IT_PE ((uint16_t)0x0028)
-#define USART_IT_TXE ((uint16_t)0x0727)
-#define USART_IT_TC ((uint16_t)0x0626)
-#define USART_IT_RXNE ((uint16_t)0x0525)
-#define USART_IT_IDLE ((uint16_t)0x0424)
-#define USART_IT_LBD ((uint16_t)0x0846)
-#define USART_IT_CTS ((uint16_t)0x096A)
-#define USART_IT_ERR ((uint16_t)0x0060)
-#define USART_IT_ORE ((uint16_t)0x0360)
-#define USART_IT_NE ((uint16_t)0x0260)
-#define USART_IT_FE ((uint16_t)0x0160)
-#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
-#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
- ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
-#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
- ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
-/**
- * @}
- */
-
-/** @defgroup USART_DMA_Requests
- * @{
- */
-
-#define USART_DMAReq_Tx ((uint16_t)0x0080)
-#define USART_DMAReq_Rx ((uint16_t)0x0040)
-#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
-
-/**
- * @}
- */
-
-/** @defgroup USART_WakeUp_methods
- * @{
- */
-
-#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
-#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
-#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
- ((WAKEUP) == USART_WakeUp_AddressMark))
-/**
- * @}
- */
-
-/** @defgroup USART_LIN_Break_Detection_Length
- * @{
- */
-
-#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
-#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
-#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
- (((LENGTH) == USART_LINBreakDetectLength_10b) || \
- ((LENGTH) == USART_LINBreakDetectLength_11b))
-/**
- * @}
- */
-
-/** @defgroup USART_IrDA_Low_Power
- * @{
- */
-
-#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
-#define USART_IrDAMode_Normal ((uint16_t)0x0000)
-#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
- ((MODE) == USART_IrDAMode_Normal))
-/**
- * @}
- */
-
-/** @defgroup USART_Flags
- * @{
- */
-
-#define USART_FLAG_CTS ((uint16_t)0x0200)
-#define USART_FLAG_LBD ((uint16_t)0x0100)
-#define USART_FLAG_TXE ((uint16_t)0x0080)
-#define USART_FLAG_TC ((uint16_t)0x0040)
-#define USART_FLAG_RXNE ((uint16_t)0x0020)
-#define USART_FLAG_IDLE ((uint16_t)0x0010)
-#define USART_FLAG_ORE ((uint16_t)0x0008)
-#define USART_FLAG_NE ((uint16_t)0x0004)
-#define USART_FLAG_FE ((uint16_t)0x0002)
-#define USART_FLAG_PE ((uint16_t)0x0001)
-#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
- ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
- ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
- ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
- ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
-
-#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
-
-#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x003D0901))
-#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
-#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Exported_Functions
- * @{
- */
-
-void USART_DeInit(USART_TypeDef* USARTx);
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
-void USART_SendBreak(USART_TypeDef* USARTx);
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_USART_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/misc.c b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/misc.c
deleted file mode 100644
index e7648ab..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/misc.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/**
- ******************************************************************************
- * @file misc.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief This file provides all the miscellaneous firmware functions (add-on
- * to CMSIS functions).
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "misc.h"
-
-/** @addtogroup STM32L1xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup MISC
- * @brief MISC driver modules
- * @{
- */
-
-/** @defgroup MISC_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup MISC_Private_Defines
- * @{
- */
-
-#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
-/**
- * @}
- */
-
-/** @defgroup MISC_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup MISC_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup MISC_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup MISC_Private_Functions
- * @{
- */
-
-/**
- * @brief Configures the priority grouping: pre-emption priority and subpriority.
- * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
- * This parameter can be one of the following values:
- * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
- * 4 bits for subpriority
- * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
- * 3 bits for subpriority
- * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
- * 2 bits for subpriority
- * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
- * 1 bits for subpriority
- * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
- * 0 bits for subpriority
- * @retval None
- */
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
-
- /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
- SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
-}
-
-/**
- * @brief Initializes the NVIC peripheral according to the specified
- * parameters in the NVIC_InitStruct.
- * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
- * the configuration information for the specified NVIC peripheral.
- * @retval None
- */
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
-{
- uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
- assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
-
- if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
- {
- /* Compute the Corresponding IRQ Priority --------------------------------*/
- tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
- tmppre = (0x4 - tmppriority);
- tmpsub = tmpsub >> tmppriority;
-
- tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
- tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
- tmppriority = tmppriority << 0x04;
-
- NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
-
- /* Enable the Selected IRQ Channels --------------------------------------*/
- NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
- (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
- }
- else
- {
- /* Disable the Selected IRQ Channels -------------------------------------*/
- NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
- (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
- }
-}
-
-/**
- * @brief Sets the vector table location and Offset.
- * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
- * This parameter can be one of the following values:
- * @arg NVIC_VectTab_RAM
- * @arg NVIC_VectTab_FLASH
- * @param Offset: Vector Table base offset field. This value must be a multiple of 0x100.
- * @retval None
- */
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
- assert_param(IS_NVIC_OFFSET(Offset));
-
- SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
-}
-
-/**
- * @brief Selects the condition for the system to enter low power mode.
- * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
- * This parameter can be one of the following values:
- * @arg NVIC_LP_SEVONPEND
- * @arg NVIC_LP_SLEEPDEEP
- * @arg NVIC_LP_SLEEPONEXIT
- * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_LP(LowPowerMode));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- SCB->SCR |= LowPowerMode;
- }
- else
- {
- SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
- }
-}
-
-/**
- * @brief Configures the SysTick clock source.
- * @param SysTick_CLKSource: specifies the SysTick clock source.
- * This parameter can be one of the following values:
- * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
- * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
- * @retval None
- */
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
-{
- /* Check the parameters */
- assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
- if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
- {
- SysTick->CTRL |= SysTick_CLKSource_HCLK;
- }
- else
- {
- SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c
deleted file mode 100644
index 348f33c..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l1xx_exti.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief This file provides all the EXTI firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_exti.h"
-
-/** @addtogroup STM32L1xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup EXTI
- * @brief EXTI driver modules
- * @{
- */
-
-/** @defgroup EXTI_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_Private_Defines
- * @{
- */
-
-#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the EXTI peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void EXTI_DeInit(void)
-{
- EXTI->IMR = 0x00000000;
- EXTI->EMR = 0x00000000;
- EXTI->RTSR = 0x00000000;
- EXTI->FTSR = 0x00000000;
- EXTI->PR = 0x007FFFFF;
-}
-
-/**
- * @brief Initializes the EXTI peripheral according to the specified
- * parameters in the EXTI_InitStruct.
- * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
- * that contains the configuration information for the EXTI peripheral.
- * @retval None
- */
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
- assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
- assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
- assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
-
- tmp = (uint32_t)EXTI_BASE;
-
- if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
- {
- /* Clear EXTI line configuration */
- EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
- EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
-
- tmp += EXTI_InitStruct->EXTI_Mode;
-
- *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
-
- /* Clear Rising Falling edge configuration */
- EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
- EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
-
- /* Select the trigger for the selected external interrupts */
- if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
- {
- /* Rising Falling edge */
- EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
- EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
- }
- else
- {
- tmp = (uint32_t)EXTI_BASE;
- tmp += EXTI_InitStruct->EXTI_Trigger;
-
- *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
- }
- }
- else
- {
- tmp += EXTI_InitStruct->EXTI_Mode;
-
- /* Disable the selected external lines */
- *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
- }
-}
-
-/**
- * @brief Fills each EXTI_InitStruct member with its reset value.
- * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
-{
- EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
- EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
- EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
- EXTI_InitStruct->EXTI_LineCmd = DISABLE;
-}
-
-/**
- * @brief Generates a Software interrupt.
- * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled.
- * This parameter can be any combination of EXTI_Linex where x can be (0..22).
- * @retval None
- */
-void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE(EXTI_Line));
-
- EXTI->SWIER |= EXTI_Line;
-}
-
-/**
- * @brief Checks whether the specified EXTI line flag is set or not.
- * @param EXTI_Line: specifies the EXTI line flag to check.
- * This parameter can be:
- * @arg EXTI_Linex: External interrupt line x where x(0..22)
- * @retval The new state of EXTI_Line (SET or RESET).
- */
-FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_GET_EXTI_LINE(EXTI_Line));
-
- if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the EXTIÂ’s line pending flags.
- * @param EXTI_Line: specifies the EXTI lines flags to clear.
- * This parameter can be any combination of EXTI_Linex where x can be (0..22).
- * @retval None
- */
-void EXTI_ClearFlag(uint32_t EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE(EXTI_Line));
-
- EXTI->PR = EXTI_Line;
-}
-
-/**
- * @brief Checks whether the specified EXTI line is asserted or not.
- * @param EXTI_Line: specifies the EXTI line to check.
- * This parameter can be:
- * @arg EXTI_Linex: External interrupt line x where x(0..22)
- * @retval The new state of EXTI_Line (SET or RESET).
- */
-ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
- /* Check the parameters */
- assert_param(IS_GET_EXTI_LINE(EXTI_Line));
-
- enablestatus = EXTI->IMR & EXTI_Line;
- if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the EXTIÂ’s line pending bits.
- * @param EXTI_Line: specifies the EXTI lines to clear.
- * This parameter can be any combination of EXTI_Linex where x can be (0..22).
- * @retval None
- */
-void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE(EXTI_Line));
-
- EXTI->PR = EXTI_Line;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c
deleted file mode 100644
index 6c45f16..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c
+++ /dev/null
@@ -1,437 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l1xx_gpio.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief This file provides all the GPIO firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_gpio.h"
-#include "stm32l1xx_rcc.h"
-
-/** @addtogroup STM32L1xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup GPIO
- * @brief GPIO driver modules
- * @{
- */
-
-/** @defgroup GPIO_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup GPIO_Private_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup GPIO_Private_FunctionPrototypes
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup GPIO_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the GPIOx peripheral registers to their default reset
- * values.
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.
- * @retval None
- */
-void GPIO_DeInit(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- if(GPIOx == GPIOA)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
- }
- else if(GPIOx == GPIOB)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
- }
- else if(GPIOx == GPIOC)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);
- }
- else if(GPIOx == GPIOD)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);
- }
- else if(GPIOx == GPIOE)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);
- }
- else
- {
- if(GPIOx == GPIOH)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the GPIOx peripheral according to the specified
- * parameters in the GPIO_InitStruct.
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.
- * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
- * contains the configuration information for the specified GPIO
- * peripheral.
- * @retval None
- */
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
-{
- uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
- assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
- assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
-
- /* -------------------------Configure the port pins---------------- */
- /*-- GPIO Mode Configuration --*/
- for (pinpos = 0x00; pinpos < 0x10; pinpos++)
- {
- pos = ((uint32_t)0x01) << pinpos;
-
- /* Get the port pins position */
- currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
-
- if (currentpin == pos)
- {
- GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
-
- GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
-
- if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
- {
- /*Check Speed mode parameters */
- assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
-
- /*Speed mode configuration */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
- GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
-
- /*Check Output mode parameters */
- assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
-
- /* Output mode configuartion*/
- GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;
- GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
- }
-
- /*Pull-up Pull down resistor configuration*/
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
- GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
- }
- }
-}
-
-/**
- * @brief Fills each GPIO_InitStruct member with its default value.
- * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
-{
- /* Reset GPIO init structure parameters values */
- GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStruct->GPIO_Speed = GPIO_Speed_400KHz;
- GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
- GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
-}
-
-/**
- * @brief Reads the specified input port pin.
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to read.
- * This parameter can be GPIO_Pin_x where x can be (0..15).
- * @retval The input port pin value.
- */
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Reads the specified GPIO input data port.
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.
- * @retval GPIO input data port value.
- */
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((uint16_t)GPIOx->IDR);
-}
-
-/**
- * @brief Reads the specified output data port bit.
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.
- * @param GPIO_Pin: Specifies the port bit to read.
- * This parameter can be GPIO_Pin_x where x can be (0..15).
- * @retval The output port pin value.
- */
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Reads the specified GPIO output data port.
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.
- * @retval GPIO output data port value.
- */
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((uint16_t)GPIOx->ODR);
-}
-
-/**
- * @brief Sets the selected data port bits.
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bits to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BSRRL = GPIO_Pin;
-}
-
-/**
- * @brief Clears the selected data port bits.
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bits to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BSRRH = GPIO_Pin;
-}
-
-/**
- * @brief Sets or clears the selected data port bit.
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to be written.
- * This parameter can be one of GPIO_Pin_x where x can be (0..15).
- * @param BitVal: specifies the value to be written to the selected bit.
- * This parameter can be one of the BitAction enum values:
- * @arg Bit_RESET: to clear the port pin
- * @arg Bit_SET: to set the port pin
- * @retval None
- */
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_BIT_ACTION(BitVal));
-
- if (BitVal != Bit_RESET)
- {
- GPIOx->BSRRL = GPIO_Pin;
- }
- else
- {
- GPIOx->BSRRH = GPIO_Pin ;
- }
-}
-
-/**
- * @brief Writes data to the specified GPIO data port.
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.
- * @param PortVal: specifies the value to be written to the port output data
- * register.
- * @retval None
- */
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- GPIOx->ODR = PortVal;
-}
-
-/**
- * @brief Locks GPIO Pins configuration registers.
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint32_t tmp = 0x00010000;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- tmp |= GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Reset LCKK bit */
- GPIOx->LCKR = GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Read LCKK bit*/
- tmp = GPIOx->LCKR;
- /* Read LCKK bit*/
- tmp = GPIOx->LCKR;
-}
-
-/**
- * @brief Changes the mapping of the specified pin.
- * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.
- * @param GPIO_PinSource: specifies the pin for the Alternate function.
- * This parameter can be GPIO_PinSourcex where x can be (0..15).
- * @param GPIO_AFSelection: selects the pin to used as Alternat function.
- * This parameter can be one of the following values:
- * @arg GPIO_AF_RTC_50Hz
- * @arg GPIO_AF_MCO
- * @arg GPIO_AF_TAMPER
- * @arg GPIO_AF_WKUP
- * @arg GPIO_AF_SWJ
- * @arg GPIO_AF_TRACE
- * @arg GPIO_AF_TIMESTAMP
- * @arg GPIO_AF_CALIB
- * @arg GPIO_AF_TIM2
- * @arg GPIO_AF_TIM3
- * @arg GPIO_AF_TIM4
- * @arg GPIO_AF_TIM9
- * @arg GPIO_AF_TIM10
- * @arg GPIO_AF_TIM11
- * @arg GPIO_AF_I2C1
- * @arg GPIO_AF_I2C2
- * @arg GPIO_AF_SPI1
- * @arg GPIO_AF_SPI2
- * @arg GPIO_AF_USART1
- * @arg GPIO_AF_USART2
- * @arg GPIO_AF_USART3
- * @arg GPIO_AF_USB
- * @arg GPIO_AF_LCD
- * @arg GPIO_AF_RI
- * @arg GPIO_AF_EVENTOUT
- * @retval None
- */
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
-{
- uint32_t temp = 0x00;
- uint32_t temp_2 = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
- assert_param(IS_GPIO_AF(GPIO_AF));
-
- temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
- GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
- temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
- GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c
deleted file mode 100644
index e6b8716..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c
+++ /dev/null
@@ -1,464 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l1xx_pwr.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief This file provides all the PWR firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_pwr.h"
-#include "stm32l1xx_rcc.h"
-
-/** @addtogroup STM32L1xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup PWR
- * @brief PWR driver modules
- * @{
- */
-
-/** @defgroup PWR_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Private_Defines
- * @{
- */
-
-/* --------- PWR registers bit address in the alias region ---------- */
-#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
-
-/* --- CR Register ---*/
-
-/* Alias word address of DBP bit */
-#define CR_OFFSET (PWR_OFFSET + 0x00)
-#define DBP_BitNumber 0x08
-#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
-
-/* Alias word address of PVDE bit */
-#define PVDE_BitNumber 0x04
-#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
-
-/* Alias word address of ULP bit */
-#define ULP_BitNumber 0x09
-#define CR_ULP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ULP_BitNumber * 4))
-
-/* Alias word address of FWU bit */
-#define FWU_BitNumber 0x0A
-#define CR_FWU_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FWU_BitNumber * 4))
-
-/* --- CSR Register ---*/
-
-/* Alias word address of EWUP bit */
-#define CSR_OFFSET (PWR_OFFSET + 0x04)
-#define EWUP_BitNumber 0x08
-#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
-
-/* ------------------ PWR registers bit mask ------------------------ */
-
-/* CR register bit mask */
-#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
-#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
-#define CR_VOS_MASK ((uint32_t)0xFFFFE7FF)
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the PWR peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void PWR_DeInit(void)
-{
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
-}
-
-/**
- * @brief Enables or disables access to the RTC and backup registers.
- * @param NewState: new state of the access to the RTC and backup registers.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_RTCAccessCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the Power Voltage Detector(PVD).
- * @param NewState: new state of the PVD.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_PVDCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
- * @param PWR_PVDLevel: specifies the PVD detection level
- * This parameter can be one of the following values:
- * @arg PWR_PVDLevel_0: PVD detection level set to 1.9V
- * @arg PWR_PVDLevel_1: PVD detection level set to 2.1V
- * @arg PWR_PVDLevel_2: PVD detection level set to 2.3V
- * @arg PWR_PVDLevel_3: PVD detection level set to 2.5V
- * @arg PWR_PVDLevel_4: PVD detection level set to 2.7V
- * @arg PWR_PVDLevel_5: PVD detection level set to 2.9V
- * @arg PWR_PVDLevel_6: PVD detection level set to 3.1V
- * @arg PWR_PVDLevel_7: External input analog voltage (Compare internally to VREFINT)
- * @retval None
- */
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
-
- tmpreg = PWR->CR;
-
- /* Clear PLS[7:5] bits */
- tmpreg &= CR_PLS_MASK;
-
- /* Set PLS[7:5] bits according to PWR_PVDLevel value */
- tmpreg |= PWR_PVDLevel;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the WakeUp Pin functionality.
- * @param PWR_WakeUpPin: specifies the WakeUpPin.
- * This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3.
- * @param NewState: new state of the WakeUp Pin functionality.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));
-
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- tmp = CSR_EWUP_BB + PWR_WakeUpPin;
-
- *(__IO uint32_t *) (tmp) = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the Fast WakeUp from Ultra Low Power mode.
- * @param NewState: new state of the Fast WakeUp functionality.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_FastWakeUpCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_FWU_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the Ultra Low Power mode.
- * @param NewState: new state of the Ultra Low Power mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_UltraLowPowerCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_ULP_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the voltage scaling range.
- * @param PWR_VoltageScaling: specifies the voltage scaling range.
- * This parameter can be:
- * @arg PWR_VoltageScaling_Range1: Voltage Scaling Range 1
- * @arg PWR_VoltageScaling_Range2: Voltage Scaling Range 2
- * @arg PWR_VoltageScaling_Range3: Voltage Scaling Range 3
- * @retval None
- */
-void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(PWR_VoltageScaling));
-
- tmp = PWR->CR;
-
- tmp &= CR_VOS_MASK;
- tmp |= PWR_VoltageScaling;
-
- PWR->CR = tmp & 0xFFFFFFF3;
-
-}
-
-/**
- * @brief Enters/Exits the Low Power Run mode.
- * @param NewState: new state of the Low Power Run mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_EnterLowPowerRunMode(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- PWR->CR |= PWR_CR_LPSDSR;
- PWR->CR |= PWR_CR_LPRUN;
- }
- else
- {
- PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPRUN);
- PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPSDSR);
- }
-}
-
-/**
- * @brief Enters Sleep mode.
- * @param PWR_Regulator: specifies the regulator state in Sleep mode.
- * This parameter can be one of the following values:
- * @arg PWR_Regulator_ON: Sleep mode with regulator ON
- * @arg PWR_Regulator_LowPower: Sleep mode with regulator in low power mode
- * @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
- * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
- * @retval None
- */
-void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR(PWR_Regulator));
-
- assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
-
- /* Select the regulator state in Sleep mode ---------------------------------*/
- tmpreg = PWR->CR;
-
- /* Clear PDDS and LPDSR bits */
- tmpreg &= CR_DS_MASK;
-
- /* Set LPDSR bit according to PWR_Regulator value */
- tmpreg |= PWR_Regulator;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-
- /* Clear SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
-
- /* Select SLEEP mode entry -------------------------------------------------*/
- if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __WFE();
- }
-}
-
-/**
- * @brief Enters STOP mode.
- * @param PWR_Regulator: specifies the regulator state in STOP mode.
- * This parameter can be one of the following values:
- * @arg PWR_Regulator_ON: STOP mode with regulator ON
- * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
- * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
- * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
- * @retval None
- */
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR(PWR_Regulator));
- assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
-
- /* Select the regulator state in STOP mode ---------------------------------*/
- tmpreg = PWR->CR;
- /* Clear PDDS and LPDSR bits */
- tmpreg &= CR_DS_MASK;
-
- /* Set LPDSR bit according to PWR_Regulator value */
- tmpreg |= PWR_Regulator;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP;
-
- /* Select STOP mode entry --------------------------------------------------*/
- if(PWR_STOPEntry == PWR_STOPEntry_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __WFE();
- }
- /* Reset SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
-}
-
-/**
- * @brief Enters STANDBY mode.
- * @param None
- * @retval None
- */
-void PWR_EnterSTANDBYMode(void)
-{
- /* Clear Wake-up flag */
- PWR->CR |= PWR_CR_CWUF;
-
- /* Select STANDBY mode */
- PWR->CR |= PWR_CR_PDDS;
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP;
-
-/* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM )
- __force_stores();
-#endif
- /* Request Wait For Interrupt */
- __WFI();
-}
-
-/**
- * @brief Checks whether the specified PWR flag is set or not.
- * @param PWR_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag
- * @arg PWR_FLAG_SB: StandBy flag
- * @arg PWR_FLAG_PVDO: PVD Output
- * @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag
- * @arg PWR_FLAG_VOS: Voltage Scaling select flag
- * @arg PWR_FLAG_REGLP: Regulator LP flag
- * @retval The new state of PWR_FLAG (SET or RESET).
- */
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
-
- if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the PWR's pending flags.
- * @param PWR_FLAG: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag
- * @arg PWR_FLAG_SB: StandBy flag
- * @retval None
- */
-void PWR_ClearFlag(uint32_t PWR_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
-
- PWR->CR |= PWR_FLAG << 2;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c
deleted file mode 100644
index f7bdb49..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c
+++ /dev/null
@@ -1,1225 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l1xx_rcc.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief This file provides all the RCC firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_rcc.h"
-
-/** @addtogroup STM32L1xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup RCC
- * @brief RCC driver modules
- * @{
- */
-
-/** @defgroup RCC_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Private_Defines
- * @{
- */
-
-/* ------------ RCC registers bit address in the alias region ----------- */
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
-
-/* --- CR Register ---*/
-
-/* Alias word address of HSION bit */
-#define CR_OFFSET (RCC_OFFSET + 0x00)
-#define HSION_BitNumber 0x00
-#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
-
-/* Alias word address of MSION bit */
-#define MSION_BitNumber 0x08
-#define CR_MSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MSION_BitNumber * 4))
-
-/* Alias word address of PLLON bit */
-#define PLLON_BitNumber 0x18
-#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
-
-/* Alias word address of CSSON bit */
-#define CSSON_BitNumber 0x1C
-#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
-
-/* --- CSR Register ---*/
-
-/* Alias word address of LSION bit */
-#define CSR_OFFSET (RCC_OFFSET + 0x34)
-#define LSION_BitNumber 0x00
-#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
-
-/* Alias word address of RTCEN bit */
-#define RTCEN_BitNumber 0x16
-#define CSR_RTCEN_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCEN_BitNumber * 4))
-
-/* Alias word address of RTCRST bit */
-#define RTCRST_BitNumber 0x17
-#define CSR_RTCRST_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCRST_BitNumber * 4))
-
-
-/* ---------------------- RCC registers mask -------------------------------- */
-/* RCC Flag Mask */
-#define FLAG_MASK ((uint8_t)0x1F)
-
-/* CR register byte 3 (Bits[23:16]) base address */
-#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
-
-/* ICSCR register byte 4 (Bits[31:24]) base address */
-#define ICSCR_BYTE4_ADDRESS ((uint32_t)0x40023807)
-
-/* CFGR register byte 3 (Bits[23:16]) base address */
-#define CFGR_BYTE3_ADDRESS ((uint32_t)0x4002380A)
-
-/* CFGR register byte 4 (Bits[31:24]) base address */
-#define CFGR_BYTE4_ADDRESS ((uint32_t)0x4002380B)
-
-/* CIR register byte 2 (Bits[15:8]) base address */
-#define CIR_BYTE2_ADDRESS ((uint32_t)0x4002380D)
-
-/* CIR register byte 3 (Bits[23:16]) base address */
-#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002380E)
-
-/* CSR register byte 2 (Bits[15:8]) base address */
-#define CSR_BYTE2_ADDRESS ((uint32_t)0x40023835)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Private_Variables
- * @{
- */
-
-static __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
-static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-static __I uint8_t MSITable[7] = {0, 0, 0, 0, 1, 2, 4};
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Private_Functions
- * @{
- */
-
-/**
- * @brief Resets the RCC clock configuration to the default reset state.
- * @param None
- * @retval None
- */
-void RCC_DeInit(void)
-{
-
- /* Set MSION bit */
- RCC->CR |= (uint32_t)0x00000100;
-
- /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
- RCC->CFGR &= (uint32_t)0x88FFC00C;
-
- /* Reset HSION, HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xEEFEFFFE;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
- RCC->CFGR &= (uint32_t)0xFF02FFFF;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-}
-
-/**
- * @brief Configures the External High Speed oscillator (HSE).
- * @note HSE can not be stopped if it is used directly or through the PLL as system clock.
- * @param RCC_HSE: specifies the new state of the HSE.
- * This parameter can be one of the following values:
- * @arg RCC_HSE_OFF: HSE oscillator OFF
- * @arg RCC_HSE_ON: HSE oscillator ON
- * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
- * @retval None
- */
-void RCC_HSEConfig(uint8_t RCC_HSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_HSE));
-
- /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
- *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
-
- /* Set the new HSE configuration -------------------------------------------*/
- *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
-
-}
-
-/**
- * @brief Waits for HSE start-up.
- * @param None
- * @retval An ErrorStatus enumuration value:
- * - SUCCESS: HSE oscillator is stable and ready to use
- * - ERROR: HSE oscillator not yet ready
- */
-ErrorStatus RCC_WaitForHSEStartUp(void)
-{
- __IO uint32_t StartUpCounter = 0;
- ErrorStatus status = ERROR;
- FlagStatus HSEStatus = RESET;
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
- StartUpCounter++;
- } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
-
- if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
- {
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
- return (status);
-}
-
-/**
- * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
- * @param HSICalibrationValue: specifies the HSI calibration trimming value.
- * This parameter must be a number between 0 and 0x1F.
- * @retval None
- */
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
-
- tmpreg = RCC->ICSCR;
-
- /* Clear HSITRIM[4:0] bits */
- tmpreg &= ~RCC_ICSCR_HSITRIM;
-
- /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
- tmpreg |= (uint32_t)HSICalibrationValue << 8;
-
- /* Store the new value */
- RCC->ICSCR = tmpreg;
-}
-
-/**
- * @brief Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
- * @param MSICalibrationValue: specifies the MSI calibration trimming value.
- * This parameter must be a number between 0 and 0xFF.
- * @retval None
- */
-void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue)
-{
-
- /* Check the parameters */
- assert_param(IS_RCC_MSI_CALIBRATION_VALUE(MSICalibrationValue));
-
- *(__IO uint8_t *) ICSCR_BYTE4_ADDRESS = MSICalibrationValue;
-}
-
-/**
- * @brief Configures the Internal Multi Speed oscillator (MSI) clock range.
- * @param RCC_MSIRange: specifies the MSI Clcok range.
- * This parameter must be one of the following values:
- * @arg RCC_MSIRange_64KHz: MSI clock is around 64 KHz
- * @arg RCC_MSIRange_128KHz: MSI clock is around 128 KHz
- * @arg RCC_MSIRange_256KHz: MSI clock is around 256 KHz
- * @arg RCC_MSIRange_512KHz: MSI clock is around 512 KHz
- * @arg RCC_MSIRange_1MHz: MSI clock is around 1 MHz
- * @arg RCC_MSIRange_2MHz: MSI clock is around 2 MHz
- * @arg RCC_MSIRange_4MHz: MSI clock is around 4 MHz
- * @retval None
- */
-void RCC_MSIRangeConfig(uint32_t RCC_MSIRange)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_MSIRange));
-
- tmpreg = RCC->ICSCR;
-
- /* Clear MSIRANGE[2:0] bits */
- tmpreg &= ~RCC_ICSCR_MSIRANGE;
-
- /* Set the MSIRANGE[2:0] bits according to RCC_MSIRange value */
- tmpreg |= (uint32_t)RCC_MSIRange;
-
- /* Store the new value */
- RCC->ICSCR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Internal Multi Speed oscillator (MSI).
- * @note MSI can not be stopped if it is used directly as system clock.
- * @param NewState: new state of the MSI.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_MSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_MSION_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the Internal High Speed oscillator (HSI).
- * @note HSI can not be stopped if it is used directly or through the PLL as system clock.
- * @param NewState: new state of the HSI.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_HSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the PLL clock source and multiplication factor.
- * @note This function must be used only when the PLL is disabled.
- * @param RCC_PLLSource: specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
- * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
- * @param RCC_PLLMul: specifies the PLL multiplication factor.
- * This parameter can be:
- * @arg RCC_PLLMul_3: PLL Clock entry multiplied by 3
- * @arg RCC_PLLMul_4: PLL Clock entry multiplied by 4
- * @arg RCC_PLLMul_6: PLL Clock entry multiplied by 6
- * @arg RCC_PLLMul_8: PLL Clock entry multiplied by 8
- * @arg RCC_PLLMul_12: PLL Clock entry multiplied by 12
- * @arg RCC_PLLMul_16: PLL Clock entry multiplied by 16
- * @arg RCC_PLLMul_24: PLL Clock entry multiplied by 24
- * @arg RCC_PLLMul_32: PLL Clock entry multiplied by 32
- * @arg RCC_PLLMul_48: PLL Clock entry multiplied by 48
- * @param RCC_PLLDiv: specifies the PLL division factor.
- * This parameter can be:
- * @arg RCC_PLLDiv_2: PLL Clock output divided by 2
- * @arg RCC_PLLDiv_3: PLL Clock output divided by 3
- * @arg RCC_PLLDiv_4: PLL Clock output divided by 4
- * @retval None
- */
-void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
- assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
- assert_param(IS_RCC_PLL_DIV(RCC_PLLDiv));
-
- *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = (uint8_t)(RCC_PLLSource | ((uint8_t)(RCC_PLLMul | (uint8_t)(RCC_PLLDiv))));
-}
-
-/**
- * @brief Enables or disables the PLL.
- * @note The PLL can not be disabled if it is used as system clock.
- * @param NewState: new state of the PLL.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_PLLCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the system clock (SYSCLK).
- * @param RCC_SYSCLKSource: specifies the clock source used as system clock.
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLKSource_MSI: MSI selected as system clock
- * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
- * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
- * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
- * @retval None
- */
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
-
- tmpreg = RCC->CFGR;
-
- /* Clear SW[1:0] bits */
- tmpreg &= ~RCC_CFGR_SW;
-
- /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
- tmpreg |= RCC_SYSCLKSource;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Returns the clock source used as system clock.
- * @param None
- * @retval The clock source used as system clock. The returned value can be one
- * of the following values:
- * - 0x00: MSI used as system clock
- * - 0x04: HSI used as system clock
- * - 0x08: HSE used as system clock
- * - 0x0C: PLL used as system clock
- */
-uint8_t RCC_GetSYSCLKSource(void)
-{
- return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
-}
-
-/**
- * @brief Configures the AHB clock (HCLK).
- * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
- * the system clock (SYSCLK).
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
- * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
- * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
- * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
- * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
- * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
- * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
- * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
- * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
- * @retval None
- */
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_HCLK(RCC_SYSCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear HPRE[3:0] bits */
- tmpreg &= ~RCC_CFGR_HPRE;
-
- /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
- tmpreg |= RCC_SYSCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Configures the Low Speed APB clock (PCLK1).
- * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
- * the AHB clock (HCLK).
- * This parameter can be one of the following values:
- * @arg RCC_HCLK_Div1: APB1 clock = HCLK
- * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
- * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
- * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
- * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
- * @retval None
- */
-void RCC_PCLK1Config(uint32_t RCC_HCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PCLK(RCC_HCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear PPRE1[2:0] bits */
- tmpreg &= ~RCC_CFGR_PPRE1;
-
- /* Set PPRE1[2:0] bits according to RCC_HCLK value */
- tmpreg |= RCC_HCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Configures the High Speed APB clock (PCLK2).
- * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
- * the AHB clock (HCLK).
- * This parameter can be one of the following values:
- * @arg RCC_HCLK_Div1: APB2 clock = HCLK
- * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
- * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
- * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
- * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
- * @retval None
- */
-void RCC_PCLK2Config(uint32_t RCC_HCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PCLK(RCC_HCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear PPRE2[2:0] bits */
- tmpreg &= ~RCC_CFGR_PPRE2;
-
- /* Set PPRE2[2:0] bits according to RCC_HCLK value */
- tmpreg |= RCC_HCLK << 3;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the specified RCC interrupts.
- * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: PLL ready interrupt
- * @arg RCC_IT_MSIRDY: MSI ready interrupt
- * @param NewState: new state of the specified RCC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_IT(RCC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
- }
- else
- {
- /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
- }
-}
-
-/**
- * @brief Configures the External Low Speed oscillator (LSE).
- * @param RCC_LSE: specifies the new state of the LSE.
- * This parameter can be one of the following values:
- * @arg RCC_LSE_OFF: LSE oscillator OFF
- * @arg RCC_LSE_ON: LSE oscillator ON
- * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
- * @retval None
- */
-void RCC_LSEConfig(uint8_t RCC_LSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_LSE));
-
- /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
- *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE_OFF;
-
- /* Set the new LSE configuration -------------------------------------------*/
- *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE;
-}
-
-/**
- * @brief Enables or disables the Internal Low Speed oscillator (LSI).
- * @note LSI can not be disabled if the IWDG is running.
- * @param NewState: new state of the LSI.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_LSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the RTC and LCD clock (RTCCLK / LCDCLK).
- * @note
- * - Once the RTC clock is selected it can't be changed unless the RTC is
- * reset using RCC_RTCResetCmd function.
- * - This RTC clock (RTCCLK) is used to clock the LCD (LCDCLK).
- * @param RCC_RTCCLKSource: specifies the RTC clock source.
- * This parameter can be one of the following values:
- * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
- * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
- * @arg RCC_RTCCLKSource_HSE_Div2: HSE divided by 2 selected as RTC clock
- * @arg RCC_RTCCLKSource_HSE_Div4: HSE divided by 4 selected as RTC clock
- * @arg RCC_RTCCLKSource_HSE_Div8: HSE divided by 8 selected as RTC clock
- * @arg RCC_RTCCLKSource_HSE_Div16: HSE divided by 16 selected as RTC clock
- * @retval None
- */
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
-
- if ((RCC_RTCCLKSource & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE)
- {
- /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
- tmpreg = RCC->CR;
-
- /* Clear RTCPRE[1:0] bits */
- tmpreg &= ~RCC_CR_RTCPRE;
-
- /* Configure HSE division factor for RTC clock */
- tmpreg |= (RCC_RTCCLKSource & RCC_CR_RTCPRE);
-
- /* Store the new value */
- RCC->CR = tmpreg;
- }
-
- RCC->CSR &= ~RCC_CSR_RTCSEL;
-
- /* Select the RTC clock source */
- RCC->CSR |= (RCC_RTCCLKSource & RCC_CSR_RTCSEL);
-}
-
-/**
- * @brief Enables or disables the RTC clock.
- * @note This function must be used only after the RTC clock was selected using the
- * RCC_RTCCLKConfig function.
- * @param NewState: new state of the RTC clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_RTCCLKCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CSR_RTCEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Forces or releases the RTC peripheral reset.
- * @param NewState: new state of the RTC reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_RTCResetCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CSR_RTCRST_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Returns the frequencies of different on chip clocks.
- * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
- * the clocks frequencies.
- * @retval None
- */
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
-{
- uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, presc = 0, msirange = 0;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* MSI used as system clock */
- msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;
- RCC_Clocks->SYSCLK_Frequency = (((1 << msirange) * 64000) - (MSITable[msirange] * 24000));
- break;
- case 0x04: /* HSI used as system clock */
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- case 0x08: /* HSE used as system clock */
- RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
- break;
- case 0x0C: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
- plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
- pllmul = PLLMulTable[(pllmul >> 18)];
- plldiv = (plldiv >> 22) + 1;
-
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
- if (pllsource == 0x00)
- {
- /* HSI oscillator clock selected as PLL clock entry */
- RCC_Clocks->SYSCLK_Frequency = (((HSI_VALUE) * pllmul) / plldiv);
- }
- else
- {
- /* HSE selected as PLL clock entry */
- RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE) * pllmul) / plldiv);
- }
- break;
- default:
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- }
- /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
- /* Get HCLK prescaler */
- tmp = RCC->CFGR & RCC_CFGR_HPRE;
- tmp = tmp >> 4;
- presc = APBAHBPrescTable[tmp];
- /* HCLK clock frequency */
- RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
-
- /* Get PCLK1 prescaler */
- tmp = RCC->CFGR & RCC_CFGR_PPRE1;
- tmp = tmp >> 8;
- presc = APBAHBPrescTable[tmp];
- /* PCLK1 clock frequency */
- RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-
- /* Get PCLK2 prescaler */
- tmp = RCC->CFGR & RCC_CFGR_PPRE2;
- tmp = tmp >> 11;
- presc = APBAHBPrescTable[tmp];
- /* PCLK2 clock frequency */
- RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-}
-
-/**
- * @brief Enables or disables the AHB peripheral clock.
- * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHBPeriph_GPIOA
- * @arg RCC_AHBPeriph_GPIOB
- * @arg RCC_AHBPeriph_GPIOC
- * @arg RCC_AHBPeriph_GPIOD
- * @arg RCC_AHBPeriph_GPIOE
- * @arg RCC_AHBPeriph_GPIOH
- * @arg RCC_AHBPeriph_CRC
- * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)
- * @arg RCC_AHBPeriph_DMA1
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHBENR |= RCC_AHBPeriph;
- }
- else
- {
- RCC->AHBENR &= ~RCC_AHBPeriph;
- }
-}
-
-/**
- * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_SYSCFG
- * @arg RCC_APB2Periph_TIM9
- * @arg RCC_APB2Periph_TIM10
- * @arg RCC_APB2Periph_TIM11
- * @arg RCC_APB2Periph_ADC1
- * @arg RCC_APB2Periph_SPI1
- * @arg RCC_APB2Periph_USART1
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB2ENR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2ENR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2
- * @arg RCC_APB1Periph_TIM3
- * @arg RCC_APB1Periph_TIM4
- * @arg RCC_APB1Periph_TIM6
- * @arg RCC_APB1Periph_TIM7
- * @arg RCC_APB1Periph_LCD
- * @arg RCC_APB1Periph_WWDG
- * @arg RCC_APB1Periph_SPI2
- * @arg RCC_APB1Periph_USART2
- * @arg RCC_APB1Periph_USART3
- * @arg RCC_APB1Periph_I2C1
- * @arg RCC_APB1Periph_I2C2
- * @arg RCC_APB1Periph_USB
- * @arg RCC_APB1Periph_PWR
- * @arg RCC_APB1Periph_DAC
- * @arg RCC_APB1Periph_COMP
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB1ENR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1ENR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Forces or releases AHB peripheral reset.
- * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHBPeriph_GPIOA
- * @arg RCC_AHBPeriph_GPIOB
- * @arg RCC_AHBPeriph_GPIOC
- * @arg RCC_AHBPeriph_GPIOD
- * @arg RCC_AHBPeriph_GPIOE
- * @arg RCC_AHBPeriph_GPIOH
- * @arg RCC_AHBPeriph_CRC
- * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)
- * @arg RCC_AHBPeriph_DMA1
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHBRSTR |= RCC_AHBPeriph;
- }
- else
- {
- RCC->AHBRSTR &= ~RCC_AHBPeriph;
- }
-}
-
-/**
- * @brief Forces or releases High Speed APB (APB2) peripheral reset.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_SYSCFG
- * @arg RCC_APB2Periph_TIM9
- * @arg RCC_APB2Periph_TIM10
- * @arg RCC_APB2Periph_TIM11
- * @arg RCC_APB2Periph_ADC1
- * @arg RCC_APB2Periph_SPI1
- * @arg RCC_APB2Periph_USART1
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB2RSTR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2RSTR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2
- * @arg RCC_APB1Periph_TIM3
- * @arg RCC_APB1Periph_TIM4
- * @arg RCC_APB1Periph_TIM6
- * @arg RCC_APB1Periph_TIM7
- * @arg RCC_APB1Periph_LCD
- * @arg RCC_APB1Periph_WWDG
- * @arg RCC_APB1Periph_SPI2
- * @arg RCC_APB1Periph_USART2
- * @arg RCC_APB1Periph_USART3
- * @arg RCC_APB1Periph_I2C1
- * @arg RCC_APB1Periph_I2C2
- * @arg RCC_APB1Periph_USB
- * @arg RCC_APB1Periph_PWR
- * @arg RCC_APB1Periph_DAC
- * @arg RCC_APB1Periph_COMP
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB1RSTR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1RSTR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB peripheral clock during Low Power (SLEEP) mode.
- * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHBPeriph_GPIOA
- * @arg RCC_AHBPeriph_GPIOB
- * @arg RCC_AHBPeriph_GPIOC
- * @arg RCC_AHBPeriph_GPIOD
- * @arg RCC_AHBPeriph_GPIOE
- * @arg RCC_AHBPeriph_GPIOH
- * @arg RCC_AHBPeriph_CRC
- * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)
- * @arg RCC_AHBPeriph_SRAM
- * @arg RCC_AHBPeriph_DMA1
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB_LPMODE_PERIPH(RCC_AHBPeriph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHBLPENR |= RCC_AHBPeriph;
- }
- else
- {
- RCC->AHBLPENR &= ~RCC_AHBPeriph;
- }
-}
-
-/**
- * @brief Enables or disables the APB2 peripheral clock during Low Power (SLEEP) mode.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_SYSCFG
- * @arg RCC_APB2Periph_TIM9
- * @arg RCC_APB2Periph_TIM10
- * @arg RCC_APB2Periph_TIM11
- * @arg RCC_APB2Periph_ADC1
- * @arg RCC_APB2Periph_SPI1
- * @arg RCC_APB2Periph_USART1
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB2LPENR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2LPENR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Enables or disables the APB1 peripheral clock during Low Power (SLEEP) mode.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2
- * @arg RCC_APB1Periph_TIM3
- * @arg RCC_APB1Periph_TIM4
- * @arg RCC_APB1Periph_TIM6
- * @arg RCC_APB1Periph_TIM7
- * @arg RCC_APB1Periph_LCD
- * @arg RCC_APB1Periph_WWDG
- * @arg RCC_APB1Periph_SPI2
- * @arg RCC_APB1Periph_USART2
- * @arg RCC_APB1Periph_USART3
- * @arg RCC_APB1Periph_I2C1
- * @arg RCC_APB1Periph_I2C2
- * @arg RCC_APB1Periph_USB
- * @arg RCC_APB1Periph_PWR
- * @arg RCC_APB1Periph_DAC
- * @arg RCC_APB1Periph_COMP
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB1LPENR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1LPENR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the Clock Security System.
- * @param NewState: new state of the Clock Security System..
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Selects the clock source to output on MCO pin.
- * @param RCC_MCOSource: specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg RCC_MCOSource_NoClock: No clock selected
- * @arg RCC_MCOSource_SYSCLK: System clock selected
- * @arg RCC_MCOSource_HSI: HSI oscillator clock selected
- * @arg RCC_MCOSource_MSI: MSI oscillator clock selected
- * @arg RCC_MCOSource_HSE: HSE oscillator clock selected
- * @arg RCC_MCOSource_PLLCLK: PLL clock selected
- * @arg RCC_MCOSource_LSI: LSI clock selected
- * @arg RCC_MCOSource_LSE: LSE clock selected
- * @param RCC_MCODiv: specifies the MCO prescaler.
- * This parameter can be one of the following values:
- * @arg RCC_MCODiv_1: no division applied to MCO clock
- * @arg RCC_MCODiv_2: division by 2 applied to MCO clock
- * @arg RCC_MCODiv_4: division by 4 applied to MCO clock
- * @arg RCC_MCODiv_8: division by 8 applied to MCO clock
- * @arg RCC_MCODiv_16: division by 16 applied to MCO clock
- * @retval None
- */
-void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv)
-{
- /* Check the parameters */
- assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
- assert_param(IS_RCC_MCO_DIV(RCC_MCODiv));
-
- /* Select MCO clock source and prescaler */
- *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCOSource | RCC_MCODiv;
-}
-
-/**
- * @brief Checks whether the specified RCC flag is set or not.
- * @param RCC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
- * @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
- * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
- * @arg RCC_FLAG_PLLRDY: PLL clock ready
- * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
- * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
- * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
- * @arg RCC_FLAG_PINRST: Pin reset
- * @arg RCC_FLAG_PORRST: POR/PDR reset
- * @arg RCC_FLAG_SFTRST: Software reset
- * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
- * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
- * @arg RCC_FLAG_LPWRRST: Low Power reset
- * @retval The new state of RCC_FLAG (SET or RESET).
- */
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
-{
- uint32_t tmp = 0;
- uint32_t statusreg = 0;
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_FLAG(RCC_FLAG));
-
- /* Get the RCC register index */
- tmp = RCC_FLAG >> 5;
-
- if (tmp == 1) /* The flag to check is in CR register */
- {
- statusreg = RCC->CR;
- }
- else /* The flag to check is in CSR register (tmp == 2) */
- {
- statusreg = RCC->CSR;
- }
-
- /* Get the flag position */
- tmp = RCC_FLAG & FLAG_MASK;
-
- if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the RCC reset flags.
- * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
- * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
- * @param None
- * @retval None
- */
-void RCC_ClearFlag(void)
-{
- /* Set RMVF bit to clear the reset flags */
- RCC->CSR |= RCC_CSR_RMVF;
-}
-
-/**
- * @brief Checks whether the specified RCC interrupt has occurred or not.
- * @param RCC_IT: specifies the RCC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: PLL ready interrupt
- * @arg RCC_IT_MSIRDY: MSI ready interrupt
- * @arg RCC_IT_CSS: Clock Security System interrupt
- * @retval The new state of RCC_IT (SET or RESET).
- */
-ITStatus RCC_GetITStatus(uint8_t RCC_IT)
-{
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_RCC_GET_IT(RCC_IT));
-
- /* Check the status of the specified RCC interrupt */
- if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the RCC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the RCC's interrupt pending bits.
- * @param RCC_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: PLL ready interrupt
- * @arg RCC_IT_MSIRDY: MSI ready interrupt
- * @arg RCC_IT_CSS: Clock Security System interrupt
- * @retval None
- */
-void RCC_ClearITPendingBit(uint8_t RCC_IT)
-{
- /* Check the parameters */
- assert_param(IS_RCC_CLEAR_IT(RCC_IT));
-
- /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
- pending bits */
- *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c
deleted file mode 100644
index 67e4b38..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c
+++ /dev/null
@@ -1,641 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l1xx_spi.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief This file provides all the SPI firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_spi.h"
-#include "stm32l1xx_rcc.h"
-
-/** @addtogroup STM32L1xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SPI
- * @brief SPI driver modules
- * @{
- */
-
-/** @defgroup SPI_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup SPI_Private_Defines
- * @{
- */
-
-/* SPI registers Masks */
-#define CR1_CLEAR_MASK ((uint16_t)0x3040)
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the SPIx peripheral registers to their default
- * reset values.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @retval None
- */
-void SPI_DeInit(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- if (SPIx == SPI1)
- {
- /* Enable SPI1 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
- /* Release SPI1 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
- }
- else
- {
- if (SPIx == SPI2)
- {
- /* Enable SPI2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
- /* Release SPI2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the SPIx peripheral according to the specified
- * parameters in the SPI_InitStruct.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
- * contains the configuration information for the specified SPI peripheral.
- * @retval None
- */
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
-{
- uint16_t tmpreg = 0;
-
- /* check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Check the SPI parameters */
- assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
- assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
- assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
- assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
- assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
- assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
- assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
- assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
- assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
-
-/*---------------------------- SPIx CR1 Configuration ------------------------*/
- /* Get the SPIx CR1 value */
- tmpreg = SPIx->CR1;
- /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
- tmpreg &= CR1_CLEAR_MASK;
- /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
- master/salve mode, CPOL and CPHA */
- /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
- /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
- /* Set LSBFirst bit according to SPI_FirstBit value */
- /* Set BR bits according to SPI_BaudRatePrescaler value */
- /* Set CPOL bit according to SPI_CPOL value */
- /* Set CPHA bit according to SPI_CPHA value */
- tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
- SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
- SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
- SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
- /* Write to SPIx CR1 */
- SPIx->CR1 = tmpreg;
-
-/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
- /* Write to SPIx CRCPOLY */
- SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
-}
-
-/**
- * @brief Fills each SPI_InitStruct member with its default value.
- * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
-{
-/*--------------- Reset SPI init structure parameters values -----------------*/
- /* Initialize the SPI_Direction member */
- SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
- /* initialize the SPI_Mode member */
- SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
- /* initialize the SPI_DataSize member */
- SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
- /* Initialize the SPI_CPOL member */
- SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
- /* Initialize the SPI_CPHA member */
- SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
- /* Initialize the SPI_NSS member */
- SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
- /* Initialize the SPI_BaudRatePrescaler member */
- SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
- /* Initialize the SPI_FirstBit member */
- SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
- /* Initialize the SPI_CRCPolynomial member */
- SPI_InitStruct->SPI_CRCPolynomial = 7;
-}
-
-
-/**
- * @brief Enables or disables the specified SPI peripheral.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @param NewState: new state of the SPIx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI peripheral */
- SPIx->CR1 |= SPI_CR1_SPE;
- }
- else
- {
- /* Disable the selected SPI peripheral */
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
- }
-}
-
-/**
- * @brief Enables or disables the specified SPI interrupts.
- * @param SPIx: where x can be 1 or 2 in SPI mode
- * @param SPI_IT: specifies the SPI interrupt source to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt mask
- * @arg SPI_IT_RXNE: Rx buffer not empty interrupt mask
- * @arg SPI_IT_ERR: Error interrupt mask
- * @param NewState: new state of the specified SPI interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_IT, FunctionalState NewState)
-{
- uint16_t itpos = 0, itmask = 0 ;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_CONFIG_IT(SPI_IT));
-
- /* Get the SPI IT index */
- itpos = SPI_IT >> 4;
-
- /* Set the IT mask */
- itmask = (uint16_t)1 << (uint16_t)itpos;
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI interrupt */
- SPIx->CR2 |= itmask;
- }
- else
- {
- /* Disable the selected SPI interrupt */
- SPIx->CR2 &= (uint16_t)~itmask;
- }
-}
-
-/**
- * @brief Enables or disables the SPIx DMA interface.
- * @param SPIx: where x can be 1 or 2 in SPI mode
- * @param SPI_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg SPI_DMAReq_Tx: Tx buffer DMA transfer request
- * @arg SPI_DMAReq_Rx: Rx buffer DMA transfer request
- * @param NewState: new state of the selected SPI DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_DMAREQ(SPI_DMAReq));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI DMA requests */
- SPIx->CR2 |= SPI_DMAReq;
- }
- else
- {
- /* Disable the selected SPI DMA requests */
- SPIx->CR2 &= (uint16_t)~SPI_DMAReq;
- }
-}
-
-/**
- * @brief Transmits a Data through the SPIx peripheral.
- * @param SPIx: where x can be 1 or 2 in SPI mode
- * @param Data : Data to be transmitted.
- * @retval None
- */
-void SPI_SendData(SPI_TypeDef* SPIx, uint16_t Data)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Write in the DR register the data to be sent */
- SPIx->DR = Data;
-}
-
-/**
- * @brief Returns the most recent received data by the SPIx peripheral.
- * @param SPIx: where x can be 1 or 2 in SPI mode
- * @retval The value of the received data.
- */
-uint16_t SPI_ReceiveData(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Return the data in the DR register */
- return SPIx->DR;
-}
-
-/**
- * @brief Configures internally by software the NSS pin for the selected SPI.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
- * This parameter can be one of the following values:
- * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
- * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
- * @retval None
- */
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
- if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
- {
- /* Set NSS pin internally by software */
- SPIx->CR1 |= SPI_NSSInternalSoft_Set;
- }
- else
- {
- /* Reset NSS pin internally by software */
- SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the SS output for the selected SPI.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @param NewState: new state of the SPIx SS output.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI SS output */
- SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;
- }
- else
- {
- /* Disable the selected SPI SS output */
- SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
- }
-}
-
-/**
- * @brief Configures the data size for the selected SPI.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @param SPI_DataSize: specifies the SPI data size.
- * This parameter can be one of the following values:
- * @arg SPI_DataSize_16b: Set data frame format to 16bit
- * @arg SPI_DataSize_8b: Set data frame format to 8bit
- * @retval None
- */
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DATASIZE(SPI_DataSize));
- /* Clear DFF bit */
- SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
- /* Set new DFF bit value */
- SPIx->CR1 |= SPI_DataSize;
-}
-
-/**
- * @brief Transmit the SPIx CRC value.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @retval None
- */
-void SPI_TransmitCRC(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Enable the selected SPI CRC transmission */
- SPIx->CR1 |= SPI_CR1_CRCNEXT;
-}
-
-/**
- * @brief Enables or disables the CRC value calculation of the transfered bytes.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @param NewState: new state of the SPIx CRC value calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI CRC calculation */
- SPIx->CR1 |= SPI_CR1_CRCEN;
- }
- else
- {
- /* Disable the selected SPI CRC calculation */
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
- }
-}
-
-/**
- * @brief Returns the transmit or the receive CRC register value for the specified SPI.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @param SPI_CRC: specifies the CRC register to be read.
- * This parameter can be one of the following values:
- * @arg SPI_CRC_Tx: Selects Tx CRC register
- * @arg SPI_CRC_Rx: Selects Rx CRC register
- * @retval The selected CRC register value..
- */
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
-{
- uint16_t crcreg = 0;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_CRC(SPI_CRC));
- if (SPI_CRC != SPI_CRC_Rx)
- {
- /* Get the Tx CRC register */
- crcreg = SPIx->TXCRCR;
- }
- else
- {
- /* Get the Rx CRC register */
- crcreg = SPIx->RXCRCR;
- }
- /* Return the selected CRC register */
- return crcreg;
-}
-
-/**
- * @brief Returns the CRC Polynomial register value for the specified SPI.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @retval The CRC Polynomial register value.
- */
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Return the CRC polynomial register */
- return SPIx->CRCPR;
-}
-
-/**
- * @brief Selects the data transfer direction in bi-directional mode for the specified SPI.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @param SPI_Direction: specifies the data transfer direction in bi-directional mode.
- * This parameter can be one of the following values:
- * @arg SPI_Direction_Tx: Selects Tx transmission direction
- * @arg SPI_Direction_Rx: Selects Rx receive direction
- * @retval None
- */
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DIRECTION(SPI_Direction));
- if (SPI_Direction == SPI_Direction_Tx)
- {
- /* Set the Tx only mode */
- SPIx->CR1 |= SPI_Direction_Tx;
- }
- else
- {
- /* Set the Rx only mode */
- SPIx->CR1 &= SPI_Direction_Rx;
- }
-}
-
-/**
- * @brief Checks whether the specified SPI flag is set or not.
- * @param SPIx: where x can be 1 or 2 in SPI mode
- * @param SPI_FLAG: specifies the SPI flag to check.
- * This parameter can be one of the following values:
- * @arg SPI_FLAG_TXE: Transmit buffer empty flag.
- * @arg SPI_FLAG_RXNE: Receive buffer not empty flag.
- * @arg SPI_FLAG_BSY: Busy flag.
- * @arg SPI_FLAG_OVR: Overrun flag.
- * @arg SPI_FLAG_MODF: Mode Fault flag.
- * @arg SPI_FLAG_CRCERR: CRC Error flag.
- * @retval The new state of SPI_FLAG (SET or RESET).
- */
-FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_GET_FLAG(SPI_FLAG));
- /* Check the status of the specified SPI flag */
- if ((SPIx->SR & SPI_FLAG) != (uint16_t)RESET)
- {
- /* SPI_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the SPIx CRC Error (CRCERR) flag.
- * @param SPIx: where x can be 1 or 2 in SPI mode
- * @param SPI_FLAG: specifies the SPI flag to clear.
- * This function clears only CRCERR flag.
- * @note
- * - OVR (OverRun error) flag is cleared by software sequence: a read
- * operation to SPI_DR register (SPI_ReceiveData()) followed by a read
- * operation to SPI_SR register (SPI_GetFlagStatus()).
- * - UDR (UnderRun error) flag is cleared by a read operation to
- * SPI_SR register (SPI_GetFlagStatus()).
- * - MODF (Mode Fault) flag is cleared by software sequence: a read/write
- * operation to SPI_SR register (SPI_GetFlagStatus()) followed by a
- * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
- * @retval None
- */
-void SPI_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_CLEAR_FLAG(SPI_FLAG));
-
- /* Clear the selected SPI CRC Error (CRCERR) flag */
- SPIx->SR = (uint16_t)~SPI_FLAG;
-}
-
-/**
- * @brief Checks whether the specified SPI interrupt has occurred or not.
- * @param SPIx: where x can be
- * - 1 or 2 in SPI mode
- * @param SPI_IT: specifies the SPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Transmit buffer empty interrupt.
- * @arg SPI_IT_RXNE: Receive buffer not empty interrupt.
- * @arg SPI_IT_OVR: Overrun interrupt.
- * @arg SPI_IT_MODF: Mode Fault interrupt.
- * @arg SPI_IT_CRCERR: CRC Error interrupt.
- * @retval The new state of SPI_IT (SET or RESET).
- */
-ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itpos = 0, itmask = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_GET_IT(SPI_IT));
-
- /* Get the SPI IT index */
- itpos = 0x01 << (SPI_IT & 0x0F);
-
- /* Get the SPI IT mask */
- itmask = SPI_IT >> 4;
-
- /* Set the IT mask */
- itmask = 0x01 << itmask;
-
- /* Get the SPI_IT enable bit status */
- enablestatus = (SPIx->CR2 & itmask) ;
-
- /* Check the status of the specified SPI interrupt */
- if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
- {
- /* SPI_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_IT is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
- * @param SPIx: where x can be
- * - 1 or 2 in SPI mode
- * @param SPI_IT: specifies the SPI interrupt pending bit to clear.
- * This function clears only CRCERR intetrrupt pending bit.
- * @note
- * - OVR (OverRun Error) interrupt pending bit is cleared by software
- * sequence: a read operation to SPI_DR register (SPI_ReceiveData())
- * followed by a read operation to SPI_SR register (SPI_GetITStatus()).
- * - UDR (UnderRun Error) interrupt pending bit is cleared by a read
- * operation to SPI_SR register (SPI_GetITStatus()).
- * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
- * a read/write operation to SPI_SR register (SPI_GetITStatus())
- * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable
- * the SPI).
- * @retval None
- */
-void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_IT)
-{
- uint16_t itpos = 0;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_CLEAR_IT(SPI_IT));
-
- /* Get the SPI IT index */
- itpos = 0x01 << (SPI_IT & 0x0F);
-
- /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
- SPIx->SR = (uint16_t)~itpos;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c
deleted file mode 100644
index 0d9bef1..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c
+++ /dev/null
@@ -1,494 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l1xx_syscfg.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief This file provides all the SYSCFG and RI firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_syscfg.h"
-#include "stm32l1xx_rcc.h"
-
-/** @addtogroup STM32L1xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SYSCFG
- * @brief SYSCFG driver modules
- * @{
- */
-
-/** @defgroup SYSCFG_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_Private_Defines
- * @{
- */
-
-#define RI_ICR_RESET_VALUE ((uint32_t)0x00000000) /*!< ICR Reset value */
-#define RI_ASCR1_RESET_VALUE ((uint32_t)0x00000000) /*!< ASCR1 Reset value */
-#define RI_ASCR2_RESET_VALUE ((uint32_t)0x00000000) /*!< ASCR2 Reset value */
-#define RI_HYSCR1_RESET_VALUE ((uint32_t)0x00000000) /*!< HYSCR1 Reset value */
-#define RI_HYSCR2_RESET_VALUE ((uint32_t)0x00000000) /*!< HYSCR2 Reset value */
-#define RI_HYSCR3_RESET_VALUE ((uint32_t)0x00000000) /*!< HYSCR3 Reset value */
-
-#define TIM_SELECT_MASK ((uint32_t)0xFFFCFFFF) /*!< TIM select mask */
-#define IC_ROUTING_MASK ((uint32_t)0x0000000F) /*!< Input Capture routing mask */
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_Private_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_Private_FunctionPrototypes
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the syscfg registers to their default reset values.
- * @param None
- * @retval None
- * @ Note: MEMRMP bits are not reset by APB2 reset.
- */
-void SYSCFG_DeInit(void)
-{
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);
-}
-
-/**
- * @brief Changes the mapping of the specified pin.
- * @param SYSCFG_Memory: selects the memory remapping.
- * This parameter can be one of the following values:
- * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
- * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
- * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
- * @retval None
- */
-void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
-{
- /* Check the parameters */
- assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));
- SYSCFG->MEMRMP = SYSCFG_MemoryRemap;
-}
-
-/**
- * @brief Control the internal pull-up on USB DP line.
- * @param NewState: New state of the switch control mode.
- * This parameter can be ENABLE: Connect internal pull-up on USB DP line.
- * or DISABLE: Disconnect internal pull-up on USB DP line.
- * @retval None
- */
-void SYSCFG_USBPuCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Connect internal pull-up on USB DP line */
- SYSCFG->PMC |= (uint32_t) SYSCFG_PMC_USB_PU;
- }
- else
- {
- /* Disconnect internal pull-up on USB DP line */
- SYSCFG->PMC &= (uint32_t)(~SYSCFG_PMC_USB_PU);
- }
-}
-
-/**
- * @brief Selects the GPIO pin used as EXTI Line.
- * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source
- * for EXTI lines where x can be (A, B, C, D, E or H).
- * @param EXTI_PinSourcex: specifies the EXTI line to be configured.
- * This parameter can be EXTI_PinSourcex where x can be (0..15)
- * @retval None
- */
-void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
-{
- uint32_t tmp = 0x00;
-
- /* Check the parameters */
- assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
- assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
-
- tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
- SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
- SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
-}
-
-/**
- * @brief Deinitializes the RI registers to their default reset values.
- * @param None
- * @retval None
- */
-void SYSCFG_RIDeInit(void)
-{
- RI->ICR = RI_ICR_RESET_VALUE; /*!< Set RI->ICR to reset value */
- RI->ASCR1 = RI_ASCR1_RESET_VALUE; /*!< Set RI->ASCR1 to reset value */
- RI->ASCR2 = RI_ASCR2_RESET_VALUE; /*!< Set RI->ASCR2 to reset value */
- RI->HYSCR1 = RI_HYSCR1_RESET_VALUE; /*!< Set RI->HYSCR1 to reset value */
- RI->HYSCR2 = RI_HYSCR2_RESET_VALUE; /*!< Set RI->HYSCR2 to reset value */
- RI->HYSCR3 = RI_HYSCR3_RESET_VALUE; /*!< Set RI->HYSCR3 to reset value */
-}
-
-/**
- * @brief Configures the routing interface to select which Timer to be routed.
- * @param TIM_Select: Timer select.
- * This parameter can be one of the following values:
- * @arg TIM_Select_None : No timer selected
- * @arg TIM_Select_TIM2 : Timer 2 selected
- * @arg TIM_Select_TIM3 : Timer 3 selected
- * @arg TIM_Select_TIM4 : Timer 4 selected
- * @retval None.
- */
-void SYSCFG_RITIMSelect(uint32_t TIM_Select)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RI_TIM(TIM_Select));
-
- /* Get the old register value */
- tmpreg = RI->ICR;
-
- /* Clear the TIMx select bits */
- tmpreg &= TIM_SELECT_MASK;
-
- /* Select the Timer */
- tmpreg |= (TIM_Select);
-
- /* Write to RI->ICR register */
- RI->ICR = tmpreg;
-}
-
-/**
- * @brief Configures the routing interface to select which Timer Input Capture
- * to be routed to a selected pin.
- * @param RI_InputCapture selects which input capture to be routed.
- * This parameter can be one of the following values:
- * @arg RI_InputCapture_IC1: Input capture 1 is slected.
- * @arg RI_InputCapture_IC2: Input capture 2 is slected.
- * @arg RI_InputCapture_IC3: Input capture 3 is slected.
- * @arg RI_InputCapture_IC4: Input capture 4 is slected.
- * @param RI_InputCaptureRouting: selects which pin to be routed to Input Capture.
- * This parameter can be one of the following values:
- * @arg RI_InputCaptureRouting_0 to RI_InputCaptureRouting_15
- * @Note Input capture selection bits are not reset by this function.
- * @retval None.
- */
-void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RI_INPUTCAPTURE(RI_InputCapture));
- assert_param(IS_RI_INPUTCAPTURE_ROUTING(RI_InputCaptureRouting));
-
- /* Get the old register value */
- tmpreg = RI->ICR;
-
- /* Select input captures to be routed */
- tmpreg |= (RI_InputCapture);
-
- if((RI_InputCapture & RI_InputCapture_IC1) == RI_InputCapture_IC1)
- {
- /* Clear the input capture select bits */
- tmpreg &= (uint32_t)(~IC_ROUTING_MASK);
-
- /* Set RI_InputCaptureRouting bits */
- tmpreg |= (uint32_t)( RI_InputCaptureRouting);
- }
-
- if((RI_InputCapture & RI_InputCapture_IC2) == RI_InputCapture_IC2)
- {
- /* Clear the input capture select bits */
- tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 4));
-
- /* Set RI_InputCaptureRouting bits */
- tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 4));
- }
-
- if((RI_InputCapture & RI_InputCapture_IC3) == RI_InputCapture_IC3)
- {
- /* Clear the input capture select bits */
- tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 8));
-
- /* Set RI_InputCaptureRouting bits */
- tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 8));
- }
-
- if((RI_InputCapture & RI_InputCapture_IC4) == RI_InputCapture_IC4)
- {
- /* Clear the input capture select bits */
- tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 12));
-
- /* Set RI_InputCaptureRouting bits */
- tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 12));
- }
-
- /* Write to RI->ICR register */
- RI->ICR = tmpreg;
-}
-/**
- * @brief Configures the Pull-up and Pull-down Resistors
- * @param RI_Resistor selects the resistor to connect.
- * This parameter can be one of the following values:
- * @arg RI_Resistor_10KPU : 10K pull-up resistor
- * @arg RI_Resistor_400KPU : 400K pull-up resistor
- * @arg RI_Resistor_10KPD : 10K pull-down resistor
- * @arg RI_Resistor_400KPD : 400K pull-down resistor
- * @param NewState: New state of the analog switch associated to the selected resistor.
- * This parameter can be:
- * ENABLE so the selected resistor is connected
- * or DISABLE so the selected resistor is disconnected
- * @retval None
- */
-void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RI_RESISTOR(RI_Resistor));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the resistor */
- COMP->CSR |= (uint32_t) RI_Resistor;
- }
- else
- {
- /* Disable the Resistor */
- COMP->CSR &= (uint32_t) (~RI_Resistor);
- }
-}
-
-/**
- * @brief Close or Open the routing interface Input Output switches.
- * @param RI_IOSwitch: selects the I/O analog switch number.
- * This parameter can be one of the following values:
- * @arg RI_IOSwitch_CH0 --> RI_IOSwitch_CH15
- * @argRI_IOSwitch_CH18 --> RI_IOSwitch_CH25
- * @arg RI_IOSwitch_GR10_1 --> RI_IOSwitch_GR10_4
- * @arg RI_IOSwitch_GR6_1 --> RI_IOSwitch_GR6_2
- * @arg RI_IOSwitch_GR5_1 --> RI_IOSwitch_GR5_3
- * @arg RI_IOSwitch_GR4_1 --> RI_IOSwitch_GR4_3
- * @arg RI_IOSwitch_VCOMP
- * @param NewState: New state of the analog switch.
- * This parameter can be
- * ENABLE so the Input Output switch is closed
- * or DISABLE so the Input Output switch is open
- * @retval None
- */
-void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState)
-{
- uint32_t IOSwitchmask = 0;
-
- /* Check the parameters */
- assert_param(IS_RI_IOSWITCH(RI_IOSwitch));
-
- /* Read Analog switch register index*/
- IOSwitchmask = RI_IOSwitch >> 28;
-
- /** Get Bits[27:0] of the IO switch */
- RI_IOSwitch &= 0x0FFFFFFF;
-
-
- if (NewState != DISABLE)
- {
- if (IOSwitchmask != 0)
- {
- /* Close the analog switches */
- RI->ASCR1 |= RI_IOSwitch;
- }
- else
- {
- /* Open the analog switches */
- RI->ASCR2 |= RI_IOSwitch;
- }
- }
- else
- {
- if (IOSwitchmask != 0)
- {
- /* Close the analog switches */
- RI->ASCR1 &= (~ (uint32_t)RI_IOSwitch);
- }
- else
- {
- /* Open the analog switches */
- RI->ASCR2 &= (~ (uint32_t)RI_IOSwitch);
- }
- }
-}
-
-/**
- * @brief Enable or disable the switch control mode.
- * @param NewState: New state of the switch control mode. This parameter can
- * be ENABLE: ADC analog switches closed if the corresponding
- * I/O switch is also closed.
- * or DISABLE: ADC analog switches open or controlled by the ADC interface.
- * @retval None
- */
-void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Switch control mode */
- RI->ASCR1 |= (uint32_t) RI_ASCR1_SCM;
- }
- else
- {
- /* Disable the Switch control mode */
- RI->ASCR1 &= (uint32_t)(~RI_ASCR1_SCM);
- }
-}
-
-/**
- * @brief Enable or disable Hysteresis of the input schmitt triger of Ports A..E
- * @param RI_Port: selects the GPIO Port.
- * This parameter can be one of the following values:
- * @arg RI_PortA : Port A is selected
- * @arg RI_PortB : Port B is selected
- * @arg RI_PortC : Port C is selected
- * @arg RI_PortD : Port D is selected
- * @arg RI_PortE : Port E is selected
- * @param RI_Pin : Selects the pin(s) on which to enable or disable hysteresis.
- * This parameter can any value from RI_Pin_x where x can be (0..15) or RI_Pin_All.
- * @param NewState new state of the Hysteresis.
- * This parameter can be:
- * ENABLE so the Hysteresis is on
- * or DISABLE so the Hysteresis is off
- * @retval None
- */
-void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin,
- FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RI_PORT(RI_Port));
- assert_param(IS_RI_PIN(RI_Pin));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(RI_Port == RI_PortA)
- {
- if (NewState != DISABLE)
- {
- /* Hysteresis on */
- RI->HYSCR1 &= (uint32_t)~((uint32_t)RI_Pin);
- }
- else
- {
- /* Hysteresis off */
- RI->HYSCR1 |= (uint32_t) RI_Pin;
- }
- }
-
- else if(RI_Port == RI_PortB)
- {
-
- if (NewState != DISABLE)
- {
- /* Hysteresis on */
- RI->HYSCR1 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);
- }
- else
- {
- /* Hysteresis off */
- RI->HYSCR1 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);
- }
- }
-
- else if(RI_Port == RI_PortC)
- {
-
- if (NewState != DISABLE)
- {
- /* Hysteresis on */
- RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin));
- }
- else
- {
- /* Hysteresis off */
- RI->HYSCR2 |= (uint32_t) (RI_Pin );
- }
- }
- else if(RI_Port == RI_PortD)
- {
- if (NewState != DISABLE)
- {
- /* Hysteresis on */
- RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);
- }
- else
- {
- /* Hysteresis off */
- RI->HYSCR2 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);
-
- }
- }
- else /* RI_Port == RI_PortE */
- {
- if (NewState != DISABLE)
- {
- /* Hysteresis on */
- RI->HYSCR3 &= (uint32_t) (~((uint32_t)RI_Pin));
- }
- else
- {
- /* Hysteresis off */
- RI->HYSCR3 |= (uint32_t) (RI_Pin );
- }
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_tim.c b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_tim.c
deleted file mode 100644
index 964dfae..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_tim.c
+++ /dev/null
@@ -1,2554 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l1xx_tim.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief This file provides all the TIM firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_tim.h"
-#include "stm32l1xx_rcc.h"
-
-/** @addtogroup STM32L1xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup TIM
- * @brief TIM driver modules
- * @{
- */
-
-/** @defgroup TIM_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_Defines
- * @{
- */
-
-/* ---------------------- TIM registers bit mask ------------------------ */
-#define SMCR_ETR_MASK ((uint16_t)0x00FF)
-#define CCMR_OFFSET ((uint16_t)0x0018)
-#define CCER_CCE_SET ((uint16_t)0x0001)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_FunctionPrototypes
- * @{
- */
-
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the TIMx peripheral registers to their default reset values.
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
- * @retval None
- *
- */
-void TIM_DeInit(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- if (TIMx == TIM2)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
- }
- else if (TIMx == TIM3)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
- }
- else if (TIMx == TIM4)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
- }
-
- else if (TIMx == TIM6)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
- }
- else if (TIMx == TIM7)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
- }
-
- else if (TIMx == TIM9)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
- }
- else if (TIMx == TIM10)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
- }
- else
- {
- if (TIMx == TIM11)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
- }
- }
-
-}
-
-/**
- * @brief Initializes the TIMx Time Base Unit peripheral according to
- * the specified parameters in the TIM_TimeBaseInitStruct.
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
- * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
- * structure that contains the configuration information for
- * the specified TIM peripheral.
- * @retval None
- */
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- uint16_t tmpcr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
- assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
-
- tmpcr1 = TIMx->CR1;
-
- if(((TIMx) == TIM2) || ((TIMx) == TIM3) || ((TIMx) == TIM4))
- {
- /* Select the Counter Mode */
- tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
- }
-
- if(((TIMx) != TIM6) && ((TIMx) != TIM7))
- {
- /* Set the clock division */
- tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
- }
-
- TIMx->CR1 = tmpcr1;
-
- /* Set the Autoreload value */
- TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
-
- /* Set the Prescaler value */
- TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
-
- /* Generate an update event to reload the Prescaler value immediatly */
- TIMx->EGR = TIM_PSCReloadMode_Immediate;
-}
-
-/**
- * @brief Initializes the TIMx Channel1 according to the specified
- * parameters in the TIM_OCInitStruct.
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM
- * peripheral.
- * @retval None
- */
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_23491011_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
-
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
- /* Set the Output Compare Polarity */
- tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
-
- /* Set the Output State */
- tmpccer |= TIM_OCInitStruct->TIM_OutputState;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel2 according to the specified
- * parameters in the TIM_OCInitStruct.
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM
- * peripheral.
- * @retval None
- */
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_2349_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel3 according to the specified
- * parameters in the TIM_OCInitStruct.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM
- * peripheral.
- * @retval None
- */
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
-
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel4 according to the specified
- * parameters in the TIM_OCInitStruct.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM
- * peripheral.
- * @retval None
- */
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 2: Reset the CC4E Bit */
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIM peripheral according to the specified
- * parameters in the TIM_ICInitStruct.
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
- * that contains the configuration information for the specified TIM
- * peripheral.
- * @retval None
- */
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_23491011_PERIPH(TIMx));
- assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
- assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
- assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
-
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
- {
- /* TI2 Configuration */
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
- {
- /* TI3 Configuration */
- TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- /* TI4 Configuration */
- TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/**
- * @brief Configures the TIM peripheral according to the specified
- * parameters in the TIM_ICInitStruct to measure an external PWM signal.
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
- * that contains the configuration information for the specified TIM
- * peripheral.
- * @retval None
- */
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
- uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
- /* Check the parameters */
- assert_param(IS_TIM_2349_PERIPH(TIMx));
- /* Select the Opposite Input Polarity */
- if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
- {
- icoppositepolarity = TIM_ICPolarity_Falling;
- }
- else
- {
- icoppositepolarity = TIM_ICPolarity_Rising;
- }
- /* Select the Opposite Input */
- if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
- {
- icoppositeselection = TIM_ICSelection_IndirectTI;
- }
- else
- {
- icoppositeselection = TIM_ICSelection_DirectTI;
- }
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- /* TI2 Configuration */
- TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- /* TI2 Configuration */
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- /* TI1 Configuration */
- TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/**
- * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
- * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- /* Set the default configuration */
- TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
- TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
- TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
- TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
-}
-
-/**
- * @brief Fills each TIM_OCInitStruct member with its default value.
- * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- /* Set the default configuration */
- TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
- TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
- TIM_OCInitStruct->TIM_Pulse = 0x0000;
- TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
-}
-
-/**
- * @brief Fills each TIM_ICInitStruct member with its default value.
- * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Set the default configuration */
- TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
- TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
- TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
- TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
- TIM_ICInitStruct->TIM_ICFilter = 0x00;
-}
-
-/**
- * @brief Enables or disables the specified TIM peripheral.
- * @param TIMx: where x can be 2 to 11 to select the TIMx peripheral.
- * @param NewState: new state of the TIMx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TIM Counter */
- TIMx->CR1 |= TIM_CR1_CEN;
- }
- else
- {
- /* Disable the TIM Counter */
- TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
- }
-}
-
-/**
- * @brief Enables or disables the specified TIM interrupts.
- * @param TIMx: where x can be 2 to 11 to select the TIMx peripheral.
- * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg TIM_IT_Update: TIM update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @note
- * - TIM6 and TIM7 can only generate an update interrupt.
- * - TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4 and TIM_IT_Trigger can not be used with TIM10 and TIM11
- * - TIM_IT_CC3, TIM_IT_CC4 can not be used with TIM9.
- * @param NewState: new state of the TIM interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_IT(TIM_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt sources */
- TIMx->DIER |= TIM_IT;
- }
- else
- {
- /* Disable the Interrupt sources */
- TIMx->DIER &= (uint16_t)~TIM_IT;
- }
-}
-
-/**
- * @brief Configures the TIMx event to be generate by software.
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
- * @param TIM_EventSource: specifies the event source.
- * This parameter can be one or more of the following values:
- * @arg TIM_EventSource_Update: Timer update Event source
- * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
- * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
- * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
- * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
- * @arg TIM_EventSource_Trigger: Timer Trigger Event source
- * @note
- * - TIM6 and TIM7 can only generate an update event.
- * - TIM9 can only generate an update event, Capture Compare 1 event,
- * Capture Compare 2 event and TIM_EventSource_Trigger.
- * - TIM10 and TIM11 can only generate an update event and Capture Compare 1 event.
- * @retval None
- */
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
- /* Set the event sources */
- TIMx->EGR = TIM_EventSource;
-}
-
-/**
- * @brief Configures the TIMxÂ’s DMA interface.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param TIM_DMABase: DMA Base address.
- * This parameter can be one of the following values:
- * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
- * TIM_DMABase_DIER, TIM_DMABase_SR, TIM_DMABase_EGR,
- * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
- * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
- * TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3,
- * TIM_DMABase_CCR4, TIM_DMABase_DCR.
- * @param TIM_DMABurstLength: DMA Burst length.
- * This parameter can be one value between:
- * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.
- * @retval None
- */
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
-{
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
- assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
- /* Set the DMA Base and the DMA Burst Length */
- TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
-}
-
-/**
- * @brief Enables or disables the TIMxÂ’s DMA Requests.
- * @param TIMx: where x can be 2, 3, 4, 6 or 7 to select the TIM peripheral.
- * @param TIM_DMASource: specifies the DMA Request sources.
- * This parameter can be any combination of the following values:
- * @arg TIM_DMA_Update: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_Trigger: TIM Trigger DMA source
- * @param NewState: new state of the DMA Request sources.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_23467_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DMA sources */
- TIMx->DIER |= TIM_DMASource;
- }
- else
- {
- /* Disable the DMA sources */
- TIMx->DIER &= (uint16_t)~TIM_DMASource;
- }
-}
-
-/**
- * @brief Configures the TIMx interrnal Clock
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
- * @retval None
- */
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_2349_PERIPH(TIMx));
- /* Disable slave mode to clock the prescaler directly with the internal clock */
- TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
-}
-
-/**
- * @brief Configures the TIMx Internal Trigger as External Clock
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
- * @param TIM_ITRSource: Trigger source.
- * This parameter can be one of the following values:
- * @param TIM_TS_ITR0: Internal Trigger 0
- * @param TIM_TS_ITR1: Internal Trigger 1
- * @param TIM_TS_ITR2: Internal Trigger 2
- * @param TIM_TS_ITR3: Internal Trigger 3
- * @retval None
- */
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_2349_PERIPH(TIMx));
- assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
- /* Select the Internal Trigger */
- TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
- * @brief Configures the TIMx Trigger as External Clock
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
- * @param TIM_TIxExternalCLKSource: Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
- * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
- * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
- * @param TIM_ICPolarity: specifies the TIx Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param ICFilter : specifies the filter value.
- * This parameter must be a value between 0x0 and 0xF.
- * @retval None
- */
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
- uint16_t TIM_ICPolarity, uint16_t ICFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_2349_PERIPH(TIMx));
- assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
- assert_param(IS_TIM_IC_FILTER(ICFilter));
-
- /* Configure the Timer Input Clock Source */
- if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
- {
- TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
- else
- {
- TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
- /* Select the Trigger source */
- TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
- * @brief Configures the External clock Mode1
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_2349_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Reset the SMS Bits */
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
- /* Select the External clock mode1 */
- tmpsmcr |= TIM_SlaveMode_External1;
- /* Select the Trigger selection : ETRF */
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
- tmpsmcr |= TIM_TS_ETRF;
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Configures the External clock Mode2
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_23491011_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
- /* Enable the External clock mode2 */
- TIMx->SMCR |= TIM_SMCR_ECE;
-}
-
-/**
- * @brief Configures the TIMx External Trigger (ETR).
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_23491011_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- tmpsmcr = TIMx->SMCR;
- /* Reset the ETR Bits */
- tmpsmcr &= SMCR_ETR_MASK;
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Configures the TIMx Prescaler.
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
- * @param Prescaler: specifies the Prescaler Register value
- * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
- * This parameter can be one of the following values:
- * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
- * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
- * @retval None
- */
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
-
- /* Set the Prescaler value */
- TIMx->PSC = Prescaler;
- /* Set or reset the UG Bit */
- TIMx->EGR = TIM_PSCReloadMode;
-}
-
-/**
- * @brief Specifies the TIMx Counter Mode to be used.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param TIM_CounterMode: specifies the Counter Mode to be used
- * This parameter can be one of the following values:
- * @arg TIM_CounterMode_Up: TIM Up Counting Mode
- * @arg TIM_CounterMode_Down: TIM Down Counting Mode
- * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
- * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
- * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
- * @retval None
- */
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
-{
- uint16_t tmpcr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
-
- tmpcr1 = TIMx->CR1;
- /* Reset the CMS and DIR Bits */
- tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
- /* Set the Counter Mode */
- tmpcr1 |= TIM_CounterMode;
- /* Write to TIMx CR1 register */
- TIMx->CR1 = tmpcr1;
-}
-
-/**
- * @brief Selects the Input Trigger source
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
- * @param TIM_InputTriggerSource: The Input Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
- * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
- * @arg TIM_TS_ETRF: External Trigger input
- * @retval None
- */
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_23491011_PERIPH(TIMx));
- assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Reset the TS Bits */
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
- /* Set the Input Trigger source */
- tmpsmcr |= TIM_InputTriggerSource;
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Configures the TIMx Encoder Interface.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
- * This parameter can be one of the following values:
- * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
- * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
- * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
- * on the level of the other input.
- * @param TIM_IC1Polarity: specifies the IC1 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_ICPolarity_Falling: IC Falling edge.
- * @arg TIM_ICPolarity_Rising: IC Rising edge.
- * @param TIM_IC2Polarity: specifies the IC2 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_ICPolarity_Falling: IC Falling edge.
- * @arg TIM_ICPolarity_Rising: IC Rising edge.
- * @retval None
- */
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
-{
- uint16_t tmpsmcr = 0;
- uint16_t tmpccmr1 = 0;
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
- assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Set the encoder Mode */
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
- tmpsmcr |= TIM_EncoderMode;
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
- tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
- /* Set the TI1 and the TI2 Polarities */
- tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
- tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Forces the TIMx output 1 waveform to active or inactive level.
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC1REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
- * @retval None
- */
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_23491011_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC1M Bits */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
- /* Configure The Forced output Mode */
- tmpccmr1 |= TIM_ForcedAction;
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Forces the TIMx output 2 waveform to active or inactive level.
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM
- * peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC2REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
- * @retval None
- */
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_2349_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC2M Bits */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
- /* Configure The Forced output Mode */
- tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Forces the TIMx output 3 waveform to active or inactive level.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC3REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
- * @retval None
- */
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC1M Bits */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
- /* Configure The Forced output Mode */
- tmpccmr2 |= TIM_ForcedAction;
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Forces the TIMx output 4 waveform to active or inactive level.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC4REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
- * @retval None
- */
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr2 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC2M Bits */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
- /* Configure The Forced output Mode */
- tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Enables or disables TIMx peripheral Preload register on ARR.
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
- * @param NewState: new state of the TIMx peripheral Preload register
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the ARR Preload Bit */
- TIMx->CR1 |= TIM_CR1_ARPE;
- }
- else
- {
- /* Reset the ARR Preload Bit */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
- }
-}
-
-/**
- * @brief Selects the TIMx peripheral Capture Compare DMA source.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param NewState: new state of the Capture Compare DMA source
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the CCDS Bit */
- TIMx->CR2 |= TIM_CR2_CCDS;
- }
- else
- {
- /* Reset the CCDS Bit */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
- }
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_23491011_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC1PE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= TIM_OCPreload;
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_2349_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC2PE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC3PE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= TIM_OCPreload;
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC4PE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 1 Fast feature.
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_23491011_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC1FE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= TIM_OCFast;
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 2 Fast feature.
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_2349_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC2FE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 3 Fast feature.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC3FE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= TIM_OCFast;
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 4 Fast feature.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC4FE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Clears or safeguards the OCREF1 signal on an external event
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_23491011_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC1CE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= TIM_OCClear;
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Clears or safeguards the OCREF2 signal on an external event
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
-
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_2349_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC2CE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Clears or safeguards the OCREF3 signal on an external event
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC3CE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= TIM_OCClear;
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Clears or safeguards the OCREF4 signal on an external event
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC4CE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx channel 1 polarity.
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC1 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_23491011_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC1P Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
- tmpccer |= TIM_OCPolarity;
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 2 polarity.
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC2 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_2349_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC2P Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
- tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 3 polarity.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC3 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC3P Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
- tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 4 polarity.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC4 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC4P Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
- tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel x.
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parmeter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
- * @retval None
- */
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
-{
- uint16_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_23491011_PERIPH(TIMx));
- assert_param(IS_TIM_CCX(TIM_CCx));
-
- tmp = CCER_CCE_SET << TIM_Channel;
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= (uint16_t)~ tmp;
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
-}
-
-/**
- * @brief Selects the TIM Ouput Compare Mode.
- * @note This function disables the selected channel before changing the Ouput
- * Compare Mode.
- * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parmeter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param TIM_OCMode: specifies the TIM Output Compare Mode.
- * This paramter can be one of the following values:
- * @arg TIM_OCMode_Timing
- * @arg TIM_OCMode_Active
- * @arg TIM_OCMode_Toggle
- * @arg TIM_OCMode_PWM1
- * @arg TIM_OCMode_PWM2
- * @arg TIM_ForcedAction_Active
- * @arg TIM_ForcedAction_InActive
- * @retval None
- */
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
-{
- uint32_t tmp = 0;
- uint16_t tmp1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_23491011_PERIPH(TIMx));
- assert_param(IS_TIM_OCM(TIM_OCMode));
-
- tmp = (uint32_t) TIMx;
- tmp += CCMR_OFFSET;
-
- tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
-
- /* Disable the Channel: Reset the CCxE Bit */
- TIMx->CCER &= (uint16_t) ~tmp1;
-
- if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
- {
- tmp += (TIM_Channel>>1);
-
- /* Reset the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
-
- /* Configure the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp |= TIM_OCMode;
- }
- else
- {
- tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
-
- /* Reset the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
-
- /* Configure the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
- }
-}
-
-/**
- * @brief Enables or Disables the TIMx Update event.
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
- * @param NewState: new state of the TIMx UDIS bit
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the Update Disable Bit */
- TIMx->CR1 |= TIM_CR1_UDIS;
- }
- else
- {
- /* Reset the Update Disable Bit */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
- }
-}
-
-/**
- * @brief Configures the TIMx Update Request Interrupt source.
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
- * @param TIM_UpdateSource: specifies the Update source.
- * This parameter can be one of the following values:
- * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
- or the setting of UG bit, or an update generation
- through the slave mode controller.
- * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
- * @retval None
- */
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
-
- if (TIM_UpdateSource != TIM_UpdateSource_Global)
- {
- /* Set the URS Bit */
- TIMx->CR1 |= TIM_CR1_URS;
- }
- else
- {
- /* Reset the URS Bit */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
- }
-}
-
-/**
- * @brief Enables or disables the TIMxÂ’s Hall sensor interface.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param NewState: new state of the TIMx Hall sensor interface.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the TI1S Bit */
- TIMx->CR2 |= TIM_CR2_TI1S;
- }
- else
- {
- /* Reset the TI1S Bit */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
- }
-}
-
-/**
- * @brief Selects the TIMxÂ’s One Pulse Mode.
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
- * @param TIM_OPMode: specifies the OPM Mode to be used.
- * This parameter can be one of the following values:
- * @arg TIM_OPMode_Single
- * @arg TIM_OPMode_Repetitive
- * @retval None
- */
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
-
- /* Reset the OPM Bit */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
- /* Configure the OPM Mode */
- TIMx->CR1 |= TIM_OPMode;
-}
-
-/**
- * @brief Selects the TIMx Trigger Output Mode.
- * @param TIMx: where x can be 2, 3, 4, 6, 7 or 9 to select the TIM peripheral.
- * @param TIM_TRGOSource: specifies the Trigger Output source.
- * This paramter can be one of the following values:
- *
- * - For all TIMx
- * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
- *
- * - For all TIMx except TIM6 and TIM7
- * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
- * is to be set, as soon as a capture or compare match occurs (TRGO).
- * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
-
- * - For all TIMx except TIM6, TIM7, TIM10 and TIM11
- * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
-
- * - For TIM2, TIM3 and TIM4
- * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
- *
- * @retval None
- */
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_234679_PERIPH(TIMx));
- assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
-
- /* Reset the MMS Bits */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
- /* Select the TRGO source */
- TIMx->CR2 |= TIM_TRGOSource;
-}
-
-/**
- * @brief Selects the TIMx Slave Mode.
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
- * @param TIM_SlaveMode: specifies the Timer Slave Mode.
- * This paramter can be one of the following values:
- * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
- * the counter and triggers an update of the registers.
- * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
- * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
- * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
- * @retval None
- */
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_2349_PERIPH(TIMx));
- assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
-
- /* Reset the SMS Bits */
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
- /* Select the Slave Mode */
- TIMx->SMCR |= TIM_SlaveMode;
-}
-
-/**
- * @brief Sets or Resets the TIMx Master/Slave Mode.
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
- * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
- * This paramter can be one of the following values:
- * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
- * and its slaves (through TRGO).
- * @arg TIM_MasterSlaveMode_Disable: No action
- * @retval None
- */
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_2349_PERIPH(TIMx));
- assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
-
- /* Reset the MSM Bit */
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
-
- /* Set or Reset the MSM Bit */
- TIMx->SMCR |= TIM_MasterSlaveMode;
-}
-
-/**
- * @brief Sets the TIMx Counter Register value
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
- * @param Counter: specifies the Counter register new value.
- * @retval None
- */
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Set the Counter Register value */
- TIMx->CNT = Counter;
-}
-
-/**
- * @brief Sets the TIMx Autoreload Register value
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
- * @param Autoreload: specifies the Autoreload register new value.
- * @retval None
- */
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Set the Autoreload Register value */
- TIMx->ARR = Autoreload;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare1 Register value
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
- * @param Compare1: specifies the Capture Compare1 register new value.
- * @retval None
-
- */
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
-{
- /* Check the parameters */
- assert_param(IS_TIM_23491011_PERIPH(TIMx));
-
- /* Set the Capture Compare1 Register value */
- TIMx->CCR1 = Compare1;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare2 Register value
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
- * @param Compare2: specifies the Capture Compare2 register new value.
- * @retval None
-
- */
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
-{
- /* Check the parameters */
- assert_param(IS_TIM_2349_PERIPH(TIMx));
-
- /* Set the Capture Compare2 Register value */
- TIMx->CCR2 = Compare2;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare3 Register value
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param Compare3: specifies the Capture Compare3 register new value.
- * @retval None
-
- */
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
-{
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
-
- /* Set the Capture Compare3 Register value */
- TIMx->CCR3 = Compare3;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare4 Register value
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param Compare4: specifies the Capture Compare4 register new value.
- * @retval None
-
- */
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
-{
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
-
- /* Set the Capture Compare4 Register value */
- TIMx->CCR4 = Compare4;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 1 prescaler.
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_23491011_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC1PSC Bits */
- TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
- /* Set the IC1PSC value */
- TIMx->CCMR1 |= TIM_ICPSC;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 2 prescaler.
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_2349_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC2PSC Bits */
- TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
- /* Set the IC2PSC value */
- TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
-}
-
-/**
- * @brief Sets the TIMx Input Capture 3 prescaler.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC3PSC Bits */
- TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
- /* Set the IC3PSC value */
- TIMx->CCMR2 |= TIM_ICPSC;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 4 prescaler.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC4PSC Bits */
- TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
- /* Set the IC4PSC value */
- TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
-}
-
-/**
- * @brief Sets the TIMx Clock Division value.
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
- * @param TIM_CKD: specifies the clock division value.
- * This parameter can be one of the following value:
- * @arg TIM_CKD_DIV1: TDTS = Tck_tim
- * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
- * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
- * @retval None
- */
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
-{
- /* Check the parameters */
- assert_param(IS_TIM_23491011_PERIPH(TIMx));
- assert_param(IS_TIM_CKD_DIV(TIM_CKD));
-
- /* Reset the CKD Bits */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
- /* Set the CKD value */
- TIMx->CR1 |= TIM_CKD;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 1 value.
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
- * @retval Capture Compare 1 Register value.
-
- */
-uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_23491011_PERIPH(TIMx));
-
- /* Get the Capture 1 Register value */
- return TIMx->CCR1;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 2 value.
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
- * @retval Capture Compare 2 Register value.
-
- */
-uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_2349_PERIPH(TIMx));
-
- /* Get the Capture 2 Register value */
- return TIMx->CCR2;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 3 value.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @retval Capture Compare 3 Register value.
- */
-uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
-
- /* Get the Capture 3 Register value */
- return TIMx->CCR3;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 4 value.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @retval Capture Compare 4 Register value.
- */
-uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
-
- /* Get the Capture 4 Register value */
- return TIMx->CCR4;
-}
-
-/**
- * @brief Gets the TIMx Counter value.
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
- * @retval Counter Register value.
- */
-uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Get the Counter Register value */
- return TIMx->CNT;
-}
-
-/**
- * @brief Gets the TIMx Prescaler value.
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
- * @retval Prescaler Register value.
- */
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Get the Prescaler Register value */
- return TIMx->PSC;
-}
-
-/**
- * @brief Selects the OCReference Clear source.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param TIM_OCReferenceClear: specifies the OCReference Clear source.
- * This parameter can be one of the following values:
- * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.
- * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input.
- * @retval None
- */
-void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)
-{
- /* Check the parameters */
- assert_param(IS_TIM_234_PERIPH(TIMx));
- assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));
-
- /* Set the TIM_OCReferenceClear source */
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS);
- TIMx->SMCR |= TIM_OCReferenceClear;
-}
-
-/**
- * @brief Configures the TIM9, TIM10 and TIM11 Remapping input Capabilities.
- * @param TIMx: where x can be 9, 10 or 11 to select the TIM peripheral.
- * @param TIM_Remap: specifies the TIM input reampping source.
- * This parameter can be one of the following values:
- * @arg TIM9_GPIO: TIM9 Channel 1 is connected to dedicated Timer pin(default)
- * @arg TIM9_LSE: TIM9 Channel 1 is connected to LSE clock.
- * @arg TIM10_GPIO: TIM10 Channel 1 is connected to dedicated Timer pin(default)
- * @arg TIM10_LSI: TIM10 Channel 1 is connected to LSI clock.
- * @arg TIM10_LSE: TIM10 Channel 1 is connected to LSE clock.
- * @arg TIM10_RTC: TIM10 Channel 1 is connected to RTC Output event.
- * @arg TIM11_GPIO: TIM11 Channel 1 is connected to dedicated Timer pin(default)
- * @arg TIM11_MSI: TIM11 Channel 1 is connected to MSI clock.
- * @arg TIM11_HSE_RTC: TIM11 Channel 1 is connected to HSE_RTC clock.
- * @retval None
- */
-void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
-{
- /* Check the parameters */
- assert_param(IS_TIM_91011_PERIPH(TIMx));
- assert_param(IS_TIM_REMAP(TIM_Remap));
-
- /* Set the Timer remapping configuration */
- TIMx->OR = TIM_Remap;
-}
-
-/**
- * @brief Checks whether the specified TIM flag is set or not.
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
- * @param TIM_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_Update: TIM update Flag
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
- * @note
- * - TIM6 and TIM7 can have only one update flag.
- * - TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger,
- * TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags
- * - TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1 or TIM_FLAG_CC1OF flags
- * @retval The new state of TIM_FLAG (SET or RESET).
- */
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
-
- if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the TIMx's pending flags.
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
- * @param TIM_FLAG: specifies the flag bit to clear.
- * This parameter can be any combination of the following values:
- * @arg TIM_FLAG_Update: TIM update Flag
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
- * @note
- * - TIM6 and TIM7 can have only one update flag.
- * - TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger flags
- * TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags
- * - TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1
- * or TIM_FLAG_CC1OF flags
- * @retval None
- */
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
-
- /* Clear the flags */
- TIMx->SR = (uint16_t)~TIM_FLAG;
-}
-
-/**
- * @brief Checks whether the TIM interrupt has occurred or not.
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
- * @param TIM_IT: specifies the TIM interrupt source to check.
- * This parameter can be one of the following values:
- * @arg TIM_IT_Update: TIM update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @note
- * - TIM6 and TIM7 can generate only an update interrupt.
- * - TIM9 can have only update interrupt, TIM_FLAG_CC1 or TIM_FLAG_CC2,
- * interrupt and TIM_IT_Trigger interrupt.
- * - TIM10 and TIM11 can have only update interrupt or TIM_FLAG_CC1
- * interrupt
- * @retval The new state of the TIM_IT(SET or RESET).
- */
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itstatus = 0x0, itenable = 0x0;
-
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_IT(TIM_IT));
-
- itstatus = TIMx->SR & TIM_IT;
-
- itenable = TIMx->DIER & TIM_IT;
- if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the TIMx's interrupt pending bits.
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
- * @param TIM_IT: specifies the pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg TIM_IT_Update: TIM update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @note
- * - TIM6 and TIM7 can generate only an update interrupt.
- * - TIM9 can have only update interrupt, TIM_IT_CC1 or TIM_IT_CC2,
- * and TIM_IT_Trigger interrupt.
- * - TIM10 and TIM11 can have only update interrupt or TIM_IT_CC1
- * interrupt
- * @retval None
- */
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_IT(TIM_IT));
-
- /* Clear the IT pending Bit */
- TIMx->SR = (uint16_t)~TIM_IT;
-}
-
-/**
- * @brief Configure the TI1 as Input.
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr1 = 0, tmpccer = 0;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
- /* Select the Input and set the filter */
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
- tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI2 as Input.
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
- * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 4);
- /* Select the Input and set the filter */
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
- tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
- tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI3 as Input.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
- * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 3: Reset the CC3E Bit */
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 8);
- /* Select the Input and set the filter */
- tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
- tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
- /* Select the Polarity and set the CC3E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI4 as Input.
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
- * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 12);
- /* Select the Input and set the filter */
- tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
- tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
- tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
-
- /* Select the Polarity and set the CC4E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P | TIM_CCER_CC4NP));
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer ;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c
deleted file mode 100644
index 90c1492..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c
+++ /dev/null
@@ -1,995 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l1xx_usart.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief This file provides all the USART firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_usart.h"
-#include "stm32l1xx_rcc.h"
-
-/** @addtogroup STM32L1xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup USART
- * @brief USART driver modules
- * @{
- */
-
-/** @defgroup USART_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Private_Defines
- * @{
- */
-
-/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */
-#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \
- USART_CR1_PS | USART_CR1_TE | \
- USART_CR1_RE))
-
-/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */
-#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
- USART_CR2_CPHA | USART_CR2_LBCL))
-
-/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */
-#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))
-
-/*!< USART Interrupts mask */
-#define IT_MASK ((uint16_t)0x001F)
-
-/**
- * @}
- */
-
-/** @defgroup USART_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the USARTx peripheral registers to their default reset values.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values: USART1, USART2 or USART3.
- * @retval None
- */
-void USART_DeInit(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- if (USARTx == USART1)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
- }
- else if (USARTx == USART2)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
- }
- else
- {
- if (USARTx == USART3)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the USARTx peripheral according to the specified
- * parameters in the USART_InitStruct .
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure
- * that contains the configuration information for the specified USART peripheral.
- * @retval None
- */
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
-{
- uint32_t tmpreg = 0x00, apbclock = 0x00;
- uint32_t integerdivider = 0x00;
- uint32_t fractionaldivider = 0x00;
- RCC_ClocksTypeDef RCC_ClocksStatus;
-
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
- assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
- assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
- assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
- assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
- assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
-
-/*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
- /* Clear STOP[13:12] bits */
- tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
-
- /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
- /* Set STOP[13:12] bits according to USART_StopBits value */
- tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
-
- /* Write to USART CR2 */
- USARTx->CR2 = (uint16_t)tmpreg;
-
-/*---------------------------- USART CR1 Configuration -----------------------*/
- tmpreg = USARTx->CR1;
- /* Clear M, PCE, PS, TE and RE bits */
- tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);
-
- /* Configure the USART Word Length, Parity and mode ----------------------- */
- /* Set the M bits according to USART_WordLength value */
- /* Set PCE and PS bits according to USART_Parity value */
- /* Set TE and RE bits according to USART_Mode value */
- tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
- USART_InitStruct->USART_Mode;
-
- /* Write to USART CR1 */
- USARTx->CR1 = (uint16_t)tmpreg;
-
-/*---------------------------- USART CR3 Configuration -----------------------*/
- tmpreg = USARTx->CR3;
- /* Clear CTSE and RTSE bits */
- tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);
-
- /* Configure the USART HFC -------------------------------------------------*/
- /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
- tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
-
- /* Write to USART CR3 */
- USARTx->CR3 = (uint16_t)tmpreg;
-
-/*---------------------------- USART BRR Configuration -----------------------*/
- /* Configure the USART Baud Rate -------------------------------------------*/
- RCC_GetClocksFreq(&RCC_ClocksStatus);
- if (USARTx == USART1)
- {
- apbclock = RCC_ClocksStatus.PCLK2_Frequency;
- }
- else
- {
- apbclock = RCC_ClocksStatus.PCLK1_Frequency;
- }
-
- /* Determine the integer part */
- if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
- {
- /* Integer part computing in case Oversampling mode is 8 Samples */
- integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
- }
- else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
- {
- /* Integer part computing in case Oversampling mode is 16 Samples */
- integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
- }
- tmpreg = (integerdivider / 100) << 4;
-
- /* Determine the fractional part */
- fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
-
- /* Implement the fractional part in the register */
- if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
- {
- tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
- }
- else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
- {
- tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
- }
-
- /* Write to USART BRR */
- USARTx->BRR = (uint16_t)tmpreg;
-}
-
-/**
- * @brief Fills each USART_InitStruct member with its default value.
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
-{
- /* USART_InitStruct members default value */
- USART_InitStruct->USART_BaudRate = 9600;
- USART_InitStruct->USART_WordLength = USART_WordLength_8b;
- USART_InitStruct->USART_StopBits = USART_StopBits_1;
- USART_InitStruct->USART_Parity = USART_Parity_No ;
- USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
- USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-}
-
-/**
- * @brief Initializes the USARTx peripheral Clock according to the
- * specified parameters in the USART_ClockInitStruct .
- * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral.
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
- * structure that contains the configuration information for the specified
- * USART peripheral.
- * @retval None
- */
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- uint32_t tmpreg = 0x00;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
- assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
- assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
- assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
-
-/*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
- /* Clear CLKEN, CPOL, CPHA and LBCL bits */
- tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);
- /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
- /* Set CLKEN bit according to USART_Clock value */
- /* Set CPOL bit according to USART_CPOL value */
- /* Set CPHA bit according to USART_CPHA value */
- /* Set LBCL bit according to USART_LastBit value */
- tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
- USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
- /* Write to USART CR2 */
- USARTx->CR2 = (uint16_t)tmpreg;
-}
-
-/**
- * @brief Fills each USART_ClockInitStruct member with its default value.
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- /* USART_ClockInitStruct members default value */
- USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
- USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
- USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
- USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
-}
-
-/**
- * @brief Enables or disables the specified USART peripheral.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @param NewState: new state of the USARTx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected USART by setting the UE bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_UE;
- }
- else
- {
- /* Disable the selected USART by clearing the UE bit in the CR1 register */
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE);
- }
-}
-
-/**
- * @brief Enables or disables the specified USART interrupts.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TXE: Tansmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @param NewState: new state of the specified USARTx interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
-{
- uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
- uint32_t usartxbase = 0x00;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CONFIG_IT(USART_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- usartxbase = (uint32_t)USARTx;
-
- /* Get the USART register index */
- usartreg = (((uint8_t)USART_IT) >> 0x05);
-
- /* Get the interrupt position */
- itpos = USART_IT & IT_MASK;
- itmask = (((uint32_t)0x01) << itpos);
-
- if (usartreg == 0x01) /* The IT is in CR1 register */
- {
- usartxbase += 0x0C;
- }
- else if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- usartxbase += 0x10;
- }
- else /* The IT is in CR3 register */
- {
- usartxbase += 0x14;
- }
- if (NewState != DISABLE)
- {
- *(__IO uint32_t*)usartxbase |= itmask;
- }
- else
- {
- *(__IO uint32_t*)usartxbase &= ~itmask;
- }
-}
-
-/**
- * @brief Enables or disables the USARTÂ’s DMA interface.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @param USART_DMAReq: specifies the DMA request.
- * This parameter can be any combination of the following values:
- * @arg USART_DMAReq_Tx: USART DMA transmit request
- * @arg USART_DMAReq_Rx: USART DMA receive request
- * @param NewState: new state of the DMA Request sources.
- * This parameter can be: ENABLE or DISABLE.
- * @note The DMA mode is not available for UART5.
- * @retval None
- */
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DMAREQ(USART_DMAReq));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DMA transfer for selected requests by setting the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 |= USART_DMAReq;
- }
- else
- {
- /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 &= (uint16_t)~USART_DMAReq;
- }
-}
-
-/**
- * @brief Sets the address of the USART node.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @param USART_Address: Indicates the address of the USART node.
- * @retval None
- */
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_ADDRESS(USART_Address));
-
- /* Clear the USART address */
- USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD);
- /* Set the USART address node */
- USARTx->CR2 |= USART_Address;
-}
-
-/**
- * @brief Selects the USART WakeUp method.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @param USART_WakeUp: specifies the USART wakeup method.
- * This parameter can be one of the following values:
- * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
- * @arg USART_WakeUp_AddressMark: WakeUp by an address mark
- * @retval None
- */
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_WAKEUP(USART_WakeUp));
-
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE);
- USARTx->CR1 |= USART_WakeUp;
-}
-
-/**
- * @brief Determines if the USART is in mute mode or not.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @param NewState: new state of the USART mute mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the USART mute mode by setting the RWU bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_RWU;
- }
- else
- {
- /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU);
- }
-}
-
-/**
- * @brief Sets the USART LIN Break detection length.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @param USART_LINBreakDetectLength: specifies the LIN break detection length.
- * This parameter can be one of the following values:
- * @arg USART_LINBreakDetectLength_10b: 10-bit break detection
- * @arg USART_LINBreakDetectLength_11b: 11-bit break detection
- * @retval None
- */
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
-
- USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL);
- USARTx->CR2 |= USART_LINBreakDetectLength;
-}
-
-/**
- * @brief Enables or disables the USARTÂ’s LIN mode.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @param NewState: new state of the USART LIN mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
- USARTx->CR2 |= USART_CR2_LINEN;
- }
- else
- {
- /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
- USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN);
- }
-}
-
-/**
- * @brief Transmits single data through the USARTx peripheral.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @param Data: the data to transmit.
- * @retval None
- */
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DATA(Data));
-
- /* Transmit Data */
- USARTx->DR = (Data & (uint16_t)0x01FF);
-}
-
-/**
- * @brief Returns the most recent received data by the USARTx peripheral.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @retval The received data.
- */
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Receive Data */
- return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
-}
-
-/**
- * @brief Transmits break characters.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @retval None
- */
-void USART_SendBreak(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Send break characters */
- USARTx->CR1 |= USART_CR1_SBK;
-}
-
-/**
- * @brief Sets the specified USART guard time.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @param USART_GuardTime: specifies the guard time.
- * @note The guard time bits are not available for UART4 and UART5.
- * @retval None
- */
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Clear the USART Guard time */
- USARTx->GTPR &= USART_GTPR_PSC;
- /* Set the USART guard time */
- USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
-}
-
-/**
- * @brief Sets the system clock prescaler.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @param USART_Prescaler: specifies the prescaler clock.
- * @note The function is used for IrDA mode with UART4 and UART5.
- * @retval None
- */
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Clear the USART prescaler */
- USARTx->GTPR &= USART_GTPR_GT;
- /* Set the USART prescaler */
- USARTx->GTPR |= USART_Prescaler;
-}
-
-/**
- * @brief Enables or disables the USARTÂ’s Smart Card mode.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @param NewState: new state of the Smart Card mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note The Smart Card mode is not available for UART4 and UART5.
- * @retval None
- */
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the SC mode by setting the SCEN bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_SCEN;
- }
- else
- {
- /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN);
- }
-}
-
-/**
- * @brief Enables or disables NACK transmission.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @param NewState: new state of the NACK transmission.
- * This parameter can be: ENABLE or DISABLE.
- * @note The Smart Card mode is not available for UART4 and UART5.
- * @retval None
- */
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_NACK;
- }
- else
- {
- /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK);
- }
-}
-
-/**
- * @brief Enables or disables the USARTÂ’s Half Duplex communication.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @param NewState: new state of the USART Communication.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_HDSEL;
- }
- else
- {
- /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL);
- }
-}
-
-/**
- * @brief Enables or disables the USART's 8x oversampling mode.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3.
- * @param NewState: new state of the USART 8x oversampling mode.
- * This parameter can be: ENABLE or DISABLE.
- *
- * @note
- * This function has to be called before calling USART_Init()
- * function in order to have correct baudrate Divider value.
- * @retval : None
- */
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_OVER8;
- }
- else
- {
- /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8);
- }
-}
-
-/**
- * @brief Enables or disables the USART's one bit sampling methode.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3.
- * @param NewState: new state of the USART one bit sampling methode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval : None
- */
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_ONEBIT;
- }
- else
- {
- /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT);
- }
-}
-
-/**
- * @brief Configures the USARTÂ’s IrDA interface.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @param USART_IrDAMode: specifies the IrDA mode.
- * This parameter can be one of the following values:
- * @arg USART_IrDAMode_LowPower
- * @arg USART_IrDAMode_Normal
- * @retval None
- */
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
-
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP);
- USARTx->CR3 |= USART_IrDAMode;
-}
-
-/**
- * @brief Enables or disables the USARTÂ’s IrDA interface.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @param NewState: new state of the IrDA mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_IREN;
- }
- else
- {
- /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN);
- }
-}
-
-/**
- * @brief Checks whether the specified USART flag is set or not.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @param USART_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg USART_FLAG_CTS: CTS Change flag
- * @arg USART_FLAG_LBD: LIN Break detection flag
- * @arg USART_FLAG_TXE: Transmit data register empty flag
- * @arg USART_FLAG_TC: Transmission Complete flag
- * @arg USART_FLAG_RXNE: Receive data register not empty flag
- * @arg USART_FLAG_IDLE: Idle Line detection flag
- * @arg USART_FLAG_ORE: OverRun Error flag
- * @arg USART_FLAG_NE: Noise Error flag
- * @arg USART_FLAG_FE: Framing Error flag
- * @arg USART_FLAG_PE: Parity Error flag
- * @retval The new state of USART_FLAG (SET or RESET).
- */
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_FLAG(USART_FLAG));
-
- if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the USARTx's pending flags.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @param USART_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg USART_FLAG_CTS: CTS Change flag.
- * @arg USART_FLAG_LBD: LIN Break detection flag.
- * @arg USART_FLAG_TC: Transmission Complete flag.
- * @arg USART_FLAG_RXNE: Receive data register not empty flag.
- *
- * @note
- * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
- * error) and IDLE (Idle line detected) flags are cleared by software
- * sequence: a read operation to USART_SR register (USART_GetFlagStatus())
- * followed by a read operation to USART_DR register (USART_ReceiveData()).
- * - RXNE flag can be also cleared by a read to the USART_DR register
- * (USART_ReceiveData()).
- * - TC flag can be also cleared by software sequence: a read operation to
- * USART_SR register (USART_GetFlagStatus()) followed by a write operation
- * to USART_DR register (USART_SendData()).
- * - TXE flag is cleared only by a write to the USART_DR register
- * (USART_SendData()).
- * @retval None
- */
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
-
- USARTx->SR = (uint16_t)~USART_FLAG;
-}
-
-/**
- * @brief Checks whether the specified USART interrupt has occurred or not.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @param USART_IT: specifies the USART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg USART_IT_CTS: CTS change interrupt
- * @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TXE: Tansmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_ORE: OverRun Error interrupt
- * @arg USART_IT_NE: Noise Error interrupt
- * @arg USART_IT_FE: Framing Error interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @retval The new state of USART_IT (SET or RESET).
- */
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
-{
- uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_GET_IT(USART_IT));
-
- /* Get the USART register index */
- usartreg = (((uint8_t)USART_IT) >> 0x05);
- /* Get the interrupt position */
- itmask = USART_IT & IT_MASK;
- itmask = (uint32_t)0x01 << itmask;
-
- if (usartreg == 0x01) /* The IT is in CR1 register */
- {
- itmask &= USARTx->CR1;
- }
- else if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- itmask &= USARTx->CR2;
- }
- else /* The IT is in CR3 register */
- {
- itmask &= USARTx->CR3;
- }
-
- bitpos = USART_IT >> 0x08;
- bitpos = (uint32_t)0x01 << bitpos;
- bitpos &= USARTx->SR;
- if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- return bitstatus;
-}
-
-/**
- * @brief Clears the USARTxÂ’s interrupt pending bits.
- * @param USARTx: Select the USART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2 or USART3.
- * @param USART_IT: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg USART_IT_CTS: CTS change interrupt
- * @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TC: Transmission complete interrupt.
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt.
- *
- * @note
- * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
- * error) and IDLE (Idle line detected) pending bits are cleared by
- * software sequence: a read operation to USART_SR register
- * (USART_GetITStatus()) followed by a read operation to USART_DR register
- * (USART_ReceiveData()).
- * - RXNE pending bit can be also cleared by a read to the USART_DR register
- * (USART_ReceiveData()).
- * - TC pending bit can be also cleared by software sequence: a read
- * operation to USART_SR register (USART_GetITStatus()) followed by a write
- * operation to USART_DR register (USART_SendData()).
- * - TXE pending bit is cleared only by a write to the USART_DR register
- * (USART_SendData()).
- * @retval None
- */
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
-{
- uint16_t bitpos = 0x00, itmask = 0x00;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_IT(USART_IT));
-
- bitpos = USART_IT >> 0x08;
- itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
- USARTx->SR = (uint16_t)~itmask;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/startup_stm32l1xx_md.s b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/startup_stm32l1xx_md.s
deleted file mode 100644
index 8ede05b..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/startup_stm32l1xx_md.s
+++ /dev/null
@@ -1,459 +0,0 @@
-;/******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
-;* File Name : startup_stm32l15x_lp.s
-;* Author : MCD Application Team
-;* Version : V1.0.0RC1
-;* Date : 07/02/2010
-;* Description : STM32L15x Low Power Devices vector table for EWARM5.x toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == __iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address.
-;* After Reset the Cortex-M3 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************/
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- EXTERN vPortSVCHandler
- EXTERN xPortPendSVHandler
- EXTERN xPortSysTickHandler
-
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD vPortSVCHandler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD xPortPendSVHandler ; PendSV Handler
- DCD xPortSysTickHandler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_IRQHandler ; ADC1
- DCD USB_HP_IRQHandler ; USB High Priority
- DCD USB_LP_IRQHandler ; USB Low Priority
- DCD DAC_IRQHandler ; DAC
- DCD COMP_IRQHandler ; COMP through EXTI Line
- DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
- DCD LCD_IRQHandler ; LCD
- DCD TIM9_IRQHandler ; TIM9
- DCD TIM10_IRQHandler ; TIM10
- DCD TIM11_IRQHandler ; TIM11
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
- DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
- DCD TIM6_IRQHandler ; TIM6
- DCD TIM7_IRQHandler ; TIM7
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER(1)
-NMI_Handler
- B NMI_Handler
-
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER(1)
-HardFault_Handler
- B HardFault_Handler
-
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER(1)
-MemManage_Handler
- B MemManage_Handler
-
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER(1)
-BusFault_Handler
- B BusFault_Handler
-
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER(1)
-UsageFault_Handler
- B UsageFault_Handler
-
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER(1)
-SVC_Handler
- B SVC_Handler
-
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER(1)
-DebugMon_Handler
- B DebugMon_Handler
-
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER(1)
-PendSV_Handler
- B PendSV_Handler
-
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER(1)
-SysTick_Handler
- B SysTick_Handler
-
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:REORDER(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:REORDER(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
-
- PUBWEAK TAMPER_STAMP_IRQHandler
- SECTION .text:CODE:REORDER(1)
-TAMPER_STAMP_IRQHandler
- B TAMPER_STAMP_IRQHandler
-
-
- PUBWEAK RTC_WKUP_IRQHandler
- SECTION .text:CODE:REORDER(1)
-RTC_WKUP_IRQHandler
- B RTC_WKUP_IRQHandler
-
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:REORDER(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:REORDER(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:REORDER(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:REORDER(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:REORDER(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:REORDER(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:REORDER(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
-
- PUBWEAK DMA1_Channel2_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMA1_Channel2_IRQHandler
- B DMA1_Channel2_IRQHandler
-
-
- PUBWEAK DMA1_Channel3_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMA1_Channel3_IRQHandler
- B DMA1_Channel3_IRQHandler
-
-
- PUBWEAK DMA1_Channel4_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMA1_Channel4_IRQHandler
- B DMA1_Channel4_IRQHandler
-
-
- PUBWEAK DMA1_Channel5_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMA1_Channel5_IRQHandler
- B DMA1_Channel5_IRQHandler
-
-
- PUBWEAK DMA1_Channel6_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMA1_Channel6_IRQHandler
- B DMA1_Channel6_IRQHandler
-
-
- PUBWEAK DMA1_Channel7_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMA1_Channel7_IRQHandler
- B DMA1_Channel7_IRQHandler
-
-
- PUBWEAK ADC1_IRQHandler
- SECTION .text:CODE:REORDER(1)
-ADC1_IRQHandler
- B ADC1_IRQHandler
-
-
- PUBWEAK USB_HP_IRQHandler
- SECTION .text:CODE:REORDER(1)
-USB_HP_IRQHandler
- B USB_HP_IRQHandler
-
-
- PUBWEAK USB_LP_IRQHandler
- SECTION .text:CODE:REORDER(1)
-USB_LP_IRQHandler
- B USB_LP_IRQHandler
-
-
- PUBWEAK DAC_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DAC_IRQHandler
- B DAC_IRQHandler
-
-
- PUBWEAK COMP_IRQHandler
- SECTION .text:CODE:REORDER(1)
-COMP_IRQHandler
- B COMP_IRQHandler
-
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:REORDER(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
-
- PUBWEAK LCD_IRQHandler
- SECTION .text:CODE:REORDER(1)
-LCD_IRQHandler
- B LCD_IRQHandler
-
-
- PUBWEAK TIM9_IRQHandler
- SECTION .text:CODE:REORDER(1)
-TIM9_IRQHandler
- B TIM9_IRQHandler
-
-
- PUBWEAK TIM10_IRQHandler
- SECTION .text:CODE:REORDER(1)
-TIM10_IRQHandler
- B TIM10_IRQHandler
-
-
- PUBWEAK TIM11_IRQHandler
- SECTION .text:CODE:REORDER(1)
-TIM11_IRQHandler
- B TIM11_IRQHandler
-
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:REORDER(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
-
- PUBWEAK TIM3_IRQHandler
- SECTION .text:CODE:REORDER(1)
-TIM3_IRQHandler
- B TIM3_IRQHandler
-
-
- PUBWEAK TIM4_IRQHandler
- SECTION .text:CODE:REORDER(1)
-TIM4_IRQHandler
- B TIM4_IRQHandler
-
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:REORDER(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:REORDER(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:REORDER(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:REORDER(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:REORDER(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
-
- PUBWEAK SPI2_IRQHandler
- SECTION .text:CODE:REORDER(1)
-SPI2_IRQHandler
- B SPI2_IRQHandler
-
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:REORDER(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:REORDER(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:REORDER(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:REORDER(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
-
- PUBWEAK RTC_Alarm_IRQHandler
- SECTION .text:CODE:REORDER(1)
-RTC_Alarm_IRQHandler
- B RTC_Alarm_IRQHandler
-
-
- PUBWEAK USB_FS_WKUP_IRQHandler
- SECTION .text:CODE:REORDER(1)
-USB_FS_WKUP_IRQHandler
- B USB_FS_WKUP_IRQHandler
-
-
- PUBWEAK TIM6_IRQHandler
- SECTION .text:CODE:REORDER(1)
-TIM6_IRQHandler
- B TIM6_IRQHandler
-
-
- PUBWEAK TIM7_IRQHandler
- SECTION .text:CODE:REORDER(1)
-TIM7_IRQHandler
- B TIM7_IRQHandler
-
- END
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/stm32_eval.h b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/stm32_eval.h
deleted file mode 100644
index 7d1cabd..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/stm32_eval.h
+++ /dev/null
@@ -1,360 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32_eval.h
- * @author MCD Application Team
- * @version V4.4.0RC1
- * @date 07/02/2010
- * @brief Header file for stm32_eval.c module.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_EVAL_H
-#define __STM32_EVAL_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-
-/** @addtogroup Utilities
- * @{
- */
-
-/** @addtogroup STM32_EVAL
- * @{
- */
-
-/** @defgroup STM32_EVAL_Abstraction_Layer
- * @{
- */
-
-/** @defgroup STM32_EVAL_HARDWARE_RESOURCES
- * @{
- */
-
-/**
-@code
- The table below gives an overview of the hardware resources supported by each
- STM32 EVAL board.
- - LCD: TFT Color LCD (Parallel (FSMC) and Serial (SPI))
- - IOE: IO Expander on I2C
- - sFLASH: serial SPI FLASH (M25Pxxx)
- - sEE: serial I2C EEPROM (M24C08, M24C32, M24C64)
- - TSENSOR: Temperature Sensor (LM75)
- - SD: SD Card memory (SPI and SDIO (SD Card MODE))
- =================================================================================================================+
- STM32 EVAL | LED | Buttons | Com Ports | LCD | IOE | sFLASH | sEE | TSENSOR | SD (SPI) | SD(SDIO) |
- =================================================================================================================+
- STM3210B-EVAL | 4 | 8 | 2 | YES (SPI) | NO | YES | NO | YES | YES | NO |
- -----------------------------------------------------------------------------------------------------------------+
- STM3210E-EVAL | 4 | 8 | 2 | YES (FSMC)| NO | YES | NO | YES | NO | YES |
- -----------------------------------------------------------------------------------------------------------------+
- STM3210C-EVAL | 4 | 3 | 1 | YES (SPI) | YES | NO | YES | NO | YES | NO |
- -----------------------------------------------------------------------------------------------------------------+
- STM32100B-EVAL | 4 | 8 | 2 | YES (SPI) | NO | YES | NO | YES | YES | NO |
- -----------------------------------------------------------------------------------------------------------------+
- STM32L152-EVAL | 4 | 8 | 2 | YES (SPI) | NO | NO | NO | YES | YES | NO |
- =================================================================================================================+
-@endcode
-*/
-
-/**
- * @}
- */
-
-/** @defgroup STM32_EVAL_Exported_Types
- * @{
- */
-typedef enum
-{
- LED1 = 0,
- LED2 = 1,
- LED3 = 2,
- LED4 = 3
-} Led_TypeDef;
-
-typedef enum
-{
- BUTTON_WAKEUP = 0,
- BUTTON_TAMPER = 1,
- BUTTON_KEY = 2,
- BUTTON_RIGHT = 3,
- BUTTON_LEFT = 4,
- BUTTON_UP = 5,
- BUTTON_DOWN = 6,
- BUTTON_SEL = 7
-} Button_TypeDef;
-
-typedef enum
-{
- BUTTON_MODE_GPIO = 0,
- BUTTON_MODE_EXTI = 1
-} ButtonMode_TypeDef;
-
-typedef enum
-{
- JOY_NONE = 0,
- JOY_SEL = 1,
- JOY_DOWN = 2,
- JOY_LEFT = 3,
- JOY_RIGHT = 4,
- JOY_UP = 5
-} JOYState_TypeDef
-;
-
-typedef enum
-{
- COM1 = 0,
- COM2 = 1
-} COM_TypeDef;
-/**
- * @}
- */
-
-/** @defgroup STM32_EVAL_Exported_Constants
- * @{
- */
-
-/**
- * @brief Uncomment the line corresponding to the STMicroelectronics evaluation
- * board used in your application.
- *
- * Tip: To avoid modifying this file each time you need to switch between these
- * boards, you can define the board in your toolchain compiler preprocessor.
- */
-#if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) && !defined (USE_STM3210E_EVAL)\
- && !defined (USE_STM3210C_EVAL) && !defined (USE_STM32L152_EVAL)
- //#define USE_STM32100B_EVAL
- //#define USE_STM3210B_EVAL
- //#define USE_STM3210E_EVAL
- //#define USE_STM3210C_EVAL
- //#define USE_STM32L152_EVAL
-#endif
-
-#ifdef USE_STM32100B_EVAL
- #include "stm32f10x.h"
- #include "stm32100b_eval/stm32100b_eval.h"
-#elif defined USE_STM3210B_EVAL
- #include "stm32f10x.h"
- #include "stm3210b_eval/stm3210b_eval.h"
-#elif defined USE_STM3210E_EVAL
- #include "stm32f10x.h"
- #include "stm3210e_eval/stm3210e_eval.h"
-#elif defined USE_STM3210C_EVAL
- #include "stm32f10x.h"
- #include "stm3210c_eval/stm3210c_eval.h"
-#elif defined USE_STM32L152_EVAL
- #include "stm32l1xx.h"
- #include "stm32l152_eval/stm32l152_eval.h"
-#else
- #error "Please select first the STM32 EVAL board to be used (in stm32_eval.h)"
-#endif
-
-
-/**
- * @brief STM32 Button Defines Legacy
- */
-#define Button_WAKEUP BUTTON_WAKEUP
-#define Button_TAMPER BUTTON_TAMPER
-#define Button_KEY BUTTON_KEY
-#define Button_RIGHT BUTTON_RIGHT
-#define Button_LEFT BUTTON_LEFT
-#define Button_UP BUTTON_UP
-#define Button_DOWN BUTTON_DOWN
-#define Button_SEL BUTTON_SEL
-#define Mode_GPIO BUTTON_MODE_GPIO
-#define Mode_EXTI BUTTON_MODE_EXTI
-#define Button_Mode_TypeDef ButtonMode_TypeDef
-#define JOY_CENTER JOY_SEL
-#define JOY_State_TypeDef JOYState_TypeDef
-
-/**
- * @brief LCD Defines Legacy
- */
-#define LCD_RSNWR_GPIO_CLK LCD_NWR_GPIO_CLK
-#define LCD_SPI_GPIO_PORT LCD_SPI_SCK_GPIO_PORT
-#define LCD_SPI_GPIO_CLK LCD_SPI_SCK_GPIO_CLK
-#define R0 LCD_REG_0
-#define R1 LCD_REG_1
-#define R2 LCD_REG_2
-#define R3 LCD_REG_3
-#define R4 LCD_REG_4
-#define R5 LCD_REG_5
-#define R6 LCD_REG_6
-#define R7 LCD_REG_7
-#define R8 LCD_REG_8
-#define R9 LCD_REG_9
-#define R10 LCD_REG_10
-#define R12 LCD_REG_12
-#define R13 LCD_REG_13
-#define R14 LCD_REG_14
-#define R15 LCD_REG_15
-#define R16 LCD_REG_16
-#define R17 LCD_REG_17
-#define R18 LCD_REG_18
-#define R19 LCD_REG_19
-#define R20 LCD_REG_20
-#define R21 LCD_REG_21
-#define R22 LCD_REG_22
-#define R23 LCD_REG_23
-#define R24 LCD_REG_24
-#define R25 LCD_REG_25
-#define R26 LCD_REG_26
-#define R27 LCD_REG_27
-#define R28 LCD_REG_28
-#define R29 LCD_REG_29
-#define R30 LCD_REG_30
-#define R31 LCD_REG_31
-#define R32 LCD_REG_32
-#define R33 LCD_REG_33
-#define R34 LCD_REG_34
-#define R36 LCD_REG_36
-#define R37 LCD_REG_37
-#define R40 LCD_REG_40
-#define R41 LCD_REG_41
-#define R43 LCD_REG_43
-#define R45 LCD_REG_45
-#define R48 LCD_REG_48
-#define R49 LCD_REG_49
-#define R50 LCD_REG_50
-#define R51 LCD_REG_51
-#define R52 LCD_REG_52
-#define R53 LCD_REG_53
-#define R54 LCD_REG_54
-#define R55 LCD_REG_55
-#define R56 LCD_REG_56
-#define R57 LCD_REG_57
-#define R59 LCD_REG_59
-#define R60 LCD_REG_60
-#define R61 LCD_REG_61
-#define R62 LCD_REG_62
-#define R63 LCD_REG_63
-#define R64 LCD_REG_64
-#define R65 LCD_REG_65
-#define R66 LCD_REG_66
-#define R67 LCD_REG_67
-#define R68 LCD_REG_68
-#define R69 LCD_REG_69
-#define R70 LCD_REG_70
-#define R71 LCD_REG_71
-#define R72 LCD_REG_72
-#define R73 LCD_REG_73
-#define R74 LCD_REG_74
-#define R75 LCD_REG_75
-#define R76 LCD_REG_76
-#define R77 LCD_REG_77
-#define R78 LCD_REG_78
-#define R79 LCD_REG_79
-#define R80 LCD_REG_80
-#define R81 LCD_REG_81
-#define R82 LCD_REG_82
-#define R83 LCD_REG_83
-#define R96 LCD_REG_96
-#define R97 LCD_REG_97
-#define R106 LCD_REG_106
-#define R118 LCD_REG_118
-#define R128 LCD_REG_128
-#define R129 LCD_REG_129
-#define R130 LCD_REG_130
-#define R131 LCD_REG_131
-#define R132 LCD_REG_132
-#define R133 LCD_REG_133
-#define R134 LCD_REG_134
-#define R135 LCD_REG_135
-#define R136 LCD_REG_136
-#define R137 LCD_REG_137
-#define R139 LCD_REG_139
-#define R140 LCD_REG_140
-#define R141 LCD_REG_141
-#define R143 LCD_REG_143
-#define R144 LCD_REG_144
-#define R145 LCD_REG_145
-#define R146 LCD_REG_146
-#define R147 LCD_REG_147
-#define R148 LCD_REG_148
-#define R149 LCD_REG_149
-#define R150 LCD_REG_150
-#define R151 LCD_REG_151
-#define R152 LCD_REG_152
-#define R153 LCD_REG_153
-#define R154 LCD_REG_154
-#define R157 LCD_REG_157
-#define R192 LCD_REG_192
-#define R193 LCD_REG_193
-#define R227 LCD_REG_227
-#define R229 LCD_REG_229
-#define R231 LCD_REG_231
-#define R239 LCD_REG_239
-#define White LCD_COLOR_WHITE
-#define Black LCD_COLOR_BLACK
-#define Grey LCD_COLOR_GREY
-#define Blue LCD_COLOR_BLUE
-#define Blue2 LCD_COLOR_BLUE2
-#define Red LCD_COLOR_RED
-#define Magenta LCD_COLOR_MAGENTA
-#define Green LCD_COLOR_GREEN
-#define Cyan LCD_COLOR_CYAN
-#define Yellow LCD_COLOR_YELLOW
-#define Line0 LCD_LINE_0
-#define Line1 LCD_LINE_1
-#define Line2 LCD_LINE_2
-#define Line3 LCD_LINE_3
-#define Line4 LCD_LINE_4
-#define Line5 LCD_LINE_5
-#define Line6 LCD_LINE_6
-#define Line7 LCD_LINE_7
-#define Line8 LCD_LINE_8
-#define Line9 LCD_LINE_9
-#define Horizontal LCD_DIR_HORIZONTAL
-#define Vertical LCD_DIR_VERTICAL
-
-/**
- * @}
- */
-
-/** @defgroup STM32_EVAL_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup STM32_EVAL_Exported_Functions
- * @{
- */
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32_EVAL_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_conf.h b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_conf.h
deleted file mode 100644
index cd79da0..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_conf.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/**
- ******************************************************************************
- * @file Project/STM32L1xx_StdPeriph_Template/stm32l1xx_conf.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief Library configuration file.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_CONF_H
-#define __STM32L1xx_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment the line below to enable peripheral header file inclusion */
-/* #include "stm32l1xx_adc.h" */
-/* #include "stm32l1xx_crc.h" */
-/* #include "stm32l1xx_comp.h" */
-/* #include "stm32l1xx_dac.h" */
-/* #include "stm32l1xx_dbgmcu.h" */
-/* #include "stm32l1xx_dma.h" */
-#include "stm32l1xx_exti.h"
-/* #include "stm32l1xx_flash.h" */
-#include "stm32l1xx_gpio.h"
-#include "stm32l1xx_syscfg.h"
-/* #include "stm32l1xx_i2c.h" */
-/* #include "stm32l1xx_iwdg.h" */
-/* #include "stm32l1xx_lcd.h" */
-#include "stm32l1xx_pwr.h"
-#include "stm32l1xx_rcc.h"
-/* #include "stm32l1xx_rtc.h" */
-#include "stm32l1xx_spi.h"
-#include "stm32l1xx_tim.h"
-#include "stm32l1xx_usart.h"
-/* #include "stm32l1xx_wwdg.h" */
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the
- Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT 1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr: If expr is false, it calls assert_failed function which reports
- * the name of the source file and the source line number of the call
- * that failed. If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
-#else
- #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32L1xx_CONF_H */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_flash.icf b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_flash.icf
deleted file mode 100644
index be00d54..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x300;
-define symbol __ICFEDIT_size_heap__ = 0x0;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.c b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.c
deleted file mode 100644
index 5afcd2a..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/**
- ******************************************************************************
- * @file Project/STM32L1xx_StdPeriph_Template/stm32l1xx_it.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief Main Interrupt Service Routines.
- * This file provides template for all exceptions handler and
- * peripherals interrupt service routine.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_it.h"
-
-
-/** @addtogroup Template_Project
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/* Cortex-M3 Processor Exceptions Handlers */
-/******************************************************************************/
-
-/**
- * @brief This function handles NMI exception.
- * @param None
- * @retval None
- */
-void NMI_Handler(void)
-{
-}
-
-/**
- * @brief This function handles Hard Fault exception.
- * @param None
- * @retval None
- */
-void HardFault_Handler(void)
-{
- /* Go to infinite loop when Hard Fault exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles Memory Manage exception.
- * @param None
- * @retval None
- */
-void MemManage_Handler(void)
-{
- /* Go to infinite loop when Memory Manage exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles Bus Fault exception.
- * @param None
- * @retval None
- */
-void BusFault_Handler(void)
-{
- /* Go to infinite loop when Bus Fault exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles Usage Fault exception.
- * @param None
- * @retval None
- */
-void UsageFault_Handler(void)
-{
- /* Go to infinite loop when Usage Fault exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles SVCall exception.
- * @param None
- * @retval None
- */
-void SVC_Handler(void)
-{
-}
-
-/**
- * @brief This function handles Debug Monitor exception.
- * @param None
- * @retval None
- */
-void DebugMon_Handler(void)
-{
-}
-
-/**
- * @brief This function handles PendSVC exception.
- * @param None
- * @retval None
- */
-void PendSV_Handler(void)
-{
-}
-
-/**
- * @brief This function handles SysTick Handler.
- * @param None
- * @retval None
- */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/* STM32L1xx Peripherals Interrupt Handlers */
-/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
-/* available peripheral interrupt handler's name please refer to the startup */
-/* file (startup_stm32l1xx_md.s). */
-/******************************************************************************/
-
-/**
- * @brief This function handles PPP interrupt request.
- * @param None
- * @retval None
- */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
- * @}
- */
-
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.h b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.h
deleted file mode 100644
index 7eabc16..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/**
- ******************************************************************************
- * @file Project/STM32L1xx_StdPeriph_Template/stm32l1xx_it.h
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief This file contains the headers of the interrupt handlers.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_IT_H
-#define __STM32L1xx_IT_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_IT_H */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/system_stm32l1xx.c b/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/system_stm32l1xx.c
deleted file mode 100644
index e3881c1..0000000
--- a/Demo/_Cortex_STM32L152_IAR/system_and_ST_code/system_stm32l1xx.c
+++ /dev/null
@@ -1,934 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32l1xx.c
- * @author MCD Application Team
- * @version V1.0.0RC1
- * @date 07/02/2010
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
- ******************************************************************************
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32l1xx_system
- * @{
- */
-
-/** @addtogroup STM32L1xx_System_Private_Includes
- * @{
- */
-
-#include "stm32l1xx.h"
-
-/**
- * @}
- */
-
-/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32L1xx_System_Private_Defines
- * @{
- */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
- frequency (after reset the MSI is used as SYSCLK source)
-
- IMPORTANT NOTE:
- ==============
- 1. After each device reset the MSI is used as System clock source.
-
- 2. Please make sure that the selected System clock doesn't exceed your device's
- maximum frequency.
-
- 3. If none of the define below is enabled, the MSI (2MHz default) is used as
- System clock source.
-
- 4. The System clock configuration functions provided within this file assume that:
- - For Ultra Low Power Medium Mensity devices an external 8MHz crystal is
- used to drive the System clock.
- If you are using different crystal you have to adapt those functions accordingly.
- */
-
-/* #define SYSCLK_FREQ_MSI */
-
-#ifndef SYSCLK_FREQ_MSI
-/* #define SYSCLK_FREQ_HSI HSI_VALUE */
-/* #define SYSCLK_FREQ_HSE HSE_VALUE */
-/* #define SYSCLK_FREQ_4MHz 4000000 */
-/* #define SYSCLK_FREQ_8MHz 8000000 */
-/* #define SYSCLK_FREQ_16MHz 16000000 */
-#define SYSCLK_FREQ_32MHz 32000000
-#else
-/* #define SYSCLK_FREQ_MSI_64KHz 64000 */
-/* #define SYSCLK_FREQ_MSI_128KHz 128000 */
-/* #define SYSCLK_FREQ_MSI_256KHz 256000 */
-/* #define SYSCLK_FREQ_MSI_512KHz 512000 */
-/* #define SYSCLK_FREQ_MSI_1MHz 1000000 */
-/* #define SYSCLK_FREQ_MSI_2MHz 2000000 */
-/* #define SYSCLK_FREQ_MSI_4MHz 4000000 */
-#endif
-
-/**
- * @}
- */
-
-/** @addtogroup STM32L1xx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32L1xx_System_Private_Variables
- * @{
- */
-
-/*******************************************************************************
-* Clock Definitions
-*******************************************************************************/
-#ifndef SYSCLK_FREQ_MSI
-#ifdef SYSCLK_FREQ_HSI
- uint32_t SystemCoreClock = SYSCLK_FREQ_HSI; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_HSE
- uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_4MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_4MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_8MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_16MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_16MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_32MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_32MHz; /*!< System Clock Frequency (Core Clock) */
-#else /*!< MSI Selected as System Clock source */
- uint32_t SystemCoreClock = MSI_VALUE; /*!< System Clock Frequency (Core Clock) */
-#endif
-#else
-#ifdef SYSCLK_FREQ_MSI_64KHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_64KHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_MSI_128KHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_128KHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_MSI_256KHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_256KHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_MSI_512KHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_512KHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_MSI_1MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_1MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_MSI_2MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_2MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_MSI_4MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_4MHz; /*!< System Clock Frequency (Core Clock) */
-#else
- uint32_t SystemCoreClock = MSI_VALUE; /*!< System Clock Frequency (Core Clock) */
-#endif
-#endif
-
-__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
-__I uint8_t MSITable[7] = {0, 0, 0, 0, 1, 2, 4};
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/**
- * @}
- */
-
-/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
- * @{
- */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSI
- static void SetSysClockToHSI(void);
-#elif defined SYSCLK_FREQ_HSE
- static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_4MHz
- static void SetSysClockTo4(void);
-#elif defined SYSCLK_FREQ_8MHz
- static void SetSysClockTo8(void);
-#elif defined SYSCLK_FREQ_16MHz
- static void SetSysClockTo16(void);
-#elif defined SYSCLK_FREQ_32MHz
- static void SetSysClockTo32(void);
-#else
- static void SetSysClockToMSI(void);
-#endif
-
-/**
- * @}
- */
-
-/** @addtogroup STM32L1xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the Embedded Flash Interface, the PLL and update the
- * SystemCoreClock variable
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-void SystemInit (void)
-{
- /*!< Set MSION bit */
- RCC->CR |= (uint32_t)0x00000100;
-
- /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
- RCC->CFGR &= (uint32_t)0x88FFC00C;
-
- /*!< Reset HSION, HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xEEFEFFFE;
-
- /*!< Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
- RCC->CFGR &= (uint32_t)0xFF02FFFF;
-
- /*!< Disable all interrupts */
- RCC->CIR = 0x00000000;
-
- /*!< Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
- /*!< Configure the Flash Latency cycles and enable prefetch buffer */
- SetSysClock();
-
-}
-
-/**
- * @brief Update SystemCoreClock according to Clock Register Values
- * @note None
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
- uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* MSI used as system clock */
- msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
- SystemCoreClock = (((1 << msirange) * 64000) - (MSITable[msirange] * 24000));
- break;
- case 0x04: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- case 0x08: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
- break;
- case 0x0C: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
- plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
- pllmul = PLLMulTable[(pllmul >> 18)];
- plldiv = (plldiv >> 22) + 1;
-
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
- if (pllsource == 0x00)
- {
- /* HSI oscillator clock selected as PLL clock entry */
- SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
- }
- else
- {
- /* HSE selected as PLL clock entry */
- SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
- }
- break;
- default:
- SystemCoreClock = MSI_VALUE;
- break;
- }
- /* Compute HCLK clock frequency --------------------------------------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
- * @param None
- * @retval None
- */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSI
- SetSysClockToHSI();
-#elif defined SYSCLK_FREQ_HSE
- SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_4MHz
- SetSysClockTo4();
-#elif defined SYSCLK_FREQ_8MHz
- SetSysClockTo8();
-#elif defined SYSCLK_FREQ_16MHz
- SetSysClockTo16();
-#elif defined SYSCLK_FREQ_32MHz
- SetSysClockTo32();
-#else
- SetSysClockToMSI();
-#endif
-
- /* If none of the define above is enabled, the MSI (2MHz default) is used as
- System clock source (default after reset) */
-}
-
-#ifdef SYSCLK_FREQ_HSI
-/**
- * @brief Selects HSI as System clock source and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockToHSI(void)
-{
- __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSI */
- RCC->CR |= ((uint32_t)RCC_CR_HSION);
-
- /* Wait till HSI is ready and if Time out is reached exit */
- do
- {
- HSIStatus = RCC->CR & RCC_CR_HSIRDY;
- StartUpCounter++;
- } while((HSIStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSIRDY) != RESET)
- {
- HSIStatus = (uint32_t)0x01;
- }
- else
- {
- HSIStatus = (uint32_t)0x00;
- }
-
- if (HSIStatus == (uint32_t)0x01)
- {
- /* Enable 64-bit access */
- FLASH->ACR |= FLASH_ACR_ACC64;
-
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTEN;
-
- /* Flash 1 wait state */
- FLASH->ACR |= FLASH_ACR_LATENCY;
-
- /* Enable the PWR APB1 Clock */
- RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-
- /* Select the Voltage Range 1 (1.8V) */
- PWR->CR = PWR_CR_VOS_0;
-
- /* Wait Until the Voltage Regulator is ready */
- while((PWR->CSR & PWR_CSR_VOSF) != RESET)
- {
- }
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
- /* Select HSI as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI;
-
- /* Wait till HSI is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
- {
- }
- }
- else
- {
- /* If HSI fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_HSE
-/**
- * @brief Selects HSE as System clock source and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockToHSE(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Flash 0 wait state */
- FLASH->ACR &= ~FLASH_ACR_LATENCY;
-
- /* Disable Prefetch Buffer */
- FLASH->ACR &= ~FLASH_ACR_PRFTEN;
-
- /* Disable 64-bit access */
- FLASH->ACR &= ~FLASH_ACR_ACC64;
-
- /* Enable the PWR APB1 Clock */
- RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-
- /* Select the Voltage Range 2 (1.5V) */
- PWR->CR = PWR_CR_VOS_1;
-
- /* Wait Until the Voltage Regulator is ready */
- while((PWR->CSR & PWR_CSR_VOSF) != RESET)
- {
- }
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
- /* Select HSE as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
-
- /* Wait till HSE is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#elif defined SYSCLK_FREQ_4MHz
-/**
- * @brief Sets System clock frequency to 4MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo4(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Flash 0 wait state */
- FLASH->ACR &= ~FLASH_ACR_LATENCY;
-
- /* Disable Prefetch Buffer */
- FLASH->ACR &= ~FLASH_ACR_PRFTEN;
-
- /* Disable 64-bit access */
- FLASH->ACR &= ~FLASH_ACR_ACC64;
-
- /* Enable the PWR APB1 Clock */
- RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-
- /* Select the Voltage Range 2 (1.5V) */
- PWR->CR = PWR_CR_VOS_1;
-
- /* Wait Until the Voltage Regulator is ready */
- while((PWR->CSR & PWR_CSR_VOSF) != RESET)
- {
- }
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV2;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
- /* Select HSE as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
-
- /* Wait till HSE is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_8MHz
-/**
- * @brief Sets System clock frequency to 8MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo8(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Flash 0 wait state */
- FLASH->ACR &= ~FLASH_ACR_LATENCY;
-
- /* Disable Prefetch Buffer */
- FLASH->ACR &= ~FLASH_ACR_PRFTEN;
-
- /* Disable 64-bit access */
- FLASH->ACR &= ~FLASH_ACR_ACC64;
-
- /* Enable the PWR APB1 Clock */
- RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-
- /* Select the Voltage Range 2 (1.5V) */
- PWR->CR = PWR_CR_VOS_1;
-
- /* Wait Until the Voltage Regulator is ready */
- while((PWR->CSR & PWR_CSR_VOSF) != RESET)
- {
- }
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
- /* Select HSE as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
-
- /* Wait till HSE is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_16MHz
-/**
- * @brief Sets System clock frequency to 16MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo16(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable 64-bit access */
- FLASH->ACR |= FLASH_ACR_ACC64;
-
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTEN;
-
- /* Flash 1 wait state */
- FLASH->ACR |= FLASH_ACR_LATENCY;
-
- /* Enable the PWR APB1 Clock */
- RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-
- /* Select the Voltage Range 2 (1.5V) */
- PWR->CR = PWR_CR_VOS_1;
-
- /* Wait Until the Voltage Regulator is ready */
- while((PWR->CSR & PWR_CSR_VOSF) != RESET)
- {
- }
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV2;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
- /* PLL configuration: PLLCLK = (HSE * 12) / 3 = 32MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
- RCC_CFGR_PLLDIV));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x0C)
- {
- }
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_32MHz
-/**
- * @brief Sets System clock frequency to 32MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo32(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable 64-bit access */
- FLASH->ACR |= FLASH_ACR_ACC64;
-
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTEN;
-
- /* Flash 1 wait state */
- FLASH->ACR |= FLASH_ACR_LATENCY;
-
- /* Enable the PWR APB1 Clock */
- RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-
- /* Select the Voltage Range 1 (1.8V) */
- PWR->CR = PWR_CR_VOS_0;
-
- /* Wait Until the Voltage Regulator is ready */
- while((PWR->CSR & PWR_CSR_VOSF) != RESET)
- {
- }
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
- /* PLL configuration: PLLCLK = (HSE * 12) / 3 = 32MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
- RCC_CFGR_PLLDIV));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x0C)
- {
- }
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#else
-/**
- * @brief Selects MSI as System clock source and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockToMSI(void)
-{
- __IO uint32_t StartUpCounter = 0, MSIStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable MSI */
- RCC->CR |= ((uint32_t)RCC_CR_MSION);
-
- /* Wait till MSI is ready and if Time out is reached exit */
- do
- {
- MSIStatus = RCC->CR & RCC_CR_MSIRDY;
- StartUpCounter++;
- } while((MSIStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_MSIRDY) != RESET)
- {
- MSIStatus = (uint32_t)0x01;
- }
- else
- {
- MSIStatus = (uint32_t)0x00;
- }
-
- if (MSIStatus == (uint32_t)0x01)
- {
-#ifdef SYSCLK_FREQ_MSI
-#ifdef SYSCLK_FREQ_MSI_4MHz
- /* Enable 64-bit access */
- FLASH->ACR |= FLASH_ACR_ACC64;
-
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTEN;
-
- /* Flash 1 wait state */
- FLASH->ACR |= FLASH_ACR_LATENCY;
-#else
- /* Flash 0 wait state */
- FLASH->ACR &= ~FLASH_ACR_LATENCY;
-
- /* Disable Prefetch Buffer */
- FLASH->ACR &= ~FLASH_ACR_PRFTEN;
-
- /* Disable 64-bit access */
- FLASH->ACR &= ~FLASH_ACR_ACC64;
-#endif
-#endif
- /* Enable the PWR APB1 Clock */
- RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-
- /* Select the Voltage Range 3 (1.2V) */
- PWR->CR = PWR_CR_VOS;
-
- /* Wait Until the Voltage Regulator is ready */
- while((PWR->CSR & PWR_CSR_VOSF) != RESET)
- {
- }
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
-#ifdef SYSCLK_FREQ_MSI
- #ifdef SYSCLK_FREQ_MSI_64KHz
- /* Set MSI clock range */
- RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));
- RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_64KHz;
- #elif defined SYSCLK_FREQ_MSI_128KHz
- /* Set MSI clock range */
- RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));
- RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_128KHz;
- #elif defined SYSCLK_FREQ_MSI_256KHz
- /* Set MSI clock range */
- RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));
- RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_256KHz;
- #elif defined SYSCLK_FREQ_MSI_512KHz
- /* Set MSI clock range */
- RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));
- RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_512KHz;
- #elif defined SYSCLK_FREQ_MSI_1MHz
- /* Set MSI clock range */
- RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));
- RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_1MHz;
- #elif defined SYSCLK_FREQ_MSI_2MHz
- /* Set MSI clock range */
- RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));
- RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_2MHz;
- #elif defined SYSCLK_FREQ_MSI_4MHz
- /* Set MSI clock range */
- RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));
- RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_4MHz;
- #endif
-#endif
-
- /* Select MSI as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_MSI;
-
- /* Wait till MSI is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x00)
- {
- }
- }
- else
- {
- /* If MSI fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
