Add ARM Cortex-M52 port support FreeRTOS#1305 (#1334)
Add ARM Cortex-M52 port support
Add ARM_CM52 and ARM_CM52_NTZ port implementations for GCC and IAR compilers
diff --git a/.github/allowed_urls.txt b/.github/allowed_urls.txt
index 578b90e..fc6d211 100644
--- a/.github/allowed_urls.txt
+++ b/.github/allowed_urls.txt
@@ -1,3 +1,5 @@
https://www.renesas.com/us/en/document/mah/rh850f1k-group-users-manual-hardware?r=1170166
https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rh850-automotive-mcus
https://www.renesas.com/us/en/software-tool/c-compiler-package-rh850-family#downloads
+https://www.microchip.com
+https://www.microchip.com/support
diff --git a/.github/scripts/kernel_checker.py b/.github/scripts/kernel_checker.py
index f442a2c..be2d80d 100755
--- a/.github/scripts/kernel_checker.py
+++ b/.github/scripts/kernel_checker.py
@@ -156,6 +156,7 @@
FREERTOS_ARM_COLLAB_COPYRIGHT_REGEX = r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(C\) 20\d\d Amazon.com, Inc. or its affiliates. All Rights Reserved\.( \*\/)?$)|" + \
r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright 20\d\d(-20\d\d)? Arm Limited and/or its affiliates( +<open-source-office@arm\.com>)?( \*\/)?$)|" + \
+ r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(c\) 20\d\d(-20\d\d)? Arm Technology \(China\) Co., Ltd.All Rights Reserved\.( \*\/)?$)|" + \
r"(^(;|#)?( *(\/\*|\*|#|\/\/))? <open-source-office@arm\.com>( \*\/)?$)"
@@ -198,6 +199,8 @@
]
if (len(lines) > 0) and (lines[0].find("#!") == 0):
lines.remove(lines[0])
+ if (len(lines) > 0) and (len(lines[-1].strip()) == 0):
+ lines.remove(lines[-1])
# Split lines in sections.
headers = dict()
@@ -215,8 +218,10 @@
text_equal = self.isValidHeaderSection(file_ext, "text", headers["text"])
spdx_equal = self.isValidHeaderSection(file_ext, "spdx", headers["spdx"])
- if text_equal and spdx_equal and len(headers["copyright"]) == 3:
- isValid = True
+ if text_equal and spdx_equal:
+ # Some files do not have "open-source-office@arm.com" line.
+ if len(headers["copyright"]) == 3 or len(headers["copyright"]) == 2:
+ isValid = True
return isValid
diff --git a/CMakeLists.txt b/CMakeLists.txt
index f6007d0..9b00726 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -76,6 +76,10 @@
" GCC_ARM_CM35P_NONSECURE - Compiler: GCC Target: ARM Cortex-M35P non-secure\n"
" GCC_ARM_CM35P_SECURE - Compiler: GCC Target: ARM Cortex-M35P secure\n"
" GCC_ARM_CM35P_NTZ_NONSECURE - Compiler: GCC Target: ARM Cortex-M35P non-trustzone non-secure\n"
+ " GCC_ARM_CM52_NONSECURE - Compiler: GCC Target: ARM Cortex-M52 non-secure\n"
+ " GCC_ARM_CM52_SECURE - Compiler: GCC Target: ARM Cortex-M52 secure\n"
+ " GCC_ARM_CM52_NTZ_NONSECURE - Compiler: GCC Target: ARM Cortex-M52 non-trustzone non-secure\n"
+ " GCC_ARM_CM52_TFM - Compiler: GCC Target: ARM Cortex-M52 non-secure for TF-M\n"
" GCC_ARM_CM55_NONSECURE - Compiler: GCC Target: ARM Cortex-M55 non-secure\n"
" GCC_ARM_CM55_SECURE - Compiler: GCC Target: ARM Cortex-M55 secure\n"
" GCC_ARM_CM55_NTZ_NONSECURE - Compiler: GCC Target: ARM Cortex-M55 non-trustzone non-secure\n"
@@ -143,6 +147,10 @@
" IAR_ARM_CM35P_NONSECURE - Compiler: IAR Target: ARM Cortex-M35P non-secure\n"
" IAR_ARM_CM35P_SECURE - Compiler: IAR Target: ARM Cortex-M35P secure\n"
" IAR_ARM_CM35P_NTZ_NONSECURE - Compiler: IAR Target: ARM Cortex-M35P non-trustzone non-secure\n"
+ " IAR_ARM_CM52_NONSECURE - Compiler: IAR Target: ARM Cortex-M52 non-secure\n"
+ " IAR_ARM_CM52_SECURE - Compiler: IAR Target: ARM Cortex-M52 secure\n"
+ " IAR_ARM_CM52_NTZ_NONSECURE - Compiler: IAR Target: ARM Cortex-M52 non-trustzone non-secure\n"
+ " IAR_ARM_CM52_TFM - Compiler: IAR Target: ARM Cortex-M52 non-secure for TF-M\n"
" IAR_ARM_CM55_NONSECURE - Compiler: IAR Target: ARM Cortex-M55 non-secure\n"
" IAR_ARM_CM55_SECURE - Compiler: IAR Target: ARM Cortex-M55 secure\n"
" IAR_ARM_CM55_NTZ_NONSECURE - Compiler: IAR Target: ARM Cortex-M55 non-trustzone non-secure\n"
diff --git a/examples/template_configuration/FreeRTOSConfig.h b/examples/template_configuration/FreeRTOSConfig.h
index da1ad8a..4866356 100644
--- a/examples/template_configuration/FreeRTOSConfig.h
+++ b/examples/template_configuration/FreeRTOSConfig.h
@@ -602,10 +602,10 @@
/* Set configENABLE_MVE to 1 to enable the M-Profile Vector Extension (MVE)
* support, or 0 to leave the MVE support disabled. This option is only
- * applicable to Cortex-M55 and Cortex-M85 ports as M-Profile Vector Extension
- * (MVE) is available only on these architectures. configENABLE_MVE must be left
- * undefined, or defined to 0 for the Cortex-M23,Cortex-M33 and Cortex-M35P
- * ports. */
+ * applicable to Cortex-M52, Cortex-M55 and Cortex-M85 ports as M-Profile
+ * Vector Extension (MVE) is available only on these architectures.
+ * configENABLE_MVE must be left undefined, or defined to 0 for the
+ * Cortex-M23,Cortex-M33 and Cortex-M35P ports. */
#define configENABLE_MVE 1
/******************************************************************************/
diff --git a/portable/ARMv8M/ReadMe.txt b/portable/ARMv8M/ReadMe.txt
index c6dbe77..9dd98e8 100644
--- a/portable/ARMv8M/ReadMe.txt
+++ b/portable/ARMv8M/ReadMe.txt
@@ -1,11 +1,11 @@
This directory tree contains the master copy of the FreeRTOS Armv8-M and
Armv8.1-M ports.
Do not use the files located here! These file are copied into separate
-FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NNN directories prior to each
+FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|52|55|85]_NNN directories prior to each
FreeRTOS release.
If your Armv8-M and Armv8.1-M application uses TrustZone then use the files from the
-FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85] directories.
+FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|52|55|85] directories.
If your Armv8-M and Armv8.1-M application does not use TrustZone then use the files from
-the FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NTZ directories.
+the FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|52|55|85]_NTZ directories.
diff --git a/portable/ARMv8M/copy_files.py b/portable/ARMv8M/copy_files.py
index 023fb68..02cffbb 100644
--- a/portable/ARMv8M/copy_files.py
+++ b/portable/ARMv8M/copy_files.py
@@ -33,8 +33,8 @@
_FREERTOS_PORTABLE_DIRECTORY_ = os.path.dirname(_THIS_FILE_DIRECTORY_)
_COMPILERS_ = ['GCC', 'IAR']
-_ARCH_NS_ = ['ARM_CM85', 'ARM_CM85_NTZ', 'ARM_CM55', 'ARM_CM55_NTZ', 'ARM_CM35P', 'ARM_CM35P_NTZ', 'ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ']
-_ARCH_S_ = ['ARM_CM85', 'ARM_CM55', 'ARM_CM35P', 'ARM_CM33', 'ARM_CM23']
+_ARCH_NS_ = ['ARM_CM85', 'ARM_CM85_NTZ', 'ARM_CM55', 'ARM_CM55_NTZ', 'ARM_CM52', 'ARM_CM52_NTZ', 'ARM_CM35P', 'ARM_CM35P_NTZ', 'ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ']
+_ARCH_S_ = ['ARM_CM85', 'ARM_CM55', 'ARM_CM52', 'ARM_CM35P', 'ARM_CM33', 'ARM_CM23']
# Files to be compiled in the Secure Project
_SECURE_COMMON_FILE_PATHS_ = [
@@ -49,6 +49,7 @@
'ARM_CM23' :[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM23')],
'ARM_CM33' :[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')],
'ARM_CM35P':[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')],
+ 'ARM_CM52' :[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')],
'ARM_CM55' :[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')],
'ARM_CM85' :[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')]
},
@@ -56,6 +57,7 @@
'ARM_CM23' :[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM23')],
'ARM_CM33' :[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')],
'ARM_CM35P':[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')],
+ 'ARM_CM52' :[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')],
'ARM_CM55' :[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')],
'ARM_CM85' :[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')]
}
@@ -78,6 +80,12 @@
'ARM_CM35P_NTZ' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'portasm.c'),
os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.c'),
os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM35P', 'portmacro.h')],
+ 'ARM_CM52' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'portasm.c'),
+ os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'mpu_wrappers_v2_asm.c'),
+ os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM52', 'portmacro.h')],
+ 'ARM_CM52_NTZ' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'portasm.c'),
+ os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.c'),
+ os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM52', 'portmacro.h')],
'ARM_CM55' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'portasm.c'),
os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'mpu_wrappers_v2_asm.c'),
os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM55', 'portmacro.h')],
@@ -102,6 +110,12 @@
'ARM_CM35P_NTZ' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'portasm.s'),
os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.S'),
os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM35P', 'portmacro.h')],
+ 'ARM_CM52' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'portasm.s'),
+ os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'mpu_wrappers_v2_asm.S'),
+ os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM52', 'portmacro.h')],
+ 'ARM_CM52_NTZ' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'portasm.s'),
+ os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.S'),
+ os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM52', 'portmacro.h')],
'ARM_CM55' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'portasm.s'),
os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'mpu_wrappers_v2_asm.S'),
os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM55', 'portmacro.h')],
diff --git a/portable/ARMv8M/non_secure/ReadMe.txt b/portable/ARMv8M/non_secure/ReadMe.txt
index ed40fb6..a56b786 100644
--- a/portable/ARMv8M/non_secure/ReadMe.txt
+++ b/portable/ARMv8M/non_secure/ReadMe.txt
@@ -1,11 +1,11 @@
This directory tree contains the master copy of the FreeRTOS Armv8-M and
Armv8.1-M ports.
Do not use the files located here! These file are copied into separate
-FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NNN directories prior to
+FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|52|55|85]_NNN directories prior to
each FreeRTOS release.
If your Armv8-M/Armv8.1-M application uses TrustZone then use the files from the
-FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85] directories.
+FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|52|55|85] directories.
If your Armv8-M/Armv8.1-M application does not use TrustZone then use the files from
-the FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NTZ directories.
+the FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|52|55|85]_NTZ directories.
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM52/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM52/portmacro.h
new file mode 100644
index 0000000..1041a03
--- /dev/null
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM52/portmacro.h
@@ -0,0 +1,80 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright (c) 2025 Arm Technology (China) Co., Ltd.All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_MVE
+ #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.
+#endif /* configENABLE_MVE */
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME "Cortex-M52"
+#define portHAS_ARMV8M_MAIN_EXTENSION 1
+#define portARMV8M_MINOR_VERSION 1
+#define portDONT_DISCARD __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
+/*-----------------------------------------------------------*/
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM52/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM52/portmacro.h
new file mode 100644
index 0000000..19de84e
--- /dev/null
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM52/portmacro.h
@@ -0,0 +1,87 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright (c) 2025 Arm Technology (China) Co., Ltd.All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_MVE
+ #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.
+#endif /* configENABLE_MVE */
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME "Cortex-M52"
+#define portHAS_ARMV8M_MAIN_EXTENSION 1
+#define portARMV8M_MINOR_VERSION 1
+#define portDONT_DISCARD __root
+/*-----------------------------------------------------------*/
+
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+#pragma diag_suppress=Be006
+#pragma diag_suppress=Pa082
+/*-----------------------------------------------------------*/
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
diff --git a/portable/ARMv8M/secure/ReadMe.txt b/portable/ARMv8M/secure/ReadMe.txt
index ed40fb6..a56b786 100644
--- a/portable/ARMv8M/secure/ReadMe.txt
+++ b/portable/ARMv8M/secure/ReadMe.txt
@@ -1,11 +1,11 @@
This directory tree contains the master copy of the FreeRTOS Armv8-M and
Armv8.1-M ports.
Do not use the files located here! These file are copied into separate
-FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NNN directories prior to
+FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|52|55|85]_NNN directories prior to
each FreeRTOS release.
If your Armv8-M/Armv8.1-M application uses TrustZone then use the files from the
-FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85] directories.
+FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|52|55|85] directories.
If your Armv8-M/Armv8.1-M application does not use TrustZone then use the files from
-the FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NTZ directories.
+the FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|52|55|85]_NTZ directories.
diff --git a/portable/CMakeLists.txt b/portable/CMakeLists.txt
index a634965..870d399 100644
--- a/portable/CMakeLists.txt
+++ b/portable/CMakeLists.txt
@@ -182,6 +182,28 @@
GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c>
+ $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM52_NONSECURE>:
+ GCC/ARM_CM52/non_secure/port.c
+ GCC/ARM_CM52/non_secure/portasm.c
+ GCC/ARM_CM52/non_secure/mpu_wrappers_v2_asm.c>
+
+ $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM52_SECURE>:
+ GCC/ARM_CM52/secure/secure_context_port.c
+ GCC/ARM_CM52/secure/secure_context.c
+ GCC/ARM_CM52/secure/secure_heap.c
+ GCC/ARM_CM52/secure/secure_init.c>
+
+ $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM52_NTZ_NONSECURE>:
+ GCC/ARM_CM52_NTZ/non_secure/port.c
+ GCC/ARM_CM52_NTZ/non_secure/portasm.c
+ GCC/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.c>
+
+ $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM52_TFM>:
+ GCC/ARM_CM52_NTZ/non_secure/port.c
+ GCC/ARM_CM52_NTZ/non_secure/portasm.c
+ GCC/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.c
+ ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c>
+
$<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM85_NONSECURE>:
GCC/ARM_CM85/non_secure/port.c
GCC/ARM_CM85/non_secure/portasm.c
@@ -503,6 +525,28 @@
IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c>
+ $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM52_NONSECURE>:
+ IAR/ARM_CM52/non_secure/port.c
+ IAR/ARM_CM52/non_secure/portasm.s
+ IAR/ARM_CM52/non_secure/mpu_wrappers_v2_asm.S>
+
+ $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM52_SECURE>:
+ IAR/ARM_CM52/secure/secure_context_port_asm.s
+ IAR/ARM_CM52/secure/secure_context.c
+ IAR/ARM_CM52/secure/secure_heap.c
+ IAR/ARM_CM52/secure/secure_init.c>
+
+ $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM52_NTZ_NONSECURE>:
+ IAR/ARM_CM52_NTZ/non_secure/port.c
+ IAR/ARM_CM52_NTZ/non_secure/portasm.s
+ IAR/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.S>
+
+ $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM52_TFM>:
+ IAR/ARM_CM52_NTZ/non_secure/port.c
+ IAR/ARM_CM52_NTZ/non_secure/portasm.s
+ IAR/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.S
+ ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c>
+
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_NONSECURE>:
IAR/ARM_CM85/non_secure/port.c
IAR/ARM_CM85/non_secure/portasm.s
@@ -775,12 +819,12 @@
FREERTOS_PORT STREQUAL "IAR_ARM_CM4F_MPU" OR
FREERTOS_PORT STREQUAL "RVDS_ARM_CM4_MPU" OR
FREERTOS_PORT STREQUAL "GCC_ARM_CRX_MPU" OR
- FREERTOS_PORT MATCHES "GCC_ARM_CM(23|33|55|85)_NTZ_NONSECURE" OR
- FREERTOS_PORT MATCHES "GCC_ARM_CM(23|33|55|85)_NONSECURE" OR
- FREERTOS_PORT MATCHES "GCC_ARM_CM(33|55|85)_TFM" OR
- FREERTOS_PORT MATCHES "IAR_ARM_CM(23|33|55|85)_NTZ_NONSECURE" OR
- FREERTOS_PORT MATCHES "IAR_ARM_CM(23|33|55|85)_NONSECURE" OR
- FREERTOS_PORT MATCHES "IAR_ARM_CM(33|55|85)_TFM"
+ FREERTOS_PORT MATCHES "GCC_ARM_CM(23|33|52|55|85)_NTZ_NONSECURE" OR
+ FREERTOS_PORT MATCHES "GCC_ARM_CM(23|33|52|55|85)_NONSECURE" OR
+ FREERTOS_PORT MATCHES "GCC_ARM_CM(33|52|55|85)_TFM" OR
+ FREERTOS_PORT MATCHES "IAR_ARM_CM(23|33|52|55|85)_NTZ_NONSECURE" OR
+ FREERTOS_PORT MATCHES "IAR_ARM_CM(23|33|52|55|85)_NONSECURE" OR
+ FREERTOS_PORT MATCHES "IAR_ARM_CM(33|52|55|85)_TFM"
)
target_sources(freertos_kernel_port PRIVATE
Common/mpu_wrappers.c
@@ -794,7 +838,7 @@
message(FATAL_ERROR "ARMv8.1-M PACBTI support in the kernel is not yet enabled for GNU toolchain due to known issues.")
endif()
- if(FREERTOS_PORT MATCHES ".*ARM_CM85")
+ if(FREERTOS_PORT MATCHES ".*ARM_CM(52|85)")
if(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_STANDARD")
target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},ARMClang>:-mbranch-protection=standard>)
target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},IAR>:$<$<COMPILE_LANGUAGE:C,CXX>:--branch_protection=bti+pac-ret>>)
@@ -881,7 +925,7 @@
)
endif()
else()
- message(FATAL_ERROR "FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG option is currently only supported on ARM Cortex-M85 FreeRTOS port.")
+ message(FATAL_ERROR "FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG option is currently only supported on ARM Cortex-M85|M52 FreeRTOS port.")
endif()
endif()
@@ -959,6 +1003,11 @@
$<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM55_NTZ_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM55_NTZ/non_secure>
$<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM55_TFM>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM55_NTZ/non_secure>
+ $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM52_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM52/non_secure>
+ $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM52_SECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM52/secure>
+ $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM52_NTZ_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM52_NTZ/non_secure>
+ $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM52_TFM>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM52_NTZ/non_secure>
+
$<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM85_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85/non_secure>
$<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM85_SECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85/secure>
$<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM85_NTZ_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85_NTZ/non_secure>
@@ -1094,6 +1143,11 @@
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM55_NTZ_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM55_NTZ/non_secure>
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM55_TFM>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM55_NTZ/non_secure>
+ $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM52_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM52/non_secure>
+ $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM52_SECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM52/secure>
+ $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM52_NTZ_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM52_NTZ/non_secure>
+ $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM52_TFM>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM52_NTZ/non_secure>
+
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM85/non_secure>
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_SECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM85/secure>
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_NTZ_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM85_NTZ/non_secure>
diff --git a/portable/GCC/ARM_CM52/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM52/non_secure/mpu_wrappers_v2_asm.c
new file mode 100644
index 0000000..33410a0
--- /dev/null
+++ b/portable/GCC/ARM_CM52/non_secure/mpu_wrappers_v2_asm.c
@@ -0,0 +1,2056 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+#include "event_groups.h"
+#include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ #if ( INCLUDE_xTaskDelayUntil == 1 )
+
+ BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+ const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+ const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskDelayUntilImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskDelayUntil_Unpriv \n"
+ " MPU_xTaskDelayUntil_Priv: \n"
+ " b MPU_xTaskDelayUntilImpl \n"
+ " MPU_xTaskDelayUntil_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_xTaskAbortDelay == 1 )
+
+ BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskAbortDelayImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskAbortDelay_Unpriv \n"
+ " MPU_xTaskAbortDelay_Priv: \n"
+ " b MPU_xTaskAbortDelayImpl \n"
+ " MPU_xTaskAbortDelay_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_vTaskDelay == 1 )
+
+ void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTaskDelayImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vTaskDelay_Unpriv \n"
+ " MPU_vTaskDelay_Priv: \n"
+ " b MPU_vTaskDelayImpl \n"
+ " MPU_vTaskDelay_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+ UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxTaskPriorityGetImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_uxTaskPriorityGet_Unpriv \n"
+ " MPU_uxTaskPriorityGet_Priv: \n"
+ " b MPU_uxTaskPriorityGetImpl \n"
+ " MPU_uxTaskPriorityGet_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_eTaskGetState == 1 )
+
+ eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_eTaskGetStateImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_eTaskGetState_Unpriv \n"
+ " MPU_eTaskGetState_Priv: \n"
+ " b MPU_eTaskGetStateImpl \n"
+ " MPU_eTaskGetState_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+
+ void MPU_vTaskGetInfo( TaskHandle_t xTask,
+ TaskStatus_t * pxTaskStatus,
+ BaseType_t xGetFreeStackSpace,
+ eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTaskGetInfo( TaskHandle_t xTask,
+ TaskStatus_t * pxTaskStatus,
+ BaseType_t xGetFreeStackSpace,
+ eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTaskGetInfoImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vTaskGetInfo_Unpriv \n"
+ " MPU_vTaskGetInfo_Priv: \n"
+ " b MPU_vTaskGetInfoImpl \n"
+ " MPU_vTaskGetInfo_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+ TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGetIdleTaskHandleImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n"
+ " MPU_xTaskGetIdleTaskHandle_Priv: \n"
+ " b MPU_xTaskGetIdleTaskHandleImpl \n"
+ " MPU_xTaskGetIdleTaskHandle_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+
+ void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTaskSuspendImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vTaskSuspend_Unpriv \n"
+ " MPU_vTaskSuspend_Priv: \n"
+ " b MPU_vTaskSuspendImpl \n"
+ " MPU_vTaskSuspend_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+
+ void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTaskResumeImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vTaskResume_Unpriv \n"
+ " MPU_vTaskResume_Priv: \n"
+ " b MPU_vTaskResumeImpl \n"
+ " MPU_vTaskResume_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+/*-----------------------------------------------------------*/
+
+ TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGetTickCountImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskGetTickCount_Unpriv \n"
+ " MPU_xTaskGetTickCount_Priv: \n"
+ " b MPU_xTaskGetTickCountImpl \n"
+ " MPU_xTaskGetTickCount_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxTaskGetNumberOfTasksImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n"
+ " MPU_uxTaskGetNumberOfTasks_Priv: \n"
+ " b MPU_uxTaskGetNumberOfTasksImpl \n"
+ " MPU_uxTaskGetNumberOfTasks_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_ulTaskGetRunTimeCounterImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n"
+ " MPU_ulTaskGetRunTimeCounter_Priv: \n"
+ " b MPU_ulTaskGetRunTimeCounterImpl \n"
+ " MPU_ulTaskGetRunTimeCounter_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
+ );
+ }
+
+ #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_ulTaskGetRunTimePercentImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_ulTaskGetRunTimePercent_Unpriv \n"
+ " MPU_ulTaskGetRunTimePercent_Priv: \n"
+ " b MPU_ulTaskGetRunTimePercentImpl \n"
+ " MPU_ulTaskGetRunTimePercent_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
+ );
+ }
+
+ #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n"
+ " MPU_ulTaskGetIdleRunTimePercent_Priv: \n"
+ " b MPU_ulTaskGetIdleRunTimePercentImpl \n"
+ " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
+ );
+ }
+
+ #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n"
+ " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n"
+ " b MPU_ulTaskGetIdleRunTimeCounterImpl \n"
+ " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
+ );
+ }
+
+ #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+ void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+ TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+ TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTaskSetApplicationTaskTagImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n"
+ " MPU_vTaskSetApplicationTaskTag_Priv: \n"
+ " b MPU_vTaskSetApplicationTaskTagImpl \n"
+ " MPU_vTaskSetApplicationTaskTag_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+ TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGetApplicationTaskTagImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n"
+ " MPU_xTaskGetApplicationTaskTag_Priv: \n"
+ " b MPU_xTaskGetApplicationTaskTagImpl \n"
+ " MPU_xTaskGetApplicationTaskTag_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+ void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+ BaseType_t xIndex,
+ void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+ BaseType_t xIndex,
+ void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n"
+ " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n"
+ " b MPU_vTaskSetThreadLocalStoragePointerImpl \n"
+ " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
+ );
+ }
+
+ #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+ void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+ BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+ BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n"
+ " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n"
+ " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n"
+ " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
+ );
+ }
+
+ #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+
+ UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+ const UBaseType_t uxArraySize,
+ configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+ const UBaseType_t uxArraySize,
+ configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxTaskGetSystemStateImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_uxTaskGetSystemState_Unpriv \n"
+ " MPU_uxTaskGetSystemState_Priv: \n"
+ " b MPU_uxTaskGetSystemStateImpl \n"
+ " MPU_uxTaskGetSystemState_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+ UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n"
+ " MPU_uxTaskGetStackHighWaterMark_Priv: \n"
+ " b MPU_uxTaskGetStackHighWaterMarkImpl \n"
+ " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+
+ configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n"
+ " MPU_uxTaskGetStackHighWaterMark2_Priv: \n"
+ " b MPU_uxTaskGetStackHighWaterMark2Impl \n"
+ " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+
+ TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGetCurrentTaskHandleImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n"
+ " MPU_xTaskGetCurrentTaskHandle_Priv: \n"
+ " b MPU_xTaskGetCurrentTaskHandleImpl \n"
+ " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
+ );
+ }
+
+ #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_xTaskGetSchedulerState == 1 )
+
+ BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGetSchedulerStateImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskGetSchedulerState_Unpriv \n"
+ " MPU_xTaskGetSchedulerState_Priv: \n"
+ " b MPU_xTaskGetSchedulerStateImpl \n"
+ " MPU_xTaskGetSchedulerState_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+/*-----------------------------------------------------------*/
+
+ void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTaskSetTimeOutStateImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vTaskSetTimeOutState_Unpriv \n"
+ " MPU_vTaskSetTimeOutState_Priv: \n"
+ " b MPU_vTaskSetTimeOutStateImpl \n"
+ " MPU_vTaskSetTimeOutState_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+ TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+ TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskCheckForTimeOutImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskCheckForTimeOut_Unpriv \n"
+ " MPU_xTaskCheckForTimeOut_Priv: \n"
+ " b MPU_xTaskCheckForTimeOutImpl \n"
+ " MPU_xTaskCheckForTimeOut_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+ BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGenericNotifyImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskGenericNotify_Unpriv \n"
+ " MPU_xTaskGenericNotify_Priv: \n"
+ " b MPU_xTaskGenericNotifyImpl \n"
+ " MPU_xTaskGenericNotify_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+ BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGenericNotifyWaitImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskGenericNotifyWait_Unpriv \n"
+ " MPU_xTaskGenericNotifyWait_Priv: \n"
+ " b MPU_xTaskGenericNotifyWaitImpl \n"
+ " MPU_xTaskGenericNotifyWait_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+ uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+ BaseType_t xClearCountOnExit,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+ BaseType_t xClearCountOnExit,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_ulTaskGenericNotifyTakeImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_ulTaskGenericNotifyTake_Unpriv \n"
+ " MPU_ulTaskGenericNotifyTake_Priv: \n"
+ " b MPU_ulTaskGenericNotifyTakeImpl \n"
+ " MPU_ulTaskGenericNotifyTake_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+ BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+ UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+ UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGenericNotifyStateClearImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n"
+ " MPU_xTaskGenericNotifyStateClear_Priv: \n"
+ " b MPU_xTaskGenericNotifyStateClearImpl \n"
+ " MPU_xTaskGenericNotifyStateClear_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+ uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+ UBaseType_t uxIndexToClear,
+ uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+ UBaseType_t uxIndexToClear,
+ uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_ulTaskGenericNotifyValueClearImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n"
+ " MPU_ulTaskGenericNotifyValueClear_Priv: \n"
+ " b MPU_ulTaskGenericNotifyValueClearImpl \n"
+ " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+ const void * const pvItemToQueue,
+ TickType_t xTicksToWait,
+ const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+ const void * const pvItemToQueue,
+ TickType_t xTicksToWait,
+ const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueGenericSendImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xQueueGenericSend_Unpriv \n"
+ " MPU_xQueueGenericSend_Priv: \n"
+ " b MPU_xQueueGenericSendImpl \n"
+ " MPU_xQueueGenericSend_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxQueueMessagesWaitingImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_uxQueueMessagesWaiting_Unpriv \n"
+ " MPU_uxQueueMessagesWaiting_Priv: \n"
+ " b MPU_uxQueueMessagesWaitingImpl \n"
+ " MPU_uxQueueMessagesWaiting_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxQueueSpacesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_uxQueueSpacesAvailable_Unpriv \n"
+ " MPU_uxQueueSpacesAvailable_Priv: \n"
+ " b MPU_uxQueueSpacesAvailableImpl \n"
+ " MPU_uxQueueSpacesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+ void * const pvBuffer,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+ void * const pvBuffer,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueReceiveImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xQueueReceive_Unpriv \n"
+ " MPU_xQueueReceive_Priv: \n"
+ " b MPU_xQueueReceiveImpl \n"
+ " MPU_xQueueReceive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+ void * const pvBuffer,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+ void * const pvBuffer,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueuePeekImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xQueuePeek_Unpriv \n"
+ " MPU_xQueuePeek_Priv: \n"
+ " b MPU_xQueuePeekImpl \n"
+ " MPU_xQueuePeek_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueSemaphoreTakeImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xQueueSemaphoreTake_Unpriv \n"
+ " MPU_xQueueSemaphoreTake_Priv: \n"
+ " b MPU_xQueueSemaphoreTakeImpl \n"
+ " MPU_xQueueSemaphoreTake_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+ TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueGetMutexHolderImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xQueueGetMutexHolder_Unpriv \n"
+ " MPU_xQueueGetMutexHolder_Priv: \n"
+ " b MPU_xQueueGetMutexHolderImpl \n"
+ " MPU_xQueueGetMutexHolder_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
+ );
+ }
+
+ #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+ BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueTakeMutexRecursiveImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xQueueTakeMutexRecursive_Unpriv \n"
+ " MPU_xQueueTakeMutexRecursive_Priv: \n"
+ " b MPU_xQueueTakeMutexRecursiveImpl \n"
+ " MPU_xQueueTakeMutexRecursive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+ BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueGiveMutexRecursiveImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xQueueGiveMutexRecursive_Unpriv \n"
+ " MPU_xQueueGiveMutexRecursive_Priv: \n"
+ " b MPU_xQueueGiveMutexRecursiveImpl \n"
+ " MPU_xQueueGiveMutexRecursive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_QUEUE_SETS == 1 )
+
+ QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+ const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+ const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueSelectFromSetImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xQueueSelectFromSet_Unpriv \n"
+ " MPU_xQueueSelectFromSet_Priv: \n"
+ " b MPU_xQueueSelectFromSetImpl \n"
+ " MPU_xQueueSelectFromSet_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_QUEUE_SETS == 1 )
+
+ BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+ QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+ QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueAddToSetImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xQueueAddToSet_Unpriv \n"
+ " MPU_xQueueAddToSet_Priv: \n"
+ " b MPU_xQueueAddToSetImpl \n"
+ " MPU_xQueueAddToSet_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+ void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+ const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+ const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vQueueAddToRegistryImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vQueueAddToRegistry_Unpriv \n"
+ " MPU_vQueueAddToRegistry_Priv: \n"
+ " b MPU_vQueueAddToRegistryImpl \n"
+ " MPU_vQueueAddToRegistry_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
+ );
+ }
+
+ #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+ void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vQueueUnregisterQueueImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vQueueUnregisterQueue_Unpriv \n"
+ " MPU_vQueueUnregisterQueue_Priv: \n"
+ " b MPU_vQueueUnregisterQueueImpl \n"
+ " MPU_vQueueUnregisterQueue_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
+ );
+ }
+
+ #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+ const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_pcQueueGetNameImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_pcQueueGetName_Unpriv \n"
+ " MPU_pcQueueGetName_Priv: \n"
+ " b MPU_pcQueueGetNameImpl \n"
+ " MPU_pcQueueGetName_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
+ );
+ }
+
+ #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_pvTimerGetTimerIDImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_pvTimerGetTimerID_Unpriv \n"
+ " MPU_pvTimerGetTimerID_Priv: \n"
+ " b MPU_pvTimerGetTimerIDImpl \n"
+ " MPU_pvTimerGetTimerID_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+ void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+ void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTimerSetTimerIDImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vTimerSetTimerID_Unpriv \n"
+ " MPU_vTimerSetTimerID_Priv: \n"
+ " b MPU_vTimerSetTimerIDImpl \n"
+ " MPU_vTimerSetTimerID_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTimerIsTimerActiveImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTimerIsTimerActive_Unpriv \n"
+ " MPU_xTimerIsTimerActive_Priv: \n"
+ " b MPU_xTimerIsTimerActiveImpl \n"
+ " MPU_xTimerIsTimerActive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n"
+ " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n"
+ " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n"
+ " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTimerGenericCommandFromTaskImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTimerGenericCommandFromTask_Unpriv \n"
+ " MPU_xTimerGenericCommandFromTask_Priv: \n"
+ " b MPU_xTimerGenericCommandFromTaskImpl \n"
+ " MPU_xTimerGenericCommandFromTask_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_pcTimerGetNameImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_pcTimerGetName_Unpriv \n"
+ " MPU_pcTimerGetName_Priv: \n"
+ " b MPU_pcTimerGetNameImpl \n"
+ " MPU_pcTimerGetName_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+ const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+ const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTimerSetReloadModeImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vTimerSetReloadMode_Unpriv \n"
+ " MPU_vTimerSetReloadMode_Priv: \n"
+ " b MPU_vTimerSetReloadModeImpl \n"
+ " MPU_vTimerSetReloadMode_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTimerGetReloadModeImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTimerGetReloadMode_Unpriv \n"
+ " MPU_xTimerGetReloadMode_Priv: \n"
+ " b MPU_xTimerGetReloadModeImpl \n"
+ " MPU_xTimerGetReloadMode_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxTimerGetReloadModeImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_uxTimerGetReloadMode_Unpriv \n"
+ " MPU_uxTimerGetReloadMode_Priv: \n"
+ " b MPU_uxTimerGetReloadModeImpl \n"
+ " MPU_uxTimerGetReloadMode_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTimerGetPeriodImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTimerGetPeriod_Unpriv \n"
+ " MPU_xTimerGetPeriod_Priv: \n"
+ " b MPU_xTimerGetPeriodImpl \n"
+ " MPU_xTimerGetPeriod_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTimerGetExpiryTimeImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTimerGetExpiryTime_Unpriv \n"
+ " MPU_xTimerGetExpiryTime_Priv: \n"
+ " b MPU_xTimerGetExpiryTimeImpl \n"
+ " MPU_xTimerGetExpiryTime_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_EVENT_GROUPS == 1 )
+
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupWaitBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupWaitBits_Unpriv \n"
+ " MPU_xEventGroupWaitBits_Priv: \n"
+ " b MPU_xEventGroupWaitBitsImpl \n"
+ " MPU_xEventGroupWaitBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_EVENT_GROUPS == 1 )
+
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupClearBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupClearBits_Unpriv \n"
+ " MPU_xEventGroupClearBits_Priv: \n"
+ " b MPU_xEventGroupClearBitsImpl \n"
+ " MPU_xEventGroupClearBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_EVENT_GROUPS == 1 )
+
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSetBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupSetBits_Unpriv \n"
+ " MPU_xEventGroupSetBits_Priv: \n"
+ " b MPU_xEventGroupSetBitsImpl \n"
+ " MPU_xEventGroupSetBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_EVENT_GROUPS == 1 )
+
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSyncImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupSync_Unpriv \n"
+ " MPU_xEventGroupSync_Priv: \n"
+ " b MPU_xEventGroupSyncImpl \n"
+ " MPU_xEventGroupSync_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
+
+ UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxEventGroupGetNumberImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_uxEventGroupGetNumber_Unpriv \n"
+ " MPU_uxEventGroupGetNumber_Priv: \n"
+ " b MPU_uxEventGroupGetNumberImpl \n"
+ " MPU_uxEventGroupGetNumber_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
+ );
+ }
+
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
+
+ void MPU_vEventGroupSetNumber( void * xEventGroup,
+ UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vEventGroupSetNumber( void * xEventGroup,
+ UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vEventGroupSetNumberImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vEventGroupSetNumber_Unpriv \n"
+ " MPU_vEventGroupSetNumber_Priv: \n"
+ " b MPU_vEventGroupSetNumberImpl \n"
+ " MPU_vEventGroupSetNumber_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
+ );
+ }
+
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSendImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSend_Unpriv \n"
+ " MPU_xStreamBufferSend_Priv: \n"
+ " b MPU_xStreamBufferSendImpl \n"
+ " MPU_xStreamBufferSend_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferReceiveImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferReceive_Unpriv \n"
+ " MPU_xStreamBufferReceive_Priv: \n"
+ " b MPU_xStreamBufferReceiveImpl \n"
+ " MPU_xStreamBufferReceive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsFullImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferIsFull_Unpriv \n"
+ " MPU_xStreamBufferIsFull_Priv: \n"
+ " b MPU_xStreamBufferIsFullImpl \n"
+ " MPU_xStreamBufferIsFull_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsEmptyImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
+ " MPU_xStreamBufferIsEmpty_Priv: \n"
+ " b MPU_xStreamBufferIsEmptyImpl \n"
+ " MPU_xStreamBufferIsEmpty_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
+ " MPU_xStreamBufferSpacesAvailable_Priv: \n"
+ " b MPU_xStreamBufferSpacesAvailableImpl \n"
+ " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferBytesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
+ " MPU_xStreamBufferBytesAvailable_Priv: \n"
+ " b MPU_xStreamBufferBytesAvailableImpl \n"
+ " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
+ " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
+ " b MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
+ " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM52/non_secure/port.c b/portable/GCC/ARM_CM52/non_secure/port.c
new file mode 100644
index 0000000..76d2b24
--- /dev/null
+++ b/portable/GCC/ARM_CM52/non_secure/port.c
@@ -0,0 +1,2280 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU includes. */
+#include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if ( configENABLE_TRUSTZONE == 1 )
+ /* Secure components includes. */
+ #include "secure_context.h"
+ #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration settings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+ #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+ #define portUSE_PSPLIM_REGISTER 0
+#else
+ #define portUSE_PSPLIM_REGISTER 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
+#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
+#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used during system call enter and exit.
+ */
+#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE ( 3UL )
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS ( 20UL )
+#define portCPACR_CP11_POS ( 22UL )
+
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS ( 31UL )
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS ( 30UL )
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Offsets in the stack to the parameters when inside the SVC handler.
+ */
+#define portOFFSET_TO_LR ( 5 )
+#define portOFFSET_TO_PC ( 6 )
+#define portOFFSET_TO_PSR ( 7 )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
+
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+
+ /* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+ #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE_BIT ( 1UL << 0UL )
+
+/* Extract first address of the MPU region as encoded in the
+ * RBAR (Region Base Address Register) value. */
+#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
+ ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK )
+
+/* Extract last address of the MPU region as encoded in the
+ * RLAR (Region Limit Address Register) value. */
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
+ ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
+
+/* Does addr lies within [start, end] address range? */
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
+ ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
+
+/* Is the access request satisfied by the available permissions? */
+#define portIS_AUTHORIZED( accessRequest, permissions ) \
+ ( ( ( permissions ) & ( accessRequest ) ) == accessRequest )
+
+/* Max value that fits in a uint32_t type. */
+#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The maximum 24-bit number.
+ *
+ * It is needed because the systick is a 24-bit counter.
+ */
+#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
+
+/**
+ * @brief A fiddle factor to estimate the number of SysTick counts that would
+ * have occurred while the SysTick counter is stopped during tickless idle
+ * calculations.
+ */
+#define portMISSED_COUNTS_FACTOR ( 94UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR ( 0x01000000 )
+
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF FD
+ * 1111 1111 1111 1111 1111 1111 1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )
+#else
+
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF BC
+ * 1111 1111 1111 1111 1111 1111 1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ * Bit[0] = 0 ==> The task is privileged.
+ * Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
+
+/**
+ * @brief Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register.
+ */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS 1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT 0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+ #define portCONTROL_UPAC_EN ( 1UL << 7UL )
+ #define portCONTROL_PAC_EN ( 1UL << 6UL )
+ #define portCONTROL_UBTI_EN ( 1UL << 5UL )
+ #define portCONTROL_BTI_EN ( 1UL << 4UL )
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief Extract MPU region's access permissions from the Region Base Address
+ * Register (RBAR) value.
+ *
+ * @param ulRBARValue RBAR value for the MPU region.
+ *
+ * @return uint32_t Access permissions.
+ */
+ static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
+
+#if ( configENABLE_MPU == 1 )
+
+ /**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_FPU == 1 )
+
+ /**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ /**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ *
+ * The implementation in this file is weak to allow application writers to
+ * change the timer used to generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether the current execution context is interrupt.
+ *
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE
+ * otherwise.
+ */
+BaseType_t xPortIsInsideInterrupt( void );
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
+ */
+ void vSystemCallEnter( uint32_t * pulTaskStack,
+ uint32_t ulLR,
+ uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief Raise SVC for exiting from a system call.
+ */
+ void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+ void vSystemCallExit( uint32_t * pulSystemCallStack,
+ uint32_t ulLR ) PRIVILEGED_FUNCTION;
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+#if ( configENABLE_MPU == 1 )
+
+ /**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+ PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if ( configENABLE_TRUSTZONE == 1 )
+
+ /**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+ PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+ /**
+ * @brief The number of SysTick increments that make up one tick period.
+ */
+ PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
+
+ /**
+ * @brief The maximum number of tick periods that can be suppressed is
+ * limited by the 24 bit resolution of the SysTick timer.
+ */
+ PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
+
+ /**
+ * @brief Compensate for the CPU cycles that pass while the SysTick is
+ * stopped (low power functionality only).
+ */
+ PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+ __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+ {
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
+ TickType_t xModifiableIdleTime;
+
+ /* Make sure the SysTick reload value does not overflow the counter. */
+ if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+ {
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+ }
+
+ /* Enter a critical section but don't use the taskENTER_CRITICAL()
+ * method as that will mask interrupts that should exit sleep mode. */
+ __asm volatile ( "cpsid i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* If a context switch is pending or a task is waiting for the scheduler
+ * to be unsuspended then abandon the low power entry. */
+ if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+ {
+ /* Re-enable interrupts - see comments above the cpsid instruction
+ * above. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ }
+ else
+ {
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
+ /* Set the new reload value. */
+ portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+ /* Clear the SysTick count flag and set the count value back to
+ * zero. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Restart SysTick. */
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+ * set its parameter to 0 to indicate that its implementation contains
+ * its own wait for interrupt or wait for event instruction, and so wfi
+ * should not be executed again. However, the original expected idle
+ * time variable must remain unmodified, so a copy is taken. */
+ xModifiableIdleTime = xExpectedIdleTime;
+ configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+ if( xModifiableIdleTime > 0 )
+ {
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "wfi" );
+ __asm volatile ( "isb" );
+ }
+
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+ /* Re-enable interrupts to allow the interrupt that brought the MCU
+ * out of sleep mode to execute immediately. See comments above
+ * the cpsid instruction above. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* Disable interrupts again because the clock is about to be stopped
+ * and interrupts that execute while the clock is stopped will increase
+ * any slippage between the time maintained by the RTOS and calendar
+ * time. */
+ __asm volatile ( "cpsid i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* Disable the SysTick clock without reading the
+ * portNVIC_SYSTICK_CTRL_REG register to ensure the
+ * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
+ * the time the SysTick is stopped for is accounted for as best it can
+ * be, but using the tickless mode will inevitably result in some tiny
+ * drift of the time maintained by the kernel with respect to calendar
+ * time*/
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Determine whether the SysTick has already counted to zero. */
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ uint32_t ulCalculatedLoadValue;
+
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+ /* Don't allow a tiny value, or values that have somehow
+ * underflowed because the post sleep hook did something
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ {
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+ /* As the pending tick will be processed as soon as this
+ * function exits, the tick value maintained by the tick is stepped
+ * forward by one less than the time spent waiting. */
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+ }
+ else
+ {
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
+ * periods (not the ulReload value which accounted for part
+ * ticks). */
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
+
+ /* How many complete tick periods passed while the processor
+ * was waiting? */
+ ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+ /* The reload value is set to whatever fraction of a single tick
+ * period remains. */
+ portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+ }
+
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
+ vTaskStepTick( ulCompleteTickPeriods );
+
+ /* Exit with interrupts enabled. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ }
+ }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Calculate the constants required to configure the tick interrupt. */
+ #if ( configUSE_TICKLESS_IDLE == 1 )
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
+ #endif /* configUSE_TICKLESS_IDLE */
+
+ /* Stop and reset SysTick.
+ *
+ * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+ * enable SysTick without first selecting a valid clock source. We trigger
+ * the bug if we change clock sources from a clock with a zero clock period
+ * to one with a nonzero clock period and enable Systick at the same time.
+ * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+ * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+ volatile uint32_t ulDummy = 0UL;
+
+ /* A function that implements a task must not exit or attempt to return to
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()
+ * to be triggered if configASSERT() is defined, then stop here so
+ * application writers can catch the error. */
+ configASSERT( ulCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+
+ while( ulDummy == 0 )
+ {
+ /* This file calls prvTaskExitError() after the scheduler has been
+ * started to remove a compiler warning about the function being
+ * defined but never called. ulDummy is used purely to quieten other
+ * warnings about code appearing after this function is called - making
+ * ulDummy volatile makes the compiler think the function could return
+ * and therefore not output an 'unreachable code' warning for code that
+ * appears after it. */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulAccessPermissions = 0;
+
+ if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY )
+ {
+ ulAccessPermissions = tskMPU_READ_PERMISSION;
+ }
+
+ if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE )
+ {
+ ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION );
+ }
+
+ return ulAccessPermissions;
+ }
+
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_functions_start__;
+ extern uint32_t * __privileged_functions_end__;
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ extern uint32_t * __unprivileged_flash_start__;
+ extern uint32_t * __unprivileged_flash_end__;
+ extern uint32_t * __privileged_sram_start__;
+ extern uint32_t * __privileged_sram_end__;
+ #else /* if defined( __ARMCC_VERSION ) */
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_functions_start__[];
+ extern uint32_t __privileged_functions_end__[];
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ extern uint32_t __unprivileged_flash_start__[];
+ extern uint32_t __unprivileged_flash_end__[];
+ extern uint32_t __privileged_sram_start__[];
+ extern uint32_t __privileged_sram_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+
+ /* The only permitted number of regions are 8 or 16. */
+ configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
+
+ /* MAIR0 - Index 0. */
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ /* MAIR0 - Index 1. */
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* Setup privileged flash as Read Only so that privileged tasks can
+ * read it but not modify. */
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged flash as Read Only by both privileged and
+ * unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged syscalls flash as Read Only by both privileged
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup RAM containing kernel data for privileged access only. */
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Enable mem fault. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
+
+ /* Enable MPU with privileged background access i.e. unmapped
+ * regions have privileged access. */
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
+ }
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_FPU == 1 )
+
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ /* Enable non-secure access to the FPU. */
+ SecureInit_EnableNSFPUAccess();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+ * unprivileged code should be able to access FPU. CP11 should be
+ * programmed to the same value as CP10. */
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+ );
+
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+ * context on exception entry and restore on exception return.
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+ }
+
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Set a PendSV to request a context switch. */
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ portDISABLE_INTERRUPTS();
+ ulCriticalNesting++;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ configASSERT( ulCriticalNesting );
+ ulCriticalNesting--;
+
+ if( ulCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+ uint32_t ulPreviousMask;
+
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ traceISR_EXIT_TO_SCHEDULER();
+ /* Pend a context switch. */
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+ }
+ else
+ {
+ traceISR_EXIT();
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ uint32_t ulPC;
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ uint32_t ulR0, ulR1;
+ extern TaskHandle_t pxCurrentTCB;
+ #if ( configENABLE_MPU == 1 )
+ uint32_t ulControl, ulIsTaskPrivileged;
+ #endif /* configENABLE_MPU */
+ #endif /* configENABLE_TRUSTZONE */
+ uint8_t ucSVCNumber;
+
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+ * R12, LR, PC, xPSR. */
+ ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ];
+ ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+ switch( ucSVCNumber )
+ {
+ #if ( configENABLE_TRUSTZONE == 1 )
+ case portSVC_ALLOCATE_SECURE_CONTEXT:
+
+ /* R0 contains the stack size passed as parameter to the
+ * vPortAllocateSecureContext function. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+
+ #if ( configENABLE_MPU == 1 )
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+ }
+ #else /* if ( configENABLE_MPU == 1 ) */
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+ }
+ #endif /* configENABLE_MPU */
+
+ configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+ SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+ break;
+
+ case portSVC_FREE_SECURE_CONTEXT:
+
+ /* R0 contains TCB being freed and R1 contains the secure
+ * context handle to be freed. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+ ulR1 = pulCallerStackAddress[ 1 ];
+
+ /* Free the secure context. */
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+ break;
+ #endif /* configENABLE_TRUSTZONE */
+
+ case portSVC_START_SCHEDULER:
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
+
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ #if ( configENABLE_FPU == 1 )
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
+ #endif /* configENABLE_FPU */
+
+ /* Setup the context of the first task so that the first task starts
+ * executing. */
+ vRestoreContextOfFirstTask();
+ break;
+
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ case portSVC_RAISE_PRIVILEGE:
+
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ vRaisePrivilege();
+ }
+ break;
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ #if ( configENABLE_MPU == 1 )
+ case portSVC_YIELD:
+ vPortYield();
+ break;
+ #endif /* configENABLE_MPU == 1 */
+
+ default:
+ /* Incorrect SVC call. */
+ configASSERT( pdFALSE );
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ void vSystemCallEnter( uint32_t * pulTaskStack,
+ uint32_t ulLR,
+ uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
+ {
+ extern TaskHandle_t pxCurrentTCB;
+ extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
+ xMPU_SETTINGS * pxMpuSettings;
+ uint32_t * pulSystemCallStack;
+ uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
+
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ #endif /* #if defined( __ARMCC_VERSION ) */
+
+ ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+ pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+
+ /* Checks:
+ * 1. SVC is raised from the system call section (i.e. application is
+ * not raising SVC directly).
+ * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+ * it is non-NULL only during the execution of a system call (i.e.
+ * between system call enter and exit).
+ * 3. System call is not for a kernel API disabled by the configuration
+ * in FreeRTOSConfig.h.
+ * 4. We do not need to check that ucSystemCallNumber is within range
+ * because the assembly SVC handler checks that before calling
+ * this function.
+ */
+ if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+ ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+ ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
+ {
+ pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+ /* Hardware Saved Stack Frame Size upon Exception entry:
+ * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+ * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+ */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ {
+ if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+ {
+ /* Extended frame i.e. FPU in use. */
+ ulHardwareSavedExceptionFrameSize = 26;
+ __asm volatile (
+ " vpush {s0} \n" /* Trigger lazy stacking. */
+ " vpop {s0} \n" /* Nullify the affect of the above instruction. */
+ ::: "memory"
+ );
+ }
+ else
+ {
+ /* Standard frame i.e. FPU not in use. */
+ ulHardwareSavedExceptionFrameSize = 8;
+ }
+ }
+ #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ {
+ ulHardwareSavedExceptionFrameSize = 8;
+ }
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+
+ /* Make space on the system call stack for the stack frame. */
+ pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
+
+ /* Copy the stack frame. */
+ for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
+ {
+ pulSystemCallStack[ i ] = pulTaskStack[ i ];
+ }
+
+ /* Store the value of the Link Register before the SVC was raised.
+ * It contains the address of the caller of the System Call entry
+ * point (i.e. the caller of the MPU_<API>). We need to restore it
+ * when we exit from the system call. */
+ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
+ /* Store the value of the PSPLIM register before the SVC was raised.
+ * We need to restore it when we exit from the system call. */
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
+
+ /* Use the pulSystemCallStack in thread mode. */
+ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ }
+ #endif
+
+ /* Start executing the system call upon returning from this handler. */
+ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
+ /* Raise a request to exit from the system call upon finishing the
+ * system call. */
+ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
+ /* Remember the location where we should copy the stack frame when we exit from
+ * the system call. */
+ pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
+
+ /* Record if the hardware used padding to force the stack pointer
+ * to be double word aligned. */
+ if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+ {
+ pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
+ }
+ else
+ {
+ pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
+ }
+
+ /* We ensure in pxPortInitialiseStack that the system call stack is
+ * double word aligned and therefore, there is no need of padding.
+ * Clear the bit[9] of stacked xPSR. */
+ pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+ /* Raise the privilege for the duration of the system call. */
+ __asm volatile (
+ " mrs r0, control \n" /* Obtain current control value. */
+ " movs r1, #1 \n" /* r1 = 1. */
+ " bics r0, r1 \n" /* Clear nPRIV bit. */
+ " msr control, r0 \n" /* Write back new control value. */
+ ::: "r0", "r1", "memory"
+ );
+ }
+ }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
+ }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ void vSystemCallExit( uint32_t * pulSystemCallStack,
+ uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+ {
+ extern TaskHandle_t pxCurrentTCB;
+ xMPU_SETTINGS * pxMpuSettings;
+ uint32_t * pulTaskStack;
+ uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
+
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_functions_start__;
+ extern uint32_t * __privileged_functions_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_functions_start__[];
+ extern uint32_t __privileged_functions_end__[];
+ #endif /* #if defined( __ARMCC_VERSION ) */
+
+ ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+ pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+
+ /* Checks:
+ * 1. SVC is raised from the privileged code (i.e. application is not
+ * raising SVC directly). This SVC is only raised from
+ * vRequestSystemCallExit which is in the privileged code section.
+ * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+ * this means that we previously entered a system call and the
+ * application is not attempting to exit without entering a system
+ * call.
+ */
+ if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+ ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+ ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
+ {
+ pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+ /* Hardware Saved Stack Frame Size upon Exception entry:
+ * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+ * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+ */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ {
+ if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+ {
+ /* Extended frame i.e. FPU in use. */
+ ulHardwareSavedExceptionFrameSize = 26;
+ __asm volatile (
+ " vpush {s0} \n" /* Trigger lazy stacking. */
+ " vpop {s0} \n" /* Nullify the affect of the above instruction. */
+ ::: "memory"
+ );
+ }
+ else
+ {
+ /* Standard frame i.e. FPU not in use. */
+ ulHardwareSavedExceptionFrameSize = 8;
+ }
+ }
+ #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ {
+ ulHardwareSavedExceptionFrameSize = 8;
+ }
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+
+ /* Make space on the task stack for the stack frame. */
+ pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
+
+ /* Copy the stack frame. */
+ for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
+ {
+ pulTaskStack[ i ] = pulSystemCallStack[ i ];
+ }
+
+ /* Use the pulTaskStack in thread mode. */
+ __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+ /* Return to the caller of the System Call entry point (i.e. the
+ * caller of the MPU_<API>). */
+ pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+ /* Ensure that LR has a valid value.*/
+ pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+ /* Restore the PSPLIM register to what it was at the time of
+ * system call entry. */
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
+
+ /* If the hardware used padding to force the stack pointer
+ * to be double word aligned, set the stacked xPSR bit[9],
+ * otherwise clear it. */
+ if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+ {
+ pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
+ }
+ else
+ {
+ pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+ }
+
+ /* This is not NULL only for the duration of the system call. */
+ pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+ /* Drop the privilege before returning to the thread mode. */
+ __asm volatile (
+ " mrs r0, control \n" /* Obtain current control value. */
+ " movs r1, #1 \n" /* r1 = 1. */
+ " orrs r0, r1 \n" /* Set nPRIV bit. */
+ " msr control, r0 \n" /* Write back new control value. */
+ ::: "r0", "r1", "memory"
+ );
+ }
+ }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
+ {
+ BaseType_t xTaskIsPrivileged = pdFALSE;
+ const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+ if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ {
+ xTaskIsPrivileged = pdTRUE;
+ }
+
+ return xTaskIsPrivileged;
+ }
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ StackType_t * pxEndOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters,
+ BaseType_t xRunPrivileged,
+ xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulIndex = 0;
+ uint32_t ulControl = 0x0;
+
+ xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+ ulIndex++;
+
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
+ ulIndex++;
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+ ulIndex++;
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
+ ulIndex++;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Check PACBTI security feature configuration before pushing the
+ * CONTROL register's value on task's TCB. */
+ ulControl = prvConfigurePACBTI( pdFALSE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
+ if( xRunPrivileged == pdTRUE )
+ {
+ xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
+ ulIndex++;
+ }
+ else
+ {
+ xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
+ ulIndex++;
+ }
+
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+ ulIndex++;
+
+ #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+ {
+ /* Ensure that the system call stack is double word aligned. */
+ xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+ xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+ ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+ xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+ xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+ ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+ ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+ /* This is not NULL only for the duration of a system call. */
+ xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+ }
+ #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+ ulIndex++;
+ }
+ }
+ #endif /* configENABLE_PAC */
+
+ return &( xMPUSettings->ulContext[ ulIndex ] );
+ }
+
+#else /* configENABLE_MPU */
+
+ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ StackType_t * pxEndOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters ) /* PRIVILEGED_FUNCTION */
+ {
+ /* Simulate the stack frame as it would be created by a context switch
+ * interrupt. */
+ #if ( portPRELOAD_REGISTERS == 0 )
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #else /* portPRELOAD_REGISTERS */
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #endif /* portPRELOAD_REGISTERS */
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = ulTaskPacKey[ i ];
+ }
+ }
+ #endif /* configENABLE_PAC */
+
+ return pxTopOfStack;
+ }
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+ * for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * SVC_Handler and PendSV_Handler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+ {
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+ {
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * First, determine the number of priority bits available. Write to all
+ * possible bits in the priority setting for SVCall. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Check that the bits not implemented in hardware are zero in
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
+
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
+ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+ portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Set the CONTROL register value based on PACBTI security feature
+ * configuration before starting the first task. */
+ ( void ) prvConfigurePACBTI( pdTRUE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
+ #if ( configENABLE_MPU == 1 )
+ {
+ /* Setup the Memory Protection Unit (MPU). */
+ prvSetupMPU();
+ }
+ #endif /* configENABLE_MPU */
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ * here already. */
+ vPortSetupTimerInterrupt();
+
+ /* Initialize the critical nesting count ready for the first task. */
+ ulCriticalNesting = 0;
+
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+ {
+ xSchedulerRunning = pdTRUE;
+ }
+ #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
+
+ /* Start the first task. */
+ vStartFirstTask();
+
+ /* Should never get here as the tasks will now be executing. Call the task
+ * exit error function to prevent compiler warnings about a static function
+ * not being called in the case that the application writer overrides this
+ * functionality by defining configTASK_RETURN_ADDRESS. Call
+ * vTaskSwitchContext() so link time optimization does not remove the
+ * symbol. */
+ vTaskSwitchContext();
+ prvTaskExitError();
+
+ /* Should not get here. */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Not implemented in ports where there is nothing to return to.
+ * Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+ const struct xMEMORY_REGION * const xRegions,
+ StackType_t * pxBottomOfStack,
+ configSTACK_DEPTH_TYPE uxStackDepth )
+ {
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+ int32_t lIndex = 0;
+
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_sram_start__;
+ extern uint32_t * __privileged_sram_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_sram_start__[];
+ extern uint32_t __privileged_sram_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+
+ /* Setup MAIR0. */
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* This function is called automatically when the task is created - in
+ * which case the stack region parameters will be valid. At all other
+ * times the stack parameters will not be valid and it is assumed that
+ * the stack region has already been configured. */
+ if( uxStackDepth > 0 )
+ {
+ ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
+
+ /* If the stack is within the privileged SRAM, do not protect it
+ * using a separate MPU region. This is needed because privileged
+ * SRAM is already protected using an MPU region and ARMv8-M does
+ * not allow overlapping MPU regions. */
+ if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+ ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
+ {
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
+ }
+ else
+ {
+ /* Define the region that allows access to the stack. */
+ ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+ }
+ }
+
+ /* User supplied configurable regions. */
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+ {
+ /* If xRegions is NULL i.e. the task has not specified any MPU
+ * region, the else part ensures that all the configurable MPU
+ * regions are invalidated. */
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+ {
+ /* Translate the generic region definition contained in xRegions
+ * into the ARMv8 specific MPU settings that are then stored in
+ * xMPUSettings. */
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ /* Start address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE );
+
+ /* RO/RW. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+ }
+ else
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+ }
+
+ /* XN. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+ }
+
+ /* End Address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* PXN. */
+ #if ( portARMV8M_MINOR_VERSION >= 1 )
+ {
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+ }
+ }
+ #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
+ /* Normal memory/ Device memory. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+ {
+ /* Attr1 in MAIR0 is configured as device memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+ }
+ else
+ {
+ /* Attr0 in MAIR0 is configured as normal memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+ }
+ }
+ else
+ {
+ /* Invalidate the region. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+ }
+
+ lIndex++;
+ }
+ }
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
+ uint32_t ulBufferLength,
+ uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
+
+ {
+ uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
+ BaseType_t xAccessGranted = pdFALSE;
+ const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ {
+ xAccessGranted = pdTRUE;
+ }
+ else
+ {
+ if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
+ {
+ ulBufferStartAddress = ( uint32_t ) pvBuffer;
+ ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
+
+ for( i = 0; i < portTOTAL_NUM_REGIONS; i++ )
+ {
+ /* Is the MPU region enabled? */
+ if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE )
+ {
+ if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
+ portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ),
+ portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) &&
+ portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
+ portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ),
+ portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) &&
+ portIS_AUTHORIZED( ulAccessRequested,
+ prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) )
+ {
+ xAccessGranted = pdTRUE;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ return xAccessGranted;
+ }
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortIsInsideInterrupt( void )
+{
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
+
+ /* Obtain the number of the currently executing interrupt. Interrupt Program
+ * Status Register (IPSR) holds the exception number of the currently-executing
+ * exception or zero for Thread mode.*/
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ if( ulCurrentInterrupt == 0 )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+ void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+ int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+ xMPU_SETTINGS * xTaskMpuSettings;
+
+ ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+ ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+ xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+ xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+ }
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+ void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+ int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+ xMPU_SETTINGS * xTaskMpuSettings;
+
+ ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+ ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+ xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+ xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+ }
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+ BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+ BaseType_t xAccessGranted = pdFALSE;
+ const xMPU_SETTINGS * xTaskMpuSettings;
+
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else
+ {
+ xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+ ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+ ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+ if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ {
+ xAccessGranted = pdTRUE;
+ }
+ else
+ {
+ if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+ {
+ xAccessGranted = pdTRUE;
+ }
+ }
+ }
+
+ return xAccessGranted;
+ }
+
+ #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+ BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+ {
+ ( void ) lInternalIndexOfKernelObject;
+
+ /* If Access Control List feature is not used, all the tasks have
+ * access to all the kernel objects. */
+ return pdTRUE;
+ }
+
+ #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+ {
+ uint32_t ulControl = 0x0;
+
+ /* Ensure that PACBTI is implemented. */
+ configASSERT( portID_ISAR5_REG != 0x0 );
+
+ /* Enable UsageFault exception. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+ }
+ #endif
+
+ #if ( configENABLE_BTI == 1 )
+ {
+ ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+ }
+ #endif
+
+ if( xWriteControlRegister == pdTRUE )
+ {
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+ }
+
+ return ulControl;
+ }
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM52/non_secure/portasm.c b/portable/GCC/ARM_CM52/non_secure/portasm.c
new file mode 100644
index 0000000..0ebbe48
--- /dev/null
+++ b/portable/GCC/ARM_CM52/non_secure/portasm.c
@@ -0,0 +1,621 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if ( configENABLE_MPU == 1 )
+
+ void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " program_mpu_first_task: \n"
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r0, [r3] \n" /* r0 = pxCurrentTCB. */
+ " \n"
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
+ " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+ " str r2, [r1] \n" /* Disable MPU. */
+ " \n"
+ " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+ " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+ " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r1, [r2] \n" /* Program MAIR0. */
+ " \n"
+ " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+ " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " \n"
+ " movs r3, #4 \n" /* r3 = 4. */
+ " str r3, [r1] \n" /* Program RNR = 4. */
+ " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " \n"
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ " movs r3, #8 \n" /* r3 = 8. */
+ " str r3, [r1] \n" /* Program RNR = 8. */
+ " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " movs r3, #12 \n" /* r3 = 12. */
+ " str r3, [r1] \n" /* Program RNR = 12. */
+ " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ #endif /* configTOTAL_MPU_REGIONS == 16 */
+ " \n"
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
+ " orr r2, #1 \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
+ " str r2, [r1] \n" /* Enable MPU. */
+ " dsb \n" /* Force memory writes before continuing. */
+ " \n"
+ " restore_context_first_task: \n"
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/
+ " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */
+ " \n"
+ " restore_special_regs_first_task: \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */
+ " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_1, r4 \n"
+ " msr PAC_KEY_P_2, r5 \n"
+ " msr PAC_KEY_P_3, r6 \n"
+ " clrm {r3-r6} \n" /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+ " ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
+ " msr psp, r3 \n"
+ " msr psplim, r4 \n"
+ " msr control, r5 \n"
+ " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " str r0, [r4] \n" /* Restore xSecureContext. */
+ " \n"
+ " restore_general_regs_first_task: \n"
+ " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */
+ " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */
+ " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */
+ " \n"
+ " restore_context_done_first_task: \n"
+ " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
+ " bx lr \n"
+ );
+ }
+
+#else /* configENABLE_MPU */
+
+ void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, [r2] \n" /* Read pxCurrentTCB. */
+ " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+ " \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */
+ " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_2, r2 \n"
+ " msr PAC_KEY_P_1, r3 \n"
+ " msr PAC_KEY_P_0, r4 \n"
+ " clrm {r1-r4} \n" /* Clear r1-r4. */
+ #endif /* configENABLE_PAC */
+ " \n"
+ " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+ " ldr r4, =xSecureContext \n"
+ " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */
+ " msr psplim, r2 \n" /* Set this task's PSPLIM value. */
+ " mrs r1, control \n" /* Obtain current control register value. */
+ " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
+ " msr control, r1 \n" /* Write back the new control register value. */
+ " adds r0, #32 \n" /* Discard everything up to r0. */
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
+ " bx r3 \n" /* Finally, branch to EXC_RETURN. */
+ );
+ }
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n" /* r0 = CONTROL. */
+ " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ " ite ne \n"
+ " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ " bx lr \n" /* Return. */
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n" /* Read the CONTROL register. */
+ " bic r0, #1 \n" /* Clear the bit 0. */
+ " msr control, r0 \n" /* Write back the new CONTROL value. */
+ " bx lr \n" /* Return to the caller. */
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n" /* r0 = CONTROL. */
+ " orr r0, #1 \n" /* r0 = r0 | 1. */
+ " msr control, r0 \n" /* CONTROL = r0. */
+ " bx lr \n" /* Return to the caller. */
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
+ " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
+ " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
+ " cpsie i \n" /* Globally enable interrupts. */
+ " cpsie f \n"
+ " dsb \n"
+ " isb \n"
+ " svc %0 \n" /* System call to start the first task. */
+ " nop \n"
+ ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */
+ " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bx lr \n" /* Return. */
+ ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " msr basepri, r0 \n" /* basepri = ulMask. */
+ " dsb \n"
+ " isb \n"
+ " bx lr \n" /* Return. */
+ ::: "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern SecureContext_SaveContext \n"
+ " .extern SecureContext_LoadContext \n"
+ " \n"
+ " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+ " ldr r2, [r1] \n" /* r2 = Location in TCB where the context should be saved. */
+ " \n"
+ " cbz r0, save_ns_context \n" /* No secure context to save. */
+ " save_s_context: \n"
+ " push {r0-r2, lr} \n"
+ " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r0-r2, lr} \n"
+ " \n"
+ " save_ns_context: \n"
+ " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */
+ " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bmi save_special_regs \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+ " \n"
+ " save_general_regs: \n"
+ " mrs r3, psp \n"
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */
+ " tst lr, #0x10 \n"
+ " ittt eq \n"
+ " vstmiaeq r2!, {s16-s31} \n" /* Store s16-s31. */
+ " vldmiaeq r3, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */
+ " vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */
+ " sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+ " stmia r2!, {r4-r11} \n" /* Store r4-r11. */
+ " ldmia r3, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */
+ " stmia r2!, {r4-r11} \n" /* Store the hardware saved context. */
+ " \n"
+ " save_special_regs: \n"
+ " mrs r3, psp \n" /* r3 = PSP. */
+ " mrs r4, psplim \n" /* r4 = PSPLIM. */
+ " mrs r5, control \n" /* r5 = CONTROL. */
+ " stmia r2!, {r0, r3-r5, lr} \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+ #if ( configENABLE_PAC == 1 )
+ " mrs r3, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */
+ " mrs r4, PAC_KEY_P_1 \n"
+ " mrs r5, PAC_KEY_P_2 \n"
+ " mrs r6, PAC_KEY_P_3 \n"
+ " stmia r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the task's context. */
+ " clrm {r3-r6} \n" /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+ " str r2, [r1] \n" /* Save the location from where the context should be restored as the first member of TCB. */
+ " \n"
+ " select_next_task: \n"
+ " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n" /* r0 = 0. */
+ " msr basepri, r0 \n" /* Enable interrupts. */
+ " \n"
+ " program_mpu: \n"
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
+ " \n"
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
+ " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+ " str r2, [r1] \n" /* Disable MPU. */
+ " \n"
+ " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+ " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+ " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r1, [r2] \n" /* Program MAIR0. */
+ " \n"
+ " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+ " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " \n"
+ " movs r3, #4 \n" /* r3 = 4. */
+ " str r3, [r1] \n" /* Program RNR = 4. */
+ " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " \n"
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ " movs r3, #8 \n" /* r3 = 8. */
+ " str r3, [r1] \n" /* Program RNR = 8. */
+ " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " movs r3, #12 \n" /* r3 = 12. */
+ " str r3, [r1] \n" /* Program RNR = 12. */
+ " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ #endif /* configTOTAL_MPU_REGIONS == 16 */
+ " \n"
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
+ " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+ " str r2, [r1] \n" /* Enable MPU. */
+ " dsb \n" /* Force memory writes before continuing. */
+ " \n"
+ " restore_context: \n"
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/
+ " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */
+ " \n"
+ " restore_special_regs: \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */
+ " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_1, r4 \n"
+ " msr PAC_KEY_P_2, r5 \n"
+ " msr PAC_KEY_P_3, r6 \n"
+ " clrm {r3-r6} \n" /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+ " ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
+ " msr psp, r3 \n"
+ " msr psplim, r4 \n"
+ " msr control, r5 \n"
+ " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " str r0, [r4] \n" /* Restore xSecureContext. */
+ " cbz r0, restore_ns_context \n" /* No secure context to restore. */
+ " \n"
+ " restore_s_context: \n"
+ " push {r1-r3, lr} \n"
+ " bl SecureContext_LoadContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r1-r3, lr} \n"
+ " \n"
+ " restore_ns_context: \n"
+ " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */
+ " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+ " \n"
+ " restore_general_regs: \n"
+ " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */
+ " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */
+ " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " tst lr, #0x10 \n"
+ " ittt eq \n"
+ " vldmdbeq r2!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */
+ " vstmiaeq r3!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */
+ " vldmdbeq r2!, {s16-s31} \n" /* Restore s16-s31. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+ " \n"
+ " restore_context_done: \n"
+ " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */
+ " bx lr \n"
+ ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+ );
+ }
+
+#else /* configENABLE_MPU */
+
+ void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern SecureContext_SaveContext \n"
+ " .extern SecureContext_LoadContext \n"
+ " \n"
+ " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+ " mrs r2, psp \n" /* Read PSP in r2. */
+ " \n"
+ " cbz r0, save_ns_context \n" /* No secure context to save. */
+ " save_s_context: \n"
+ " push {r0-r2, lr} \n"
+ " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r0-r2, lr} \n"
+ " \n"
+ " save_ns_context: \n"
+ " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */
+ " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bmi save_special_regs \n" /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */
+ " \n"
+ " save_general_regs: \n"
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+ " stmdb r2!, {r4-r11} \n" /* Store the registers that are not saved automatically. */
+ " \n"
+ " save_special_regs: \n"
+ " mrs r3, psplim \n" /* r3 = PSPLIM. */
+ " stmdb r2!, {r0, r3, lr} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+ #if ( configENABLE_PAC == 1 )
+ " mrs r3, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */
+ " mrs r4, PAC_KEY_P_2 \n"
+ " mrs r5, PAC_KEY_P_1 \n"
+ " mrs r6, PAC_KEY_P_0 \n"
+ " stmdb r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the stack. */
+ " clrm {r3-r6} \n" /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+ " \n"
+ " str r2, [r1] \n" /* Save the new top of stack in TCB. */
+ " \n"
+ " select_next_task: \n"
+ " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n" /* r0 = 0. */
+ " msr basepri, r0 \n" /* Enable interrupts. */
+ " \n"
+ " restore_context: \n"
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n" /* Read pxCurrentTCB. */
+ " ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+ " \n"
+ " restore_special_regs: \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmia r2!, {r3-r6} \n" /* Read task's dedicated PAC key from stack. */
+ " msr PAC_KEY_P_3, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_2, r4 \n"
+ " msr PAC_KEY_P_1, r5 \n"
+ " msr PAC_KEY_P_0, r6 \n"
+ " clrm {r3-r6} \n" /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+ " ldmia r2!, {r0, r3, lr} \n" /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */
+ " msr psplim, r3 \n" /* Restore the PSPLIM register value for the task. */
+ " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " str r0, [r3] \n" /* Restore the task's xSecureContext. */
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */
+ " \n"
+ " restore_s_context: \n"
+ " push {r1-r3, lr} \n"
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r1-r3, lr} \n"
+ " \n"
+ " restore_ns_context: \n"
+ " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */
+ " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+ " \n"
+ " restore_general_regs: \n"
+ " ldmia r2!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+ " \n"
+ " restore_context_done: \n"
+ " msr psp, r2 \n" /* Remember the new top of stack for the task. */
+ " bx lr \n"
+ ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+ );
+ }
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile
+ (
+ ".syntax unified \n"
+ ".extern vPortSVCHandler_C \n"
+ ".extern vSystemCallEnter \n"
+ ".extern vSystemCallExit \n"
+ " \n"
+ "tst lr, #4 \n"
+ "ite eq \n"
+ "mrseq r0, msp \n"
+ "mrsne r0, psp \n"
+ " \n"
+ "ldr r1, [r0, #24] \n"
+ "ldrb r2, [r1, #-2] \n"
+ "cmp r2, %0 \n"
+ "blt syscall_enter \n"
+ "cmp r2, %1 \n"
+ "beq syscall_exit \n"
+ "b vPortSVCHandler_C \n"
+ " \n"
+ "syscall_enter: \n"
+ " mov r1, lr \n"
+ " b vSystemCallEnter \n"
+ " \n"
+ "syscall_exit: \n"
+ " mov r1, lr \n"
+ " b vSystemCallExit \n"
+ " \n"
+ : /* No outputs. */
+ : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+ : "r0", "r1", "r2", "memory"
+ );
+ }
+
+#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+ void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " tst lr, #4 \n"
+ " ite eq \n"
+ " mrseq r0, msp \n"
+ " mrsne r0, psp \n"
+ " ldr r1, =vPortSVCHandler_C \n"
+ " bx r1 \n"
+ );
+ }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " svc %0 \n" /* Secure context is allocated in the supervisor call. */
+ " bx lr \n" /* Return. */
+ ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, [r0] \n" /* The first item in the TCB is the top of the stack. */
+ " ldr r1, [r2] \n" /* The first item on the stack is the task's xSecureContext. */
+ " cmp r1, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */
+ " it ne \n"
+ " svcne %0 \n" /* Secure context is freed in the supervisor call. */
+ " bx lr \n" /* Return. */
+ ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM52/non_secure/portasm.h b/portable/GCC/ARM_CM52/non_secure/portasm.h
new file mode 100644
index 0000000..b7021b0
--- /dev/null
+++ b/portable/GCC/ARM_CM52/non_secure/portasm.h
@@ -0,0 +1,114 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kernel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/portable/GCC/ARM_CM52/non_secure/portmacro.h b/portable/GCC/ARM_CM52/non_secure/portmacro.h
new file mode 100644
index 0000000..1041a03
--- /dev/null
+++ b/portable/GCC/ARM_CM52/non_secure/portmacro.h
@@ -0,0 +1,80 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright (c) 2025 Arm Technology (China) Co., Ltd.All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_MVE
+ #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.
+#endif /* configENABLE_MVE */
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME "Cortex-M52"
+#define portHAS_ARMV8M_MAIN_EXTENSION 1
+#define portARMV8M_MINOR_VERSION 1
+#define portDONT_DISCARD __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
+/*-----------------------------------------------------------*/
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM_CM52/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM52/non_secure/portmacrocommon.h
new file mode 100644
index 0000000..f373bca
--- /dev/null
+++ b/portable/GCC/ARM_CM52/non_secure/portmacrocommon.h
@@ -0,0 +1,582 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern BaseType_t xPortIsInsideInterrupt( void );
+
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+ /**
+ * @brief Generates 128-bit task's random PAC key.
+ *
+ * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+ * filled with a 128-bit random number.
+ */
+ void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
+
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+ /* Define to 8 for backward compatibility. */
+ #define configTOTAL_MPU_REGIONS ( 8UL )
+#endif
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ * Bit[7:4] - 0000 - Device Memory
+ * Bit[3:2] - 00 --> Device-nGnRnE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
+ * Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ /**
+ * @brief Settings to define an MPU region.
+ */
+ typedef struct MPURegionSettings
+ {
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+ } MPURegionSettings_t;
+
+ #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+ #ifndef configSYSTEM_CALL_STACK_SIZE
+ #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
+ #endif
+
+ /**
+ * @brief System call stack.
+ */
+ typedef struct SYSTEM_CALL_STACK_INFO
+ {
+ uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
+ uint32_t * pulSystemCallStack;
+ uint32_t * pulSystemCallStackLimit;
+ uint32_t * pulTaskStack;
+ uint32_t ulLinkRegisterAtSystemCallEntry;
+ uint32_t ulStackLimitRegisterAtSystemCallEntry;
+ } xSYSTEM_CALL_STACK_INFO;
+
+ #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+ /**
+ * @brief MPU settings as stored in the TCB.
+ */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+ * 16 17 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 71
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ * 16 17 8 8 5 1
+ */
+ #define MAX_CONTEXT_SIZE 55
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | | | PC, xPSR | EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+ * 16 17 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 70
+
+ #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | |
+ * | | | | PC, xPSR | EXC_RETURN | |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ * 16 17 8 8 4 1
+ */
+ #define MAX_CONTEXT_SIZE 54
+
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +----------+-----------------+------------------------------+------------+-----+
+ *
+ * <---------><----------------><------------------------------><-----------><---->
+ * 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 38
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ * 8 8 5 1
+ */
+ #define MAX_CONTEXT_SIZE 22
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+----------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | PC, xPSR | EXC_RETURN | | |
+ * +----------+-----------------+----------------------+------------+-----+
+ *
+ * <---------><----------------><----------------------><-----------><---->
+ * 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 37
+
+ #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+
+ /*
+ * +----------+-----------------+----------------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | |
+ * | | PC, xPSR | EXC_RETURN | |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ * 8 8 4 1
+ */
+ #define MAX_CONTEXT_SIZE 21
+
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+
+ /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+ #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+ #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+
+ /* Size of an Access Control List (ACL) entry in bits. */
+ #define portACL_ENTRY_SIZE_BITS ( 32U )
+
+ typedef struct MPU_SETTINGS
+ {
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+ uint32_t ulContext[ MAX_CONTEXT_SIZE ];
+ uint32_t ulTaskFlags;
+
+ #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+ xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+ #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+ uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
+ #endif
+ #endif
+ } xMPU_SETTINGS;
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#if ( configASSERT_DEFINED == 1 )
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT 100
+#define portSVC_FREE_SECURE_CONTEXT 101
+#define portSVC_START_SCHEDULER 102
+#define portSVC_RAISE_PRIVILEGE 103
+#define portSVC_SYSTEM_CALL_EXIT 104
+#define portSVC_YIELD 105
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#if ( configENABLE_MPU == 1 )
+ #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() vPortYield()
+#else
+ #define portYIELD() vPortYield()
+ #define portYIELD_WITHIN_API() vPortYield()
+#endif
+
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ extern BaseType_t xPortIsTaskPrivileged( void );
+
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #else
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+ #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+ static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint32_t ulReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ulReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+ #endif
+
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+ #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+ #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACROCOMMON_H */
diff --git a/portable/GCC/ARM_CM52/secure/secure_context.c b/portable/GCC/ARM_CM52/secure/secure_context.c
new file mode 100644
index 0000000..3aa335e
--- /dev/null
+++ b/portable/GCC/ARM_CM52/secure/secure_context.c
@@ -0,0 +1,354 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED 0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03
+
+/**
+ * @brief Size of stack seal values in bytes.
+ */
+#define securecontextSTACK_SEAL_SIZE 8
+
+/**
+ * @brief Stack seal value as recommended by ARM.
+ */
+#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5
+
+/**
+ * @brief Maximum number of secure contexts.
+ */
+#ifndef secureconfigMAX_SECURE_CONTEXTS
+ #define secureconfigMAX_SECURE_CONTEXTS 8UL
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Pre-allocated array of secure contexts.
+ */
+SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ];
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Get a free secure context for a task from the secure context pool (xSecureContexts).
+ *
+ * This function ensures that only one secure context is allocated for a task.
+ *
+ * @param[in] pvTaskHandle The task handle for which the secure context is allocated.
+ *
+ * @return Index of a free secure context in the xSecureContexts array.
+ */
+static uint32_t ulGetSecureContext( void * pvTaskHandle );
+
+/**
+ * @brief Return the secure context to the secure context pool (xSecureContexts).
+ *
+ * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array.
+ */
+static void vReturnSecureContext( uint32_t ulSecureContextIndex );
+
+/* These are implemented in assembly. */
+extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext );
+extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext );
+/*-----------------------------------------------------------*/
+
+static uint32_t ulGetSecureContext( void * pvTaskHandle )
+{
+ /* Start with invalid index. */
+ uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
+
+ for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
+ {
+ if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) &&
+ ( xSecureContexts[ i ].pucStackLimit == NULL ) &&
+ ( xSecureContexts[ i ].pucStackStart == NULL ) &&
+ ( xSecureContexts[ i ].pvTaskHandle == NULL ) &&
+ ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) )
+ {
+ ulSecureContextIndex = i;
+ }
+ else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle )
+ {
+ /* A task can only have one secure context. Do not allocate a second
+ * context for the same task. */
+ ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
+ break;
+ }
+ }
+
+ return ulSecureContextIndex;
+}
+/*-----------------------------------------------------------*/
+
+static void vReturnSecureContext( uint32_t ulSecureContextIndex )
+{
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL;
+ xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL;
+ xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL;
+ xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+ uint32_t ulIPSR, i;
+ static uint32_t ulSecureContextsInitialized = 0;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) )
+ {
+ /* Ensure to initialize secure contexts only once. */
+ ulSecureContextsInitialized = 1;
+
+ /* No stack for thread mode until a task's context is loaded. */
+ secureportSET_PSPLIM( securecontextNO_STACK );
+ secureportSET_PSP( securecontextNO_STACK );
+
+ /* Initialize all secure contexts. */
+ for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
+ {
+ xSecureContexts[ i ].pucCurrentStackPointer = NULL;
+ xSecureContexts[ i ].pucStackLimit = NULL;
+ xSecureContexts[ i ].pucStackStart = NULL;
+ xSecureContexts[ i ].pvTaskHandle = NULL;
+ }
+
+ #if ( configENABLE_MPU == 1 )
+ {
+ /* Configure thread mode to use PSP and to be unprivileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+ }
+ #else /* configENABLE_MPU */
+ {
+ /* Configure thread mode to use PSP and to be privileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+ }
+ #endif /* configENABLE_MPU */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+ uint32_t ulIsTaskPrivileged,
+ void * pvTaskHandle )
+#else /* configENABLE_MPU */
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+ void * pvTaskHandle )
+#endif /* configENABLE_MPU */
+{
+ uint8_t * pucStackMemory = NULL;
+ uint8_t * pucStackLimit;
+ uint32_t ulIPSR, ulSecureContextIndex;
+ SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID;
+
+ #if ( configENABLE_MPU == 1 )
+ uint32_t * pulCurrentStackPointer = NULL;
+ #endif /* configENABLE_MPU */
+
+ /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit
+ * Register (PSPLIM) value. */
+ secureportREAD_IPSR( ulIPSR );
+ secureportREAD_PSPLIM( pucStackLimit );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode.
+ * Also do nothing, if a secure context us already loaded. PSPLIM is set to
+ * securecontextNO_STACK when no secure context is loaded. */
+ if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
+ {
+ /* Obtain a free secure context. */
+ ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
+
+ /* Were we able to get a free context? */
+ if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS )
+ {
+ /* Allocate the stack space. */
+ pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE );
+
+ if( pucStackMemory != NULL )
+ {
+ /* Since stack grows down, the starting point will be the last
+ * location. Note that this location is next to the last
+ * allocated byte for stack (excluding the space for seal values)
+ * because the hardware decrements the stack pointer before
+ * writing i.e. if stack pointer is 0x2, a push operation will
+ * decrement the stack pointer to 0x1 and then write at 0x1. */
+ xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
+
+ /* Seal the created secure process stack. */
+ *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+ *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+
+ /* The stack cannot go beyond this location. This value is
+ * programmed in the PSPLIM register on context switch.*/
+ xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory;
+
+ xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
+
+ #if ( configENABLE_MPU == 1 )
+ {
+ /* Store the correct CONTROL value for the task on the stack.
+ * This value is programmed in the CONTROL register on
+ * context switch. */
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ pulCurrentStackPointer--;
+
+ if( ulIsTaskPrivileged )
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+ }
+ else
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+ }
+
+ /* Store the current stack pointer. This value is programmed in
+ * the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ }
+ #else /* configENABLE_MPU */
+ {
+ /* Current SP is set to the starting of the stack. This
+ * value programmed in the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ }
+ #endif /* configENABLE_MPU */
+
+ /* Ensure to never return 0 as a valid context handle. */
+ xSecureContextHandle = ulSecureContextIndex + 1UL;
+ }
+ }
+ }
+
+ return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
+{
+ uint32_t ulIPSR, ulSecureContextIndex;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* Only free if a valid context handle is passed. */
+ if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
+ {
+ ulSecureContextIndex = xSecureContextHandle - 1UL;
+
+ /* Ensure that the secure context being deleted is associated with
+ * the task. */
+ if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle )
+ {
+ /* Free the stack space. */
+ vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit );
+
+ /* Return the secure context back to the free secure contexts pool. */
+ vReturnSecureContext( ulSecureContextIndex );
+ }
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
+{
+ uint8_t * pucStackLimit;
+ uint32_t ulSecureContextIndex;
+
+ if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
+ {
+ ulSecureContextIndex = xSecureContextHandle - 1UL;
+
+ secureportREAD_PSPLIM( pucStackLimit );
+
+ /* Ensure that no secure context is loaded and the task is loading it's
+ * own context. */
+ if( ( pucStackLimit == securecontextNO_STACK ) &&
+ ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
+ {
+ SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
+{
+ uint8_t * pucStackLimit;
+ uint32_t ulSecureContextIndex;
+
+ if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
+ {
+ ulSecureContextIndex = xSecureContextHandle - 1UL;
+
+ secureportREAD_PSPLIM( pucStackLimit );
+
+ /* Ensure that task's context is loaded and the task is saving it's own
+ * context. */
+ if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
+ ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
+ {
+ SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM52/secure/secure_context.h b/portable/GCC/ARM_CM52/secure/secure_context.h
new file mode 100644
index 0000000..e36a8e4
--- /dev/null
+++ b/portable/GCC/ARM_CM52/secure/secure_context.h
@@ -0,0 +1,138 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no secure context is loaded.
+ */
+#define securecontextNO_STACK 0x0
+
+/**
+ * @brief Invalid context ID.
+ */
+#define securecontextINVALID_CONTEXT_ID 0UL
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent a secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first address of the allocated memory.
+ */
+typedef struct SecureContext
+{
+ uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
+ uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */
+ uint8_t * pucStackStart; /**< First location of the stack memory. */
+ void * pvTaskHandle; /**< Task handle of the task this context is associated with. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Opaque handle for a secure context.
+ */
+typedef uint32_t SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if ( configENABLE_MPU == 1 )
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+ uint32_t ulIsTaskPrivileged,
+ void * pvTaskHandle );
+#else /* configENABLE_MPU */
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+ void * pvTaskHandle );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/portable/GCC/ARM_CM52/secure/secure_context_port.c b/portable/GCC/ARM_CM52/secure/secure_context_port.c
new file mode 100644
index 0000000..2d3d943
--- /dev/null
+++ b/portable/GCC/ARM_CM52/secure/secure_context_port.c
@@ -0,0 +1,97 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
+void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
+
+void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )
+{
+ /* pxSecureContext value is in r0. */
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r1, ipsr \n" /* r1 = IPSR. */
+ " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
+ " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+ " msr control, r3 \n" /* CONTROL = r3. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " msr psplim, r2 \n" /* PSPLIM = r2. */
+ " msr psp, r1 \n" /* PSP = r1. */
+ " \n"
+ " load_ctx_therad_mode: \n"
+ " bx lr \n"
+ " \n"
+ ::: "r0", "r1", "r2"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )
+{
+ /* pxSecureContext value is in r0. */
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r1, ipsr \n" /* r1 = IPSR. */
+ " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
+ " mrs r1, psp \n" /* r1 = PSP. */
+ " \n"
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " vstmdb r1!, {s0} \n" /* Trigger the deferred stacking of FPU registers. */
+ " vldmia r1!, {s0} \n" /* Nullify the effect of the previous statement. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " mrs r2, control \n" /* r2 = CONTROL. */
+ " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
+ " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */
+ " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */
+ " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+ " \n"
+ " save_ctx_therad_mode: \n"
+ " bx lr \n"
+ " \n"
+ ::"i" ( securecontextNO_STACK ) : "r1", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM52/secure/secure_heap.c b/portable/GCC/ARM_CM52/secure/secure_heap.c
new file mode 100644
index 0000000..896b53e
--- /dev/null
+++ b/portable/GCC/ARM_CM52/secure/secure_heap.c
@@ -0,0 +1,485 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Configuration includes. */
+#include "FreeRTOSConfig.h"
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#ifndef secureconfigTOTAL_HEAP_SIZE
+ #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )
+#endif
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+ #define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+ #define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+ #define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block. When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) )
+#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK )
+#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
+
+/* The application writer has already defined the array used for the RTOS
+* heap - probably so it can be placed in a special segment or address. */
+ extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+ static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+ struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */
+ size_t xBlockSize; /**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart;
+static BlockLink_t * pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+ BlockLink_t * pxFirstFreeBlock;
+ uint8_t * pucAlignedHeap;
+ size_t uxAddress;
+ size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+ /* Ensure the heap starts on a correctly aligned boundary. */
+ uxAddress = ( size_t ) ucHeap;
+
+ if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+ {
+ uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+ xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+ }
+
+ pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+ /* xStart is used to hold a pointer to the first item in the list of free
+ * blocks. The void cast is used to prevent compiler warnings. */
+ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+ xStart.xBlockSize = ( size_t ) 0;
+
+ /* pxEnd is used to mark the end of the list of free blocks and is inserted
+ * at the end of the heap space. */
+ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+ uxAddress -= xHeapStructSize;
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+ pxEnd = ( void * ) uxAddress;
+ pxEnd->xBlockSize = 0;
+ pxEnd->pxNextFreeBlock = NULL;
+
+ /* To start with there is a single free block that is sized to take up the
+ * entire heap space, minus the space taken by pxEnd. */
+ pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+ pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+ pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+ /* Only one block exists - and it covers the entire usable heap space. */
+ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+ xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
+{
+ BlockLink_t * pxIterator;
+ uint8_t * puc;
+
+ /* Iterate through the list until a block is found that has a higher address
+ * than the block being inserted. */
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+ {
+ /* Nothing to do here, just iterate to the right position. */
+ }
+
+ /* Do the block being inserted, and the block it is being inserted after
+ * make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxIterator;
+
+ if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+ {
+ pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+ pxBlockToInsert = pxIterator;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Do the block being inserted, and the block it is being inserted before
+ * make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxBlockToInsert;
+
+ if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+ {
+ if( pxIterator->pxNextFreeBlock != pxEnd )
+ {
+ /* Form one big block from the two blocks. */
+ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxEnd;
+ }
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+ }
+
+ /* If the block being inserted plugged a gap, so was merged with the block
+ * before and the block after, then it's pxNextFreeBlock pointer will have
+ * already been set, and should not be set here as that would make it point
+ * to itself. */
+ if( pxIterator != pxBlockToInsert )
+ {
+ pxIterator->pxNextFreeBlock = pxBlockToInsert;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void * pvPortMalloc( size_t xWantedSize )
+{
+ BlockLink_t * pxBlock;
+ BlockLink_t * pxPreviousBlock;
+ BlockLink_t * pxNewBlockLink;
+ void * pvReturn = NULL;
+ size_t xAdditionalRequiredSize;
+ size_t xAllocatedBlockSize = 0;
+
+ /* If this is the first call to malloc then the heap will require
+ * initialisation to setup the list of free blocks. */
+ if( pxEnd == NULL )
+ {
+ prvHeapInit();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( xWantedSize > 0 )
+ {
+ /* The wanted size must be increased so it can contain a BlockLink_t
+ * structure in addition to the requested amount of bytes. */
+ if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
+ {
+ xWantedSize += xHeapStructSize;
+
+ /* Ensure that blocks are always aligned to the required number
+ * of bytes. */
+ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+ {
+ /* Byte alignment required. */
+ xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK );
+
+ if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+ {
+ xWantedSize += xAdditionalRequiredSize;
+ }
+ else
+ {
+ xWantedSize = 0;
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ xWantedSize = 0;
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Check the requested block size is not so large that the top bit is set.
+ * The top bit of the block size member of the BlockLink_t structure is used
+ * to determine who owns the block - the application or the kernel, so it
+ * must be free. */
+ if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+ {
+ if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+ {
+ /* Traverse the list from the start (lowest address) block until
+ * one of adequate size is found. */
+ pxPreviousBlock = &xStart;
+ pxBlock = xStart.pxNextFreeBlock;
+
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+ {
+ pxPreviousBlock = pxBlock;
+ pxBlock = pxBlock->pxNextFreeBlock;
+ }
+
+ /* If the end marker was reached then a block of adequate size was
+ * not found. */
+ if( pxBlock != pxEnd )
+ {
+ /* Return the memory space pointed to - jumping over the
+ * BlockLink_t structure at its start. */
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+ /* This block is being returned for use so must be taken out
+ * of the list of free blocks. */
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+ /* If the block is larger than required it can be split into
+ * two. */
+ if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+ {
+ /* This block is to be split into two. Create a new
+ * block following the number of bytes requested. The void
+ * cast is used to prevent byte alignment warnings from the
+ * compiler. */
+ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+ secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+ /* Calculate the sizes of two blocks split from the single
+ * block. */
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+ pxBlock->xBlockSize = xWantedSize;
+
+ /* Insert the new block into the list of free blocks. */
+ pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+ pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+ if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+ {
+ xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ xAllocatedBlockSize = pxBlock->xBlockSize;
+
+ /* The block is being returned - it is allocated and owned by
+ * the application and has no "next" block. */
+ secureheapALLOCATE_BLOCK( pxBlock );
+ pxBlock->pxNextFreeBlock = NULL;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+ /* Prevent compiler warnings when trace macros are not used. */
+ ( void ) xAllocatedBlockSize;
+
+ #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
+ {
+ extern void vApplicationMallocFailedHook( void );
+ vApplicationMallocFailedHook();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
+
+ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void * pv )
+{
+ uint8_t * puc = ( uint8_t * ) pv;
+ BlockLink_t * pxLink;
+
+ if( pv != NULL )
+ {
+ /* The memory being freed will have an BlockLink_t structure immediately
+ * before it. */
+ puc -= xHeapStructSize;
+
+ /* This casting is to keep the compiler from issuing warnings. */
+ pxLink = ( void * ) puc;
+
+ /* Check the block is actually allocated. */
+ secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
+ secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+ if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
+ {
+ if( pxLink->pxNextFreeBlock == NULL )
+ {
+ /* The block is being returned to the heap - it is no longer
+ * allocated. */
+ secureheapFREE_BLOCK( pxLink );
+
+ secureportDISABLE_NON_SECURE_INTERRUPTS();
+ {
+ /* Add this block to the list of free blocks. */
+ xFreeBytesRemaining += pxLink->xBlockSize;
+ traceFREE( pv, pxLink->xBlockSize );
+ prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+ }
+ secureportENABLE_NON_SECURE_INTERRUPTS();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+ return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+ return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM52/secure/secure_heap.h b/portable/GCC/ARM_CM52/secure/secure_heap.h
new file mode 100644
index 0000000..0e84a9d
--- /dev/null
+++ b/portable/GCC/ARM_CM52/secure/secure_heap.h
@@ -0,0 +1,66 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void * pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void * pv );
+
+/**
+ * @brief Get the free heap size.
+ *
+ * @return Free heap size.
+ */
+size_t xPortGetFreeHeapSize( void );
+
+/**
+ * @brief Get the minimum ever free heap size.
+ *
+ * @return Minimum ever free heap size.
+ */
+size_t xPortGetMinimumEverFreeHeapSize( void );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/portable/GCC/ARM_CM52/secure/secure_init.c b/portable/GCC/ARM_CM52/secure/secure_init.c
new file mode 100644
index 0000000..c50d376
--- /dev/null
+++ b/portable/GCC/ARM_CM52/secure/secure_init.c
@@ -0,0 +1,106 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS ( 29UL )
+#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS ( 26UL )
+#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS ( 10UL )
+#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS ( 11UL )
+#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+ ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+ ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
+ }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+ * permitted. CP11 should be programmed to the same value as CP10. */
+ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+ /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
+ * that we can enable/disable lazy stacking in port.c file. */
+ *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
+
+ /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+ * registers (S16-S31) are also pushed to stack on exception entry and
+ * restored on exception return. */
+ *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+ }
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM52/secure/secure_init.h b/portable/GCC/ARM_CM52/secure/secure_init.h
new file mode 100644
index 0000000..ebe0490
--- /dev/null
+++ b/portable/GCC/ARM_CM52/secure/secure_init.h
@@ -0,0 +1,54 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/portable/GCC/ARM_CM52/secure/secure_port_macros.h b/portable/GCC/ARM_CM52/secure/secure_port_macros.h
new file mode 100644
index 0000000..a70da2c
--- /dev/null
+++ b/portable/GCC/ARM_CM52/secure/secure_port_macros.h
@@ -0,0 +1,140 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT 8
+#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root
+#else
+ #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+ __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+ __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+ __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+ __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Read the PSPLIM value in the given variable.
+ */
+#define secureportREAD_PSPLIM( pucOutStackLimit ) \
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+ __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+ __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x ) \
+ if( ( x ) == 0 ) \
+ { \
+ secureportDISABLE_SECURE_INTERRUPTS(); \
+ secureportDISABLE_NON_SECURE_INTERRUPTS(); \
+ for( ; ; ) {; } \
+ }
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/portable/GCC/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.c
new file mode 100644
index 0000000..4b98493
--- /dev/null
+++ b/portable/GCC/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -0,0 +1,2055 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+#include "event_groups.h"
+#include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ #if ( INCLUDE_xTaskDelayUntil == 1 )
+
+ BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+ const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+ const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskDelayUntilImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskDelayUntil_Unpriv \n"
+ " MPU_xTaskDelayUntil_Priv: \n"
+ " b MPU_xTaskDelayUntilImpl \n"
+ " MPU_xTaskDelayUntil_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_xTaskAbortDelay == 1 )
+
+ BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskAbortDelayImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskAbortDelay_Unpriv \n"
+ " MPU_xTaskAbortDelay_Priv: \n"
+ " b MPU_xTaskAbortDelayImpl \n"
+ " MPU_xTaskAbortDelay_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_vTaskDelay == 1 )
+
+ void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTaskDelayImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vTaskDelay_Unpriv \n"
+ " MPU_vTaskDelay_Priv: \n"
+ " b MPU_vTaskDelayImpl \n"
+ " MPU_vTaskDelay_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+ UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxTaskPriorityGetImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_uxTaskPriorityGet_Unpriv \n"
+ " MPU_uxTaskPriorityGet_Priv: \n"
+ " b MPU_uxTaskPriorityGetImpl \n"
+ " MPU_uxTaskPriorityGet_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_eTaskGetState == 1 )
+
+ eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_eTaskGetStateImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_eTaskGetState_Unpriv \n"
+ " MPU_eTaskGetState_Priv: \n"
+ " b MPU_eTaskGetStateImpl \n"
+ " MPU_eTaskGetState_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+
+ void MPU_vTaskGetInfo( TaskHandle_t xTask,
+ TaskStatus_t * pxTaskStatus,
+ BaseType_t xGetFreeStackSpace,
+ eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTaskGetInfo( TaskHandle_t xTask,
+ TaskStatus_t * pxTaskStatus,
+ BaseType_t xGetFreeStackSpace,
+ eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTaskGetInfoImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vTaskGetInfo_Unpriv \n"
+ " MPU_vTaskGetInfo_Priv: \n"
+ " b MPU_vTaskGetInfoImpl \n"
+ " MPU_vTaskGetInfo_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+ TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGetIdleTaskHandleImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n"
+ " MPU_xTaskGetIdleTaskHandle_Priv: \n"
+ " b MPU_xTaskGetIdleTaskHandleImpl \n"
+ " MPU_xTaskGetIdleTaskHandle_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+
+ void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTaskSuspendImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vTaskSuspend_Unpriv \n"
+ " MPU_vTaskSuspend_Priv: \n"
+ " b MPU_vTaskSuspendImpl \n"
+ " MPU_vTaskSuspend_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+
+ void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTaskResumeImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vTaskResume_Unpriv \n"
+ " MPU_vTaskResume_Priv: \n"
+ " b MPU_vTaskResumeImpl \n"
+ " MPU_vTaskResume_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+/*-----------------------------------------------------------*/
+
+ TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGetTickCountImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskGetTickCount_Unpriv \n"
+ " MPU_xTaskGetTickCount_Priv: \n"
+ " b MPU_xTaskGetTickCountImpl \n"
+ " MPU_xTaskGetTickCount_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxTaskGetNumberOfTasksImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n"
+ " MPU_uxTaskGetNumberOfTasks_Priv: \n"
+ " b MPU_uxTaskGetNumberOfTasksImpl \n"
+ " MPU_uxTaskGetNumberOfTasks_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_ulTaskGetRunTimeCounterImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n"
+ " MPU_ulTaskGetRunTimeCounter_Priv: \n"
+ " b MPU_ulTaskGetRunTimeCounterImpl \n"
+ " MPU_ulTaskGetRunTimeCounter_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
+ );
+ }
+
+ #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_ulTaskGetRunTimePercentImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_ulTaskGetRunTimePercent_Unpriv \n"
+ " MPU_ulTaskGetRunTimePercent_Priv: \n"
+ " b MPU_ulTaskGetRunTimePercentImpl \n"
+ " MPU_ulTaskGetRunTimePercent_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
+ );
+ }
+
+ #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n"
+ " MPU_ulTaskGetIdleRunTimePercent_Priv: \n"
+ " b MPU_ulTaskGetIdleRunTimePercentImpl \n"
+ " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
+ );
+ }
+
+ #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n"
+ " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n"
+ " b MPU_ulTaskGetIdleRunTimeCounterImpl \n"
+ " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
+ );
+ }
+
+ #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+ void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+ TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+ TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTaskSetApplicationTaskTagImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n"
+ " MPU_vTaskSetApplicationTaskTag_Priv: \n"
+ " b MPU_vTaskSetApplicationTaskTagImpl \n"
+ " MPU_vTaskSetApplicationTaskTag_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+ TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGetApplicationTaskTagImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n"
+ " MPU_xTaskGetApplicationTaskTag_Priv: \n"
+ " b MPU_xTaskGetApplicationTaskTagImpl \n"
+ " MPU_xTaskGetApplicationTaskTag_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+ void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+ BaseType_t xIndex,
+ void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+ BaseType_t xIndex,
+ void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n"
+ " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n"
+ " b MPU_vTaskSetThreadLocalStoragePointerImpl \n"
+ " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
+ );
+ }
+
+ #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+ void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+ BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+ BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n"
+ " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n"
+ " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n"
+ " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
+ );
+ }
+
+ #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+
+ UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+ const UBaseType_t uxArraySize,
+ configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+ const UBaseType_t uxArraySize,
+ configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxTaskGetSystemStateImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_uxTaskGetSystemState_Unpriv \n"
+ " MPU_uxTaskGetSystemState_Priv: \n"
+ " b MPU_uxTaskGetSystemStateImpl \n"
+ " MPU_uxTaskGetSystemState_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+ UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n"
+ " MPU_uxTaskGetStackHighWaterMark_Priv: \n"
+ " b MPU_uxTaskGetStackHighWaterMarkImpl \n"
+ " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+
+ configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n"
+ " MPU_uxTaskGetStackHighWaterMark2_Priv: \n"
+ " b MPU_uxTaskGetStackHighWaterMark2Impl \n"
+ " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+
+ TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGetCurrentTaskHandleImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n"
+ " MPU_xTaskGetCurrentTaskHandle_Priv: \n"
+ " b MPU_xTaskGetCurrentTaskHandleImpl \n"
+ " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
+ );
+ }
+
+ #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_xTaskGetSchedulerState == 1 )
+
+ BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGetSchedulerStateImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskGetSchedulerState_Unpriv \n"
+ " MPU_xTaskGetSchedulerState_Priv: \n"
+ " b MPU_xTaskGetSchedulerStateImpl \n"
+ " MPU_xTaskGetSchedulerState_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+/*-----------------------------------------------------------*/
+
+ void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTaskSetTimeOutStateImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vTaskSetTimeOutState_Unpriv \n"
+ " MPU_vTaskSetTimeOutState_Priv: \n"
+ " b MPU_vTaskSetTimeOutStateImpl \n"
+ " MPU_vTaskSetTimeOutState_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+ TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+ TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskCheckForTimeOutImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskCheckForTimeOut_Unpriv \n"
+ " MPU_xTaskCheckForTimeOut_Priv: \n"
+ " b MPU_xTaskCheckForTimeOutImpl \n"
+ " MPU_xTaskCheckForTimeOut_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+ BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGenericNotifyImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskGenericNotify_Unpriv \n"
+ " MPU_xTaskGenericNotify_Priv: \n"
+ " b MPU_xTaskGenericNotifyImpl \n"
+ " MPU_xTaskGenericNotify_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+ BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGenericNotifyWaitImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskGenericNotifyWait_Unpriv \n"
+ " MPU_xTaskGenericNotifyWait_Priv: \n"
+ " b MPU_xTaskGenericNotifyWaitImpl \n"
+ " MPU_xTaskGenericNotifyWait_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+ uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+ BaseType_t xClearCountOnExit,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+ BaseType_t xClearCountOnExit,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_ulTaskGenericNotifyTakeImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_ulTaskGenericNotifyTake_Unpriv \n"
+ " MPU_ulTaskGenericNotifyTake_Priv: \n"
+ " b MPU_ulTaskGenericNotifyTakeImpl \n"
+ " MPU_ulTaskGenericNotifyTake_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+ BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+ UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+ UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGenericNotifyStateClearImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n"
+ " MPU_xTaskGenericNotifyStateClear_Priv: \n"
+ " b MPU_xTaskGenericNotifyStateClearImpl \n"
+ " MPU_xTaskGenericNotifyStateClear_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+ uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+ UBaseType_t uxIndexToClear,
+ uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+ UBaseType_t uxIndexToClear,
+ uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_ulTaskGenericNotifyValueClearImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n"
+ " MPU_ulTaskGenericNotifyValueClear_Priv: \n"
+ " b MPU_ulTaskGenericNotifyValueClearImpl \n"
+ " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+ const void * const pvItemToQueue,
+ TickType_t xTicksToWait,
+ const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+ const void * const pvItemToQueue,
+ TickType_t xTicksToWait,
+ const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueGenericSendImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xQueueGenericSend_Unpriv \n"
+ " MPU_xQueueGenericSend_Priv: \n"
+ " b MPU_xQueueGenericSendImpl \n"
+ " MPU_xQueueGenericSend_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxQueueMessagesWaitingImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_uxQueueMessagesWaiting_Unpriv \n"
+ " MPU_uxQueueMessagesWaiting_Priv: \n"
+ " b MPU_uxQueueMessagesWaitingImpl \n"
+ " MPU_uxQueueMessagesWaiting_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxQueueSpacesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_uxQueueSpacesAvailable_Unpriv \n"
+ " MPU_uxQueueSpacesAvailable_Priv: \n"
+ " b MPU_uxQueueSpacesAvailableImpl \n"
+ " MPU_uxQueueSpacesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+ void * const pvBuffer,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+ void * const pvBuffer,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueReceiveImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xQueueReceive_Unpriv \n"
+ " MPU_xQueueReceive_Priv: \n"
+ " b MPU_xQueueReceiveImpl \n"
+ " MPU_xQueueReceive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+ void * const pvBuffer,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+ void * const pvBuffer,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueuePeekImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xQueuePeek_Unpriv \n"
+ " MPU_xQueuePeek_Priv: \n"
+ " b MPU_xQueuePeekImpl \n"
+ " MPU_xQueuePeek_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueSemaphoreTakeImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xQueueSemaphoreTake_Unpriv \n"
+ " MPU_xQueueSemaphoreTake_Priv: \n"
+ " b MPU_xQueueSemaphoreTakeImpl \n"
+ " MPU_xQueueSemaphoreTake_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+ TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueGetMutexHolderImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xQueueGetMutexHolder_Unpriv \n"
+ " MPU_xQueueGetMutexHolder_Priv: \n"
+ " b MPU_xQueueGetMutexHolderImpl \n"
+ " MPU_xQueueGetMutexHolder_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
+ );
+ }
+
+ #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+ BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueTakeMutexRecursiveImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xQueueTakeMutexRecursive_Unpriv \n"
+ " MPU_xQueueTakeMutexRecursive_Priv: \n"
+ " b MPU_xQueueTakeMutexRecursiveImpl \n"
+ " MPU_xQueueTakeMutexRecursive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+ BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueGiveMutexRecursiveImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xQueueGiveMutexRecursive_Unpriv \n"
+ " MPU_xQueueGiveMutexRecursive_Priv: \n"
+ " b MPU_xQueueGiveMutexRecursiveImpl \n"
+ " MPU_xQueueGiveMutexRecursive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_QUEUE_SETS == 1 )
+
+ QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+ const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+ const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueSelectFromSetImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xQueueSelectFromSet_Unpriv \n"
+ " MPU_xQueueSelectFromSet_Priv: \n"
+ " b MPU_xQueueSelectFromSetImpl \n"
+ " MPU_xQueueSelectFromSet_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_QUEUE_SETS == 1 )
+
+ BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+ QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+ QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueAddToSetImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xQueueAddToSet_Unpriv \n"
+ " MPU_xQueueAddToSet_Priv: \n"
+ " b MPU_xQueueAddToSetImpl \n"
+ " MPU_xQueueAddToSet_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+ void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+ const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+ const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vQueueAddToRegistryImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vQueueAddToRegistry_Unpriv \n"
+ " MPU_vQueueAddToRegistry_Priv: \n"
+ " b MPU_vQueueAddToRegistryImpl \n"
+ " MPU_vQueueAddToRegistry_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
+ );
+ }
+
+ #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+ void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vQueueUnregisterQueueImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vQueueUnregisterQueue_Unpriv \n"
+ " MPU_vQueueUnregisterQueue_Priv: \n"
+ " b MPU_vQueueUnregisterQueueImpl \n"
+ " MPU_vQueueUnregisterQueue_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
+ );
+ }
+
+ #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+ const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_pcQueueGetNameImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_pcQueueGetName_Unpriv \n"
+ " MPU_pcQueueGetName_Priv: \n"
+ " b MPU_pcQueueGetNameImpl \n"
+ " MPU_pcQueueGetName_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
+ );
+ }
+
+ #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_pvTimerGetTimerIDImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_pvTimerGetTimerID_Unpriv \n"
+ " MPU_pvTimerGetTimerID_Priv: \n"
+ " b MPU_pvTimerGetTimerIDImpl \n"
+ " MPU_pvTimerGetTimerID_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+ void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+ void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTimerSetTimerIDImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vTimerSetTimerID_Unpriv \n"
+ " MPU_vTimerSetTimerID_Priv: \n"
+ " b MPU_vTimerSetTimerIDImpl \n"
+ " MPU_vTimerSetTimerID_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTimerIsTimerActiveImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTimerIsTimerActive_Unpriv \n"
+ " MPU_xTimerIsTimerActive_Priv: \n"
+ " b MPU_xTimerIsTimerActiveImpl \n"
+ " MPU_xTimerIsTimerActive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n"
+ " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n"
+ " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n"
+ " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTimerGenericCommandFromTaskImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTimerGenericCommandFromTask_Unpriv \n"
+ " MPU_xTimerGenericCommandFromTask_Priv: \n"
+ " b MPU_xTimerGenericCommandFromTaskImpl \n"
+ " MPU_xTimerGenericCommandFromTask_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_pcTimerGetNameImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_pcTimerGetName_Unpriv \n"
+ " MPU_pcTimerGetName_Priv: \n"
+ " b MPU_pcTimerGetNameImpl \n"
+ " MPU_pcTimerGetName_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+ const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+ const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTimerSetReloadModeImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vTimerSetReloadMode_Unpriv \n"
+ " MPU_vTimerSetReloadMode_Priv: \n"
+ " b MPU_vTimerSetReloadModeImpl \n"
+ " MPU_vTimerSetReloadMode_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTimerGetReloadModeImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTimerGetReloadMode_Unpriv \n"
+ " MPU_xTimerGetReloadMode_Priv: \n"
+ " b MPU_xTimerGetReloadModeImpl \n"
+ " MPU_xTimerGetReloadMode_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxTimerGetReloadModeImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_uxTimerGetReloadMode_Unpriv \n"
+ " MPU_uxTimerGetReloadMode_Priv: \n"
+ " b MPU_uxTimerGetReloadModeImpl \n"
+ " MPU_uxTimerGetReloadMode_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTimerGetPeriodImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTimerGetPeriod_Unpriv \n"
+ " MPU_xTimerGetPeriod_Priv: \n"
+ " b MPU_xTimerGetPeriodImpl \n"
+ " MPU_xTimerGetPeriod_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTimerGetExpiryTimeImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xTimerGetExpiryTime_Unpriv \n"
+ " MPU_xTimerGetExpiryTime_Priv: \n"
+ " b MPU_xTimerGetExpiryTimeImpl \n"
+ " MPU_xTimerGetExpiryTime_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_EVENT_GROUPS == 1 )
+
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupWaitBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupWaitBits_Unpriv \n"
+ " MPU_xEventGroupWaitBits_Priv: \n"
+ " b MPU_xEventGroupWaitBitsImpl \n"
+ " MPU_xEventGroupWaitBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_EVENT_GROUPS == 1 )
+
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupClearBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupClearBits_Unpriv \n"
+ " MPU_xEventGroupClearBits_Priv: \n"
+ " b MPU_xEventGroupClearBitsImpl \n"
+ " MPU_xEventGroupClearBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_EVENT_GROUPS == 1 )
+
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSetBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupSetBits_Unpriv \n"
+ " MPU_xEventGroupSetBits_Priv: \n"
+ " b MPU_xEventGroupSetBitsImpl \n"
+ " MPU_xEventGroupSetBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_EVENT_GROUPS == 1 )
+
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSyncImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupSync_Unpriv \n"
+ " MPU_xEventGroupSync_Priv: \n"
+ " b MPU_xEventGroupSyncImpl \n"
+ " MPU_xEventGroupSync_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
+
+ UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxEventGroupGetNumberImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_uxEventGroupGetNumber_Unpriv \n"
+ " MPU_uxEventGroupGetNumber_Priv: \n"
+ " b MPU_uxEventGroupGetNumberImpl \n"
+ " MPU_uxEventGroupGetNumber_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
+ );
+ }
+
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
+
+ void MPU_vEventGroupSetNumber( void * xEventGroup,
+ UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vEventGroupSetNumber( void * xEventGroup,
+ UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vEventGroupSetNumberImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_vEventGroupSetNumber_Unpriv \n"
+ " MPU_vEventGroupSetNumber_Priv: \n"
+ " b MPU_vEventGroupSetNumberImpl \n"
+ " MPU_vEventGroupSetNumber_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
+ );
+ }
+
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSendImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSend_Unpriv \n"
+ " MPU_xStreamBufferSend_Priv: \n"
+ " b MPU_xStreamBufferSendImpl \n"
+ " MPU_xStreamBufferSend_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferReceiveImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferReceive_Unpriv \n"
+ " MPU_xStreamBufferReceive_Priv: \n"
+ " b MPU_xStreamBufferReceiveImpl \n"
+ " MPU_xStreamBufferReceive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsFullImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferIsFull_Unpriv \n"
+ " MPU_xStreamBufferIsFull_Priv: \n"
+ " b MPU_xStreamBufferIsFullImpl \n"
+ " MPU_xStreamBufferIsFull_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsEmptyImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
+ " MPU_xStreamBufferIsEmpty_Priv: \n"
+ " b MPU_xStreamBufferIsEmptyImpl \n"
+ " MPU_xStreamBufferIsEmpty_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
+ " MPU_xStreamBufferSpacesAvailable_Priv: \n"
+ " b MPU_xStreamBufferSpacesAvailableImpl \n"
+ " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferBytesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
+ " MPU_xStreamBufferBytesAvailable_Priv: \n"
+ " b MPU_xStreamBufferBytesAvailableImpl \n"
+ " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
+ " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
+ " b MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
+ " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM52_NTZ/non_secure/port.c b/portable/GCC/ARM_CM52_NTZ/non_secure/port.c
new file mode 100644
index 0000000..76d2b24
--- /dev/null
+++ b/portable/GCC/ARM_CM52_NTZ/non_secure/port.c
@@ -0,0 +1,2280 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU includes. */
+#include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if ( configENABLE_TRUSTZONE == 1 )
+ /* Secure components includes. */
+ #include "secure_context.h"
+ #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration settings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+ #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+ #define portUSE_PSPLIM_REGISTER 0
+#else
+ #define portUSE_PSPLIM_REGISTER 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
+#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
+#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used during system call enter and exit.
+ */
+#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE ( 3UL )
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS ( 20UL )
+#define portCPACR_CP11_POS ( 22UL )
+
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS ( 31UL )
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS ( 30UL )
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Offsets in the stack to the parameters when inside the SVC handler.
+ */
+#define portOFFSET_TO_LR ( 5 )
+#define portOFFSET_TO_PC ( 6 )
+#define portOFFSET_TO_PSR ( 7 )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
+
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+
+ /* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+ #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE_BIT ( 1UL << 0UL )
+
+/* Extract first address of the MPU region as encoded in the
+ * RBAR (Region Base Address Register) value. */
+#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
+ ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK )
+
+/* Extract last address of the MPU region as encoded in the
+ * RLAR (Region Limit Address Register) value. */
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
+ ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
+
+/* Does addr lies within [start, end] address range? */
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
+ ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
+
+/* Is the access request satisfied by the available permissions? */
+#define portIS_AUTHORIZED( accessRequest, permissions ) \
+ ( ( ( permissions ) & ( accessRequest ) ) == accessRequest )
+
+/* Max value that fits in a uint32_t type. */
+#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The maximum 24-bit number.
+ *
+ * It is needed because the systick is a 24-bit counter.
+ */
+#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
+
+/**
+ * @brief A fiddle factor to estimate the number of SysTick counts that would
+ * have occurred while the SysTick counter is stopped during tickless idle
+ * calculations.
+ */
+#define portMISSED_COUNTS_FACTOR ( 94UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR ( 0x01000000 )
+
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF FD
+ * 1111 1111 1111 1111 1111 1111 1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )
+#else
+
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF BC
+ * 1111 1111 1111 1111 1111 1111 1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ * Bit[0] = 0 ==> The task is privileged.
+ * Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
+
+/**
+ * @brief Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register.
+ */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS 1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT 0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+ #define portCONTROL_UPAC_EN ( 1UL << 7UL )
+ #define portCONTROL_PAC_EN ( 1UL << 6UL )
+ #define portCONTROL_UBTI_EN ( 1UL << 5UL )
+ #define portCONTROL_BTI_EN ( 1UL << 4UL )
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief Extract MPU region's access permissions from the Region Base Address
+ * Register (RBAR) value.
+ *
+ * @param ulRBARValue RBAR value for the MPU region.
+ *
+ * @return uint32_t Access permissions.
+ */
+ static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
+
+#if ( configENABLE_MPU == 1 )
+
+ /**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_FPU == 1 )
+
+ /**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ /**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ *
+ * The implementation in this file is weak to allow application writers to
+ * change the timer used to generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether the current execution context is interrupt.
+ *
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE
+ * otherwise.
+ */
+BaseType_t xPortIsInsideInterrupt( void );
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
+ */
+ void vSystemCallEnter( uint32_t * pulTaskStack,
+ uint32_t ulLR,
+ uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief Raise SVC for exiting from a system call.
+ */
+ void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+ void vSystemCallExit( uint32_t * pulSystemCallStack,
+ uint32_t ulLR ) PRIVILEGED_FUNCTION;
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+#if ( configENABLE_MPU == 1 )
+
+ /**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+ PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if ( configENABLE_TRUSTZONE == 1 )
+
+ /**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+ PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+ /**
+ * @brief The number of SysTick increments that make up one tick period.
+ */
+ PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
+
+ /**
+ * @brief The maximum number of tick periods that can be suppressed is
+ * limited by the 24 bit resolution of the SysTick timer.
+ */
+ PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
+
+ /**
+ * @brief Compensate for the CPU cycles that pass while the SysTick is
+ * stopped (low power functionality only).
+ */
+ PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+ __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+ {
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
+ TickType_t xModifiableIdleTime;
+
+ /* Make sure the SysTick reload value does not overflow the counter. */
+ if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+ {
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+ }
+
+ /* Enter a critical section but don't use the taskENTER_CRITICAL()
+ * method as that will mask interrupts that should exit sleep mode. */
+ __asm volatile ( "cpsid i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* If a context switch is pending or a task is waiting for the scheduler
+ * to be unsuspended then abandon the low power entry. */
+ if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+ {
+ /* Re-enable interrupts - see comments above the cpsid instruction
+ * above. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ }
+ else
+ {
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
+ /* Set the new reload value. */
+ portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+ /* Clear the SysTick count flag and set the count value back to
+ * zero. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Restart SysTick. */
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+ * set its parameter to 0 to indicate that its implementation contains
+ * its own wait for interrupt or wait for event instruction, and so wfi
+ * should not be executed again. However, the original expected idle
+ * time variable must remain unmodified, so a copy is taken. */
+ xModifiableIdleTime = xExpectedIdleTime;
+ configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+ if( xModifiableIdleTime > 0 )
+ {
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "wfi" );
+ __asm volatile ( "isb" );
+ }
+
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+ /* Re-enable interrupts to allow the interrupt that brought the MCU
+ * out of sleep mode to execute immediately. See comments above
+ * the cpsid instruction above. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* Disable interrupts again because the clock is about to be stopped
+ * and interrupts that execute while the clock is stopped will increase
+ * any slippage between the time maintained by the RTOS and calendar
+ * time. */
+ __asm volatile ( "cpsid i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* Disable the SysTick clock without reading the
+ * portNVIC_SYSTICK_CTRL_REG register to ensure the
+ * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
+ * the time the SysTick is stopped for is accounted for as best it can
+ * be, but using the tickless mode will inevitably result in some tiny
+ * drift of the time maintained by the kernel with respect to calendar
+ * time*/
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Determine whether the SysTick has already counted to zero. */
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ uint32_t ulCalculatedLoadValue;
+
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+ /* Don't allow a tiny value, or values that have somehow
+ * underflowed because the post sleep hook did something
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ {
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+ /* As the pending tick will be processed as soon as this
+ * function exits, the tick value maintained by the tick is stepped
+ * forward by one less than the time spent waiting. */
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+ }
+ else
+ {
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
+ * periods (not the ulReload value which accounted for part
+ * ticks). */
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
+
+ /* How many complete tick periods passed while the processor
+ * was waiting? */
+ ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+ /* The reload value is set to whatever fraction of a single tick
+ * period remains. */
+ portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+ }
+
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
+ vTaskStepTick( ulCompleteTickPeriods );
+
+ /* Exit with interrupts enabled. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ }
+ }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Calculate the constants required to configure the tick interrupt. */
+ #if ( configUSE_TICKLESS_IDLE == 1 )
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
+ #endif /* configUSE_TICKLESS_IDLE */
+
+ /* Stop and reset SysTick.
+ *
+ * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+ * enable SysTick without first selecting a valid clock source. We trigger
+ * the bug if we change clock sources from a clock with a zero clock period
+ * to one with a nonzero clock period and enable Systick at the same time.
+ * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+ * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+ volatile uint32_t ulDummy = 0UL;
+
+ /* A function that implements a task must not exit or attempt to return to
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()
+ * to be triggered if configASSERT() is defined, then stop here so
+ * application writers can catch the error. */
+ configASSERT( ulCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+
+ while( ulDummy == 0 )
+ {
+ /* This file calls prvTaskExitError() after the scheduler has been
+ * started to remove a compiler warning about the function being
+ * defined but never called. ulDummy is used purely to quieten other
+ * warnings about code appearing after this function is called - making
+ * ulDummy volatile makes the compiler think the function could return
+ * and therefore not output an 'unreachable code' warning for code that
+ * appears after it. */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulAccessPermissions = 0;
+
+ if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY )
+ {
+ ulAccessPermissions = tskMPU_READ_PERMISSION;
+ }
+
+ if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE )
+ {
+ ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION );
+ }
+
+ return ulAccessPermissions;
+ }
+
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_functions_start__;
+ extern uint32_t * __privileged_functions_end__;
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ extern uint32_t * __unprivileged_flash_start__;
+ extern uint32_t * __unprivileged_flash_end__;
+ extern uint32_t * __privileged_sram_start__;
+ extern uint32_t * __privileged_sram_end__;
+ #else /* if defined( __ARMCC_VERSION ) */
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_functions_start__[];
+ extern uint32_t __privileged_functions_end__[];
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ extern uint32_t __unprivileged_flash_start__[];
+ extern uint32_t __unprivileged_flash_end__[];
+ extern uint32_t __privileged_sram_start__[];
+ extern uint32_t __privileged_sram_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+
+ /* The only permitted number of regions are 8 or 16. */
+ configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
+
+ /* MAIR0 - Index 0. */
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ /* MAIR0 - Index 1. */
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* Setup privileged flash as Read Only so that privileged tasks can
+ * read it but not modify. */
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged flash as Read Only by both privileged and
+ * unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged syscalls flash as Read Only by both privileged
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup RAM containing kernel data for privileged access only. */
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Enable mem fault. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
+
+ /* Enable MPU with privileged background access i.e. unmapped
+ * regions have privileged access. */
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
+ }
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_FPU == 1 )
+
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ /* Enable non-secure access to the FPU. */
+ SecureInit_EnableNSFPUAccess();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+ * unprivileged code should be able to access FPU. CP11 should be
+ * programmed to the same value as CP10. */
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+ );
+
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+ * context on exception entry and restore on exception return.
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+ }
+
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Set a PendSV to request a context switch. */
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ portDISABLE_INTERRUPTS();
+ ulCriticalNesting++;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ configASSERT( ulCriticalNesting );
+ ulCriticalNesting--;
+
+ if( ulCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+ uint32_t ulPreviousMask;
+
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ traceISR_EXIT_TO_SCHEDULER();
+ /* Pend a context switch. */
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+ }
+ else
+ {
+ traceISR_EXIT();
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ uint32_t ulPC;
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ uint32_t ulR0, ulR1;
+ extern TaskHandle_t pxCurrentTCB;
+ #if ( configENABLE_MPU == 1 )
+ uint32_t ulControl, ulIsTaskPrivileged;
+ #endif /* configENABLE_MPU */
+ #endif /* configENABLE_TRUSTZONE */
+ uint8_t ucSVCNumber;
+
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+ * R12, LR, PC, xPSR. */
+ ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ];
+ ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+ switch( ucSVCNumber )
+ {
+ #if ( configENABLE_TRUSTZONE == 1 )
+ case portSVC_ALLOCATE_SECURE_CONTEXT:
+
+ /* R0 contains the stack size passed as parameter to the
+ * vPortAllocateSecureContext function. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+
+ #if ( configENABLE_MPU == 1 )
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+ }
+ #else /* if ( configENABLE_MPU == 1 ) */
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+ }
+ #endif /* configENABLE_MPU */
+
+ configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+ SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+ break;
+
+ case portSVC_FREE_SECURE_CONTEXT:
+
+ /* R0 contains TCB being freed and R1 contains the secure
+ * context handle to be freed. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+ ulR1 = pulCallerStackAddress[ 1 ];
+
+ /* Free the secure context. */
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+ break;
+ #endif /* configENABLE_TRUSTZONE */
+
+ case portSVC_START_SCHEDULER:
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
+
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ #if ( configENABLE_FPU == 1 )
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
+ #endif /* configENABLE_FPU */
+
+ /* Setup the context of the first task so that the first task starts
+ * executing. */
+ vRestoreContextOfFirstTask();
+ break;
+
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ case portSVC_RAISE_PRIVILEGE:
+
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ vRaisePrivilege();
+ }
+ break;
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ #if ( configENABLE_MPU == 1 )
+ case portSVC_YIELD:
+ vPortYield();
+ break;
+ #endif /* configENABLE_MPU == 1 */
+
+ default:
+ /* Incorrect SVC call. */
+ configASSERT( pdFALSE );
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ void vSystemCallEnter( uint32_t * pulTaskStack,
+ uint32_t ulLR,
+ uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
+ {
+ extern TaskHandle_t pxCurrentTCB;
+ extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
+ xMPU_SETTINGS * pxMpuSettings;
+ uint32_t * pulSystemCallStack;
+ uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
+
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ #endif /* #if defined( __ARMCC_VERSION ) */
+
+ ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+ pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+
+ /* Checks:
+ * 1. SVC is raised from the system call section (i.e. application is
+ * not raising SVC directly).
+ * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+ * it is non-NULL only during the execution of a system call (i.e.
+ * between system call enter and exit).
+ * 3. System call is not for a kernel API disabled by the configuration
+ * in FreeRTOSConfig.h.
+ * 4. We do not need to check that ucSystemCallNumber is within range
+ * because the assembly SVC handler checks that before calling
+ * this function.
+ */
+ if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+ ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+ ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
+ {
+ pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+ /* Hardware Saved Stack Frame Size upon Exception entry:
+ * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+ * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+ */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ {
+ if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+ {
+ /* Extended frame i.e. FPU in use. */
+ ulHardwareSavedExceptionFrameSize = 26;
+ __asm volatile (
+ " vpush {s0} \n" /* Trigger lazy stacking. */
+ " vpop {s0} \n" /* Nullify the affect of the above instruction. */
+ ::: "memory"
+ );
+ }
+ else
+ {
+ /* Standard frame i.e. FPU not in use. */
+ ulHardwareSavedExceptionFrameSize = 8;
+ }
+ }
+ #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ {
+ ulHardwareSavedExceptionFrameSize = 8;
+ }
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+
+ /* Make space on the system call stack for the stack frame. */
+ pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
+
+ /* Copy the stack frame. */
+ for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
+ {
+ pulSystemCallStack[ i ] = pulTaskStack[ i ];
+ }
+
+ /* Store the value of the Link Register before the SVC was raised.
+ * It contains the address of the caller of the System Call entry
+ * point (i.e. the caller of the MPU_<API>). We need to restore it
+ * when we exit from the system call. */
+ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
+ /* Store the value of the PSPLIM register before the SVC was raised.
+ * We need to restore it when we exit from the system call. */
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
+
+ /* Use the pulSystemCallStack in thread mode. */
+ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ }
+ #endif
+
+ /* Start executing the system call upon returning from this handler. */
+ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
+ /* Raise a request to exit from the system call upon finishing the
+ * system call. */
+ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
+ /* Remember the location where we should copy the stack frame when we exit from
+ * the system call. */
+ pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
+
+ /* Record if the hardware used padding to force the stack pointer
+ * to be double word aligned. */
+ if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+ {
+ pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
+ }
+ else
+ {
+ pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
+ }
+
+ /* We ensure in pxPortInitialiseStack that the system call stack is
+ * double word aligned and therefore, there is no need of padding.
+ * Clear the bit[9] of stacked xPSR. */
+ pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+ /* Raise the privilege for the duration of the system call. */
+ __asm volatile (
+ " mrs r0, control \n" /* Obtain current control value. */
+ " movs r1, #1 \n" /* r1 = 1. */
+ " bics r0, r1 \n" /* Clear nPRIV bit. */
+ " msr control, r0 \n" /* Write back new control value. */
+ ::: "r0", "r1", "memory"
+ );
+ }
+ }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
+ }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ void vSystemCallExit( uint32_t * pulSystemCallStack,
+ uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+ {
+ extern TaskHandle_t pxCurrentTCB;
+ xMPU_SETTINGS * pxMpuSettings;
+ uint32_t * pulTaskStack;
+ uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
+
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_functions_start__;
+ extern uint32_t * __privileged_functions_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_functions_start__[];
+ extern uint32_t __privileged_functions_end__[];
+ #endif /* #if defined( __ARMCC_VERSION ) */
+
+ ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+ pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+
+ /* Checks:
+ * 1. SVC is raised from the privileged code (i.e. application is not
+ * raising SVC directly). This SVC is only raised from
+ * vRequestSystemCallExit which is in the privileged code section.
+ * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+ * this means that we previously entered a system call and the
+ * application is not attempting to exit without entering a system
+ * call.
+ */
+ if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+ ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+ ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
+ {
+ pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+ /* Hardware Saved Stack Frame Size upon Exception entry:
+ * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+ * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+ */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ {
+ if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+ {
+ /* Extended frame i.e. FPU in use. */
+ ulHardwareSavedExceptionFrameSize = 26;
+ __asm volatile (
+ " vpush {s0} \n" /* Trigger lazy stacking. */
+ " vpop {s0} \n" /* Nullify the affect of the above instruction. */
+ ::: "memory"
+ );
+ }
+ else
+ {
+ /* Standard frame i.e. FPU not in use. */
+ ulHardwareSavedExceptionFrameSize = 8;
+ }
+ }
+ #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ {
+ ulHardwareSavedExceptionFrameSize = 8;
+ }
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+
+ /* Make space on the task stack for the stack frame. */
+ pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
+
+ /* Copy the stack frame. */
+ for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
+ {
+ pulTaskStack[ i ] = pulSystemCallStack[ i ];
+ }
+
+ /* Use the pulTaskStack in thread mode. */
+ __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+ /* Return to the caller of the System Call entry point (i.e. the
+ * caller of the MPU_<API>). */
+ pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+ /* Ensure that LR has a valid value.*/
+ pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+ /* Restore the PSPLIM register to what it was at the time of
+ * system call entry. */
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
+
+ /* If the hardware used padding to force the stack pointer
+ * to be double word aligned, set the stacked xPSR bit[9],
+ * otherwise clear it. */
+ if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+ {
+ pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
+ }
+ else
+ {
+ pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+ }
+
+ /* This is not NULL only for the duration of the system call. */
+ pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+ /* Drop the privilege before returning to the thread mode. */
+ __asm volatile (
+ " mrs r0, control \n" /* Obtain current control value. */
+ " movs r1, #1 \n" /* r1 = 1. */
+ " orrs r0, r1 \n" /* Set nPRIV bit. */
+ " msr control, r0 \n" /* Write back new control value. */
+ ::: "r0", "r1", "memory"
+ );
+ }
+ }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
+ {
+ BaseType_t xTaskIsPrivileged = pdFALSE;
+ const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+ if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ {
+ xTaskIsPrivileged = pdTRUE;
+ }
+
+ return xTaskIsPrivileged;
+ }
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ StackType_t * pxEndOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters,
+ BaseType_t xRunPrivileged,
+ xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulIndex = 0;
+ uint32_t ulControl = 0x0;
+
+ xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+ ulIndex++;
+
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
+ ulIndex++;
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+ ulIndex++;
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
+ ulIndex++;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Check PACBTI security feature configuration before pushing the
+ * CONTROL register's value on task's TCB. */
+ ulControl = prvConfigurePACBTI( pdFALSE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
+ if( xRunPrivileged == pdTRUE )
+ {
+ xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
+ ulIndex++;
+ }
+ else
+ {
+ xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
+ ulIndex++;
+ }
+
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+ ulIndex++;
+
+ #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+ {
+ /* Ensure that the system call stack is double word aligned. */
+ xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+ xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+ ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+ xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+ xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+ ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+ ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+ /* This is not NULL only for the duration of a system call. */
+ xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+ }
+ #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+ ulIndex++;
+ }
+ }
+ #endif /* configENABLE_PAC */
+
+ return &( xMPUSettings->ulContext[ ulIndex ] );
+ }
+
+#else /* configENABLE_MPU */
+
+ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ StackType_t * pxEndOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters ) /* PRIVILEGED_FUNCTION */
+ {
+ /* Simulate the stack frame as it would be created by a context switch
+ * interrupt. */
+ #if ( portPRELOAD_REGISTERS == 0 )
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #else /* portPRELOAD_REGISTERS */
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #endif /* portPRELOAD_REGISTERS */
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = ulTaskPacKey[ i ];
+ }
+ }
+ #endif /* configENABLE_PAC */
+
+ return pxTopOfStack;
+ }
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+ * for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * SVC_Handler and PendSV_Handler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+ {
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+ {
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * First, determine the number of priority bits available. Write to all
+ * possible bits in the priority setting for SVCall. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Check that the bits not implemented in hardware are zero in
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
+
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
+ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+ portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Set the CONTROL register value based on PACBTI security feature
+ * configuration before starting the first task. */
+ ( void ) prvConfigurePACBTI( pdTRUE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
+ #if ( configENABLE_MPU == 1 )
+ {
+ /* Setup the Memory Protection Unit (MPU). */
+ prvSetupMPU();
+ }
+ #endif /* configENABLE_MPU */
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ * here already. */
+ vPortSetupTimerInterrupt();
+
+ /* Initialize the critical nesting count ready for the first task. */
+ ulCriticalNesting = 0;
+
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+ {
+ xSchedulerRunning = pdTRUE;
+ }
+ #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
+
+ /* Start the first task. */
+ vStartFirstTask();
+
+ /* Should never get here as the tasks will now be executing. Call the task
+ * exit error function to prevent compiler warnings about a static function
+ * not being called in the case that the application writer overrides this
+ * functionality by defining configTASK_RETURN_ADDRESS. Call
+ * vTaskSwitchContext() so link time optimization does not remove the
+ * symbol. */
+ vTaskSwitchContext();
+ prvTaskExitError();
+
+ /* Should not get here. */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Not implemented in ports where there is nothing to return to.
+ * Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+ const struct xMEMORY_REGION * const xRegions,
+ StackType_t * pxBottomOfStack,
+ configSTACK_DEPTH_TYPE uxStackDepth )
+ {
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+ int32_t lIndex = 0;
+
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_sram_start__;
+ extern uint32_t * __privileged_sram_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_sram_start__[];
+ extern uint32_t __privileged_sram_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+
+ /* Setup MAIR0. */
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* This function is called automatically when the task is created - in
+ * which case the stack region parameters will be valid. At all other
+ * times the stack parameters will not be valid and it is assumed that
+ * the stack region has already been configured. */
+ if( uxStackDepth > 0 )
+ {
+ ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
+
+ /* If the stack is within the privileged SRAM, do not protect it
+ * using a separate MPU region. This is needed because privileged
+ * SRAM is already protected using an MPU region and ARMv8-M does
+ * not allow overlapping MPU regions. */
+ if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+ ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
+ {
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
+ }
+ else
+ {
+ /* Define the region that allows access to the stack. */
+ ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+ }
+ }
+
+ /* User supplied configurable regions. */
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+ {
+ /* If xRegions is NULL i.e. the task has not specified any MPU
+ * region, the else part ensures that all the configurable MPU
+ * regions are invalidated. */
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+ {
+ /* Translate the generic region definition contained in xRegions
+ * into the ARMv8 specific MPU settings that are then stored in
+ * xMPUSettings. */
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ /* Start address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE );
+
+ /* RO/RW. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+ }
+ else
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+ }
+
+ /* XN. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+ }
+
+ /* End Address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* PXN. */
+ #if ( portARMV8M_MINOR_VERSION >= 1 )
+ {
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+ }
+ }
+ #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
+ /* Normal memory/ Device memory. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+ {
+ /* Attr1 in MAIR0 is configured as device memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+ }
+ else
+ {
+ /* Attr0 in MAIR0 is configured as normal memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+ }
+ }
+ else
+ {
+ /* Invalidate the region. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+ }
+
+ lIndex++;
+ }
+ }
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
+ uint32_t ulBufferLength,
+ uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
+
+ {
+ uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
+ BaseType_t xAccessGranted = pdFALSE;
+ const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ {
+ xAccessGranted = pdTRUE;
+ }
+ else
+ {
+ if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
+ {
+ ulBufferStartAddress = ( uint32_t ) pvBuffer;
+ ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
+
+ for( i = 0; i < portTOTAL_NUM_REGIONS; i++ )
+ {
+ /* Is the MPU region enabled? */
+ if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE )
+ {
+ if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
+ portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ),
+ portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) &&
+ portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
+ portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ),
+ portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) &&
+ portIS_AUTHORIZED( ulAccessRequested,
+ prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) )
+ {
+ xAccessGranted = pdTRUE;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ return xAccessGranted;
+ }
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortIsInsideInterrupt( void )
+{
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
+
+ /* Obtain the number of the currently executing interrupt. Interrupt Program
+ * Status Register (IPSR) holds the exception number of the currently-executing
+ * exception or zero for Thread mode.*/
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ if( ulCurrentInterrupt == 0 )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+ void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+ int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+ xMPU_SETTINGS * xTaskMpuSettings;
+
+ ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+ ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+ xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+ xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+ }
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+ void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+ int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+ xMPU_SETTINGS * xTaskMpuSettings;
+
+ ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+ ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+ xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+ xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+ }
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+ BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+ BaseType_t xAccessGranted = pdFALSE;
+ const xMPU_SETTINGS * xTaskMpuSettings;
+
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else
+ {
+ xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+ ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+ ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+ if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ {
+ xAccessGranted = pdTRUE;
+ }
+ else
+ {
+ if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+ {
+ xAccessGranted = pdTRUE;
+ }
+ }
+ }
+
+ return xAccessGranted;
+ }
+
+ #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+ BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+ {
+ ( void ) lInternalIndexOfKernelObject;
+
+ /* If Access Control List feature is not used, all the tasks have
+ * access to all the kernel objects. */
+ return pdTRUE;
+ }
+
+ #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+ {
+ uint32_t ulControl = 0x0;
+
+ /* Ensure that PACBTI is implemented. */
+ configASSERT( portID_ISAR5_REG != 0x0 );
+
+ /* Enable UsageFault exception. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+ }
+ #endif
+
+ #if ( configENABLE_BTI == 1 )
+ {
+ ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+ }
+ #endif
+
+ if( xWriteControlRegister == pdTRUE )
+ {
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+ }
+
+ return ulControl;
+ }
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM52_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM52_NTZ/non_secure/portasm.c
new file mode 100644
index 0000000..bc7bb60
--- /dev/null
+++ b/portable/GCC/ARM_CM52_NTZ/non_secure/portasm.c
@@ -0,0 +1,524 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if ( configENABLE_MPU == 1 )
+
+ void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " program_mpu_first_task: \n"
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
+ " \n"
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
+ " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+ " str r2, [r1] \n" /* Disable MPU. */
+ " \n"
+ " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+ " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+ " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r1, [r2] \n" /* Program MAIR0. */
+ " \n"
+ " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+ " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " \n"
+ " movs r3, #4 \n" /* r3 = 4. */
+ " str r3, [r1] \n" /* Program RNR = 4. */
+ " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " \n"
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ " movs r3, #8 \n" /* r3 = 8. */
+ " str r3, [r1] \n" /* Program RNR = 8. */
+ " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " movs r3, #12 \n" /* r3 = 12. */
+ " str r3, [r1] \n" /* Program RNR = 12. */
+ " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ #endif /* configTOTAL_MPU_REGIONS == 16 */
+ " \n"
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
+ " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+ " str r2, [r1] \n" /* Enable MPU. */
+ " dsb \n" /* Force memory writes before continuing. */
+ " \n"
+ " restore_context_first_task: \n"
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
+ " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
+ " \n"
+ " restore_special_regs_first_task: \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */
+ " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_1, r3 \n"
+ " msr PAC_KEY_P_2, r4 \n"
+ " msr PAC_KEY_P_3, r5 \n"
+ " clrm {r2-r5} \n" /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
+ " ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
+ " msr psp, r2 \n"
+ " msr psplim, r3 \n"
+ " msr control, r4 \n"
+ " \n"
+ " restore_general_regs_first_task: \n"
+ " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */
+ " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */
+ " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */
+ " \n"
+ " restore_context_done_first_task: \n"
+ " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
+ " bx lr \n"
+ );
+ }
+
+#else /* configENABLE_MPU */
+
+ void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
+ " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+ " \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */
+ " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_2, r2 \n"
+ " msr PAC_KEY_P_1, r3 \n"
+ " msr PAC_KEY_P_0, r4 \n"
+ " clrm {r1-r4} \n" /* Clear r1-r4. */
+ #endif /* configENABLE_PAC */
+ " \n"
+ " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+ " msr psplim, r1 \n" /* Set this task's PSPLIM value. */
+ " mrs r1, control \n" /* Obtain current control register value. */
+ " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
+ " msr control, r1 \n" /* Write back the new control register value. */
+ " adds r0, #32 \n" /* Discard everything up to r0. */
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
+ " bx r2 \n" /* Finally, branch to EXC_RETURN. */
+ );
+ }
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n" /* r0 = CONTROL. */
+ " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ " ite ne \n"
+ " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ " bx lr \n" /* Return. */
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n" /* Read the CONTROL register. */
+ " bic r0, #1 \n" /* Clear the bit 0. */
+ " msr control, r0 \n" /* Write back the new CONTROL value. */
+ " bx lr \n" /* Return to the caller. */
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n" /* r0 = CONTROL. */
+ " orr r0, #1 \n" /* r0 = r0 | 1. */
+ " msr control, r0 \n" /* CONTROL = r0. */
+ " bx lr \n" /* Return to the caller. */
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
+ " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
+ " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
+ " cpsie i \n" /* Globally enable interrupts. */
+ " cpsie f \n"
+ " dsb \n"
+ " isb \n"
+ " svc %0 \n" /* System call to start the first task. */
+ " nop \n"
+ ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */
+ " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bx lr \n" /* Return. */
+ ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " msr basepri, r0 \n" /* basepri = ulMask. */
+ " dsb \n"
+ " isb \n"
+ " bx lr \n" /* Return. */
+ ::: "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
+ " ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */
+ " mrs r2, psp \n" /* r2 = PSP. */
+ " \n"
+ " save_general_regs: \n"
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " add r2, r2, #0x20 \n" /* Move r2 to location where s0 is saved. */
+ " tst lr, #0x10 \n"
+ " ittt eq \n"
+ " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */
+ " vldmiaeq r2, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */
+ " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */
+ " sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+ " stmia r1!, {r4-r11} \n" /* Store r4-r11. */
+ " ldmia r2, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */
+ " stmia r1!, {r4-r11} \n" /* Store the hardware saved context. */
+ " \n"
+ " save_special_regs: \n"
+ " mrs r3, psplim \n" /* r3 = PSPLIM. */
+ " mrs r4, control \n" /* r4 = CONTROL. */
+ " stmia r1!, {r2-r4, lr} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+ #if ( configENABLE_PAC == 1 )
+ " mrs r2, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */
+ " mrs r3, PAC_KEY_P_1 \n"
+ " mrs r4, PAC_KEY_P_2 \n"
+ " mrs r5, PAC_KEY_P_3 \n"
+ " stmia r1!, {r2-r5} \n" /* Store the task's dedicated PAC key on the task's context. */
+ " clrm {r2-r5} \n" /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
+ " str r1, [r0] \n" /* Save the location from where the context should be restored as the first member of TCB. */
+ " \n"
+ " select_next_task: \n"
+ " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n" /* r0 = 0. */
+ " msr basepri, r0 \n" /* Enable interrupts. */
+ " \n"
+ " program_mpu: \n"
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
+ " \n"
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
+ " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+ " str r2, [r1] \n" /* Disable MPU. */
+ " \n"
+ " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+ " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+ " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r1, [r2] \n" /* Program MAIR0. */
+ " \n"
+ " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+ " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " \n"
+ " movs r3, #4 \n" /* r3 = 4. */
+ " str r3, [r1] \n" /* Program RNR = 4. */
+ " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " \n"
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ " movs r3, #8 \n" /* r3 = 8. */
+ " str r3, [r1] \n" /* Program RNR = 8. */
+ " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " movs r3, #12 \n" /* r3 = 12. */
+ " str r3, [r1] \n" /* Program RNR = 12. */
+ " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ #endif /* configTOTAL_MPU_REGIONS == 16 */
+ " \n"
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
+ " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+ " str r2, [r1] \n" /* Enable MPU. */
+ " dsb \n" /* Force memory writes before continuing. */
+ " \n"
+ " restore_context: \n"
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
+ " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
+ " \n"
+ " restore_special_regs: \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */
+ " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_1, r3 \n"
+ " msr PAC_KEY_P_2, r4 \n"
+ " msr PAC_KEY_P_3, r5 \n"
+ " clrm {r2-r5} \n" /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
+ " ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
+ " msr psp, r2 \n"
+ " msr psplim, r3 \n"
+ " msr control, r4 \n"
+ " \n"
+ " restore_general_regs: \n"
+ " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */
+ " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */
+ " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " tst lr, #0x10 \n"
+ " ittt eq \n"
+ " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */
+ " vstmiaeq r2!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */
+ " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+ " \n"
+ " restore_context_done: \n"
+ " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
+ " bx lr \n"
+ ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+ );
+ }
+
+#else /* configENABLE_MPU */
+
+ void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, psp \n" /* Read PSP in r0. */
+ " \n"
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vstmdbeq r0!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+ " \n"
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
+ " stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
+ " \n"
+ #if ( configENABLE_PAC == 1 )
+ " mrs r1, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */
+ " mrs r2, PAC_KEY_P_2 \n"
+ " mrs r3, PAC_KEY_P_1 \n"
+ " mrs r4, PAC_KEY_P_0 \n"
+ " stmdb r0!, {r1-r4} \n" /* Store the task's dedicated PAC key on the stack. */
+ " clrm {r1-r4} \n" /* Clear r1-r4. */
+ #endif /* configENABLE_PAC */
+ " \n"
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
+ " str r0, [r1] \n" /* Save the new top of stack in TCB. */
+ " \n"
+ " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n" /* r0 = 0. */
+ " msr basepri, r0 \n" /* Enable interrupts. */
+ " \n"
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+ " \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmia r0!, {r2-r5} \n" /* Read task's dedicated PAC key from stack. */
+ " msr PAC_KEY_P_3, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_2, r3 \n"
+ " msr PAC_KEY_P_1, r4 \n"
+ " msr PAC_KEY_P_0, r5 \n"
+ " clrm {r2-r5} \n" /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
+ " \n"
+ " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+ " \n"
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vldmiaeq r0!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+ " \n"
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
+ " msr psp, r0 \n" /* Remember the new top of stack for the task. */
+ " bx r3 \n"
+ ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+ );
+ }
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile
+ (
+ ".syntax unified \n"
+ ".extern vPortSVCHandler_C \n"
+ ".extern vSystemCallEnter \n"
+ ".extern vSystemCallExit \n"
+ " \n"
+ "tst lr, #4 \n"
+ "ite eq \n"
+ "mrseq r0, msp \n"
+ "mrsne r0, psp \n"
+ " \n"
+ "ldr r1, [r0, #24] \n"
+ "ldrb r2, [r1, #-2] \n"
+ "cmp r2, %0 \n"
+ "blt syscall_enter \n"
+ "cmp r2, %1 \n"
+ "beq syscall_exit \n"
+ "b vPortSVCHandler_C \n"
+ " \n"
+ "syscall_enter: \n"
+ " mov r1, lr \n"
+ " b vSystemCallEnter \n"
+ " \n"
+ "syscall_exit: \n"
+ " mov r1, lr \n"
+ " b vSystemCallExit \n"
+ " \n"
+ : /* No outputs. */
+ : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+ : "r0", "r1", "r2", "memory"
+ );
+ }
+
+#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+ void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " tst lr, #4 \n"
+ " ite eq \n"
+ " mrseq r0, msp \n"
+ " mrsne r0, psp \n"
+ " ldr r1, =vPortSVCHandler_C \n"
+ " bx r1 \n"
+ );
+ }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM52_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM52_NTZ/non_secure/portasm.h
new file mode 100644
index 0000000..b7021b0
--- /dev/null
+++ b/portable/GCC/ARM_CM52_NTZ/non_secure/portasm.h
@@ -0,0 +1,114 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kernel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/portable/GCC/ARM_CM52_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM52_NTZ/non_secure/portmacro.h
new file mode 100644
index 0000000..1041a03
--- /dev/null
+++ b/portable/GCC/ARM_CM52_NTZ/non_secure/portmacro.h
@@ -0,0 +1,80 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright (c) 2025 Arm Technology (China) Co., Ltd.All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_MVE
+ #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.
+#endif /* configENABLE_MVE */
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME "Cortex-M52"
+#define portHAS_ARMV8M_MAIN_EXTENSION 1
+#define portARMV8M_MINOR_VERSION 1
+#define portDONT_DISCARD __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
+/*-----------------------------------------------------------*/
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM_CM52_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM52_NTZ/non_secure/portmacrocommon.h
new file mode 100644
index 0000000..f373bca
--- /dev/null
+++ b/portable/GCC/ARM_CM52_NTZ/non_secure/portmacrocommon.h
@@ -0,0 +1,582 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern BaseType_t xPortIsInsideInterrupt( void );
+
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+ /**
+ * @brief Generates 128-bit task's random PAC key.
+ *
+ * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+ * filled with a 128-bit random number.
+ */
+ void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
+
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+ /* Define to 8 for backward compatibility. */
+ #define configTOTAL_MPU_REGIONS ( 8UL )
+#endif
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ * Bit[7:4] - 0000 - Device Memory
+ * Bit[3:2] - 00 --> Device-nGnRnE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
+ * Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ /**
+ * @brief Settings to define an MPU region.
+ */
+ typedef struct MPURegionSettings
+ {
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+ } MPURegionSettings_t;
+
+ #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+ #ifndef configSYSTEM_CALL_STACK_SIZE
+ #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
+ #endif
+
+ /**
+ * @brief System call stack.
+ */
+ typedef struct SYSTEM_CALL_STACK_INFO
+ {
+ uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
+ uint32_t * pulSystemCallStack;
+ uint32_t * pulSystemCallStackLimit;
+ uint32_t * pulTaskStack;
+ uint32_t ulLinkRegisterAtSystemCallEntry;
+ uint32_t ulStackLimitRegisterAtSystemCallEntry;
+ } xSYSTEM_CALL_STACK_INFO;
+
+ #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+ /**
+ * @brief MPU settings as stored in the TCB.
+ */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+ * 16 17 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 71
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ * 16 17 8 8 5 1
+ */
+ #define MAX_CONTEXT_SIZE 55
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | | | PC, xPSR | EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+ * 16 17 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 70
+
+ #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | |
+ * | | | | PC, xPSR | EXC_RETURN | |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ * 16 17 8 8 4 1
+ */
+ #define MAX_CONTEXT_SIZE 54
+
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +----------+-----------------+------------------------------+------------+-----+
+ *
+ * <---------><----------------><------------------------------><-----------><---->
+ * 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 38
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ * 8 8 5 1
+ */
+ #define MAX_CONTEXT_SIZE 22
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+----------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | PC, xPSR | EXC_RETURN | | |
+ * +----------+-----------------+----------------------+------------+-----+
+ *
+ * <---------><----------------><----------------------><-----------><---->
+ * 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 37
+
+ #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+
+ /*
+ * +----------+-----------------+----------------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | |
+ * | | PC, xPSR | EXC_RETURN | |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ * 8 8 4 1
+ */
+ #define MAX_CONTEXT_SIZE 21
+
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+
+ /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+ #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+ #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+
+ /* Size of an Access Control List (ACL) entry in bits. */
+ #define portACL_ENTRY_SIZE_BITS ( 32U )
+
+ typedef struct MPU_SETTINGS
+ {
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+ uint32_t ulContext[ MAX_CONTEXT_SIZE ];
+ uint32_t ulTaskFlags;
+
+ #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+ xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+ #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+ uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
+ #endif
+ #endif
+ } xMPU_SETTINGS;
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#if ( configASSERT_DEFINED == 1 )
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT 100
+#define portSVC_FREE_SECURE_CONTEXT 101
+#define portSVC_START_SCHEDULER 102
+#define portSVC_RAISE_PRIVILEGE 103
+#define portSVC_SYSTEM_CALL_EXIT 104
+#define portSVC_YIELD 105
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#if ( configENABLE_MPU == 1 )
+ #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() vPortYield()
+#else
+ #define portYIELD() vPortYield()
+ #define portYIELD_WITHIN_API() vPortYield()
+#endif
+
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ extern BaseType_t xPortIsTaskPrivileged( void );
+
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #else
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+ #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+ static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint32_t ulReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ulReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+ #endif
+
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+ #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+ #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACROCOMMON_H */
diff --git a/portable/IAR/ARM_CM52/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM52/non_secure/mpu_wrappers_v2_asm.S
new file mode 100644
index 0000000..d2cb78e
--- /dev/null
+++ b/portable/IAR/ARM_CM52/non_secure/mpu_wrappers_v2_asm.S
@@ -0,0 +1,1242 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+ SECTION freertos_system_calls:CODE:NOROOT(2)
+ THUMB
+/*-----------------------------------------------------------*/
+
+#include "FreeRTOSConfig.h"
+#include "mpu_syscall_numbers.h"
+
+#ifndef configUSE_MPU_WRAPPERS_V1
+ #define configUSE_MPU_WRAPPERS_V1 0
+#endif
+
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ PUBLIC MPU_xTaskDelayUntil
+MPU_xTaskDelayUntil:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskDelayUntil_Unpriv
+ MPU_xTaskDelayUntil_Priv:
+ b MPU_xTaskDelayUntilImpl
+ MPU_xTaskDelayUntil_Unpriv:
+ svc #SYSTEM_CALL_xTaskDelayUntil
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTaskAbortDelay
+MPU_xTaskAbortDelay:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskAbortDelay_Unpriv
+ MPU_xTaskAbortDelay_Priv:
+ b MPU_xTaskAbortDelayImpl
+ MPU_xTaskAbortDelay_Unpriv:
+ svc #SYSTEM_CALL_xTaskAbortDelay
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vTaskDelay
+MPU_vTaskDelay:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vTaskDelay_Unpriv
+ MPU_vTaskDelay_Priv:
+ b MPU_vTaskDelayImpl
+ MPU_vTaskDelay_Unpriv:
+ svc #SYSTEM_CALL_vTaskDelay
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_uxTaskPriorityGet
+MPU_uxTaskPriorityGet:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_uxTaskPriorityGet_Unpriv
+ MPU_uxTaskPriorityGet_Priv:
+ b MPU_uxTaskPriorityGetImpl
+ MPU_uxTaskPriorityGet_Unpriv:
+ svc #SYSTEM_CALL_uxTaskPriorityGet
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_eTaskGetState
+MPU_eTaskGetState:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_eTaskGetState_Unpriv
+ MPU_eTaskGetState_Priv:
+ b MPU_eTaskGetStateImpl
+ MPU_eTaskGetState_Unpriv:
+ svc #SYSTEM_CALL_eTaskGetState
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vTaskGetInfo
+MPU_vTaskGetInfo:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vTaskGetInfo_Unpriv
+ MPU_vTaskGetInfo_Priv:
+ b MPU_vTaskGetInfoImpl
+ MPU_vTaskGetInfo_Unpriv:
+ svc #SYSTEM_CALL_vTaskGetInfo
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTaskGetIdleTaskHandle
+MPU_xTaskGetIdleTaskHandle:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskGetIdleTaskHandle_Unpriv
+ MPU_xTaskGetIdleTaskHandle_Priv:
+ b MPU_xTaskGetIdleTaskHandleImpl
+ MPU_xTaskGetIdleTaskHandle_Unpriv:
+ svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vTaskSuspend
+MPU_vTaskSuspend:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vTaskSuspend_Unpriv
+ MPU_vTaskSuspend_Priv:
+ b MPU_vTaskSuspendImpl
+ MPU_vTaskSuspend_Unpriv:
+ svc #SYSTEM_CALL_vTaskSuspend
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vTaskResume
+MPU_vTaskResume:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vTaskResume_Unpriv
+ MPU_vTaskResume_Priv:
+ b MPU_vTaskResumeImpl
+ MPU_vTaskResume_Unpriv:
+ svc #SYSTEM_CALL_vTaskResume
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTaskGetTickCount
+MPU_xTaskGetTickCount:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskGetTickCount_Unpriv
+ MPU_xTaskGetTickCount_Priv:
+ b MPU_xTaskGetTickCountImpl
+ MPU_xTaskGetTickCount_Unpriv:
+ svc #SYSTEM_CALL_xTaskGetTickCount
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_uxTaskGetNumberOfTasks
+MPU_uxTaskGetNumberOfTasks:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_uxTaskGetNumberOfTasks_Unpriv
+ MPU_uxTaskGetNumberOfTasks_Priv:
+ b MPU_uxTaskGetNumberOfTasksImpl
+ MPU_uxTaskGetNumberOfTasks_Unpriv:
+ svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_ulTaskGetRunTimeCounter
+MPU_ulTaskGetRunTimeCounter:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_ulTaskGetRunTimeCounter_Unpriv
+ MPU_ulTaskGetRunTimeCounter_Priv:
+ b MPU_ulTaskGetRunTimeCounterImpl
+ MPU_ulTaskGetRunTimeCounter_Unpriv:
+ svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_ulTaskGetRunTimePercent
+MPU_ulTaskGetRunTimePercent:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_ulTaskGetRunTimePercent_Unpriv
+ MPU_ulTaskGetRunTimePercent_Priv:
+ b MPU_ulTaskGetRunTimePercentImpl
+ MPU_ulTaskGetRunTimePercent_Unpriv:
+ svc #SYSTEM_CALL_ulTaskGetRunTimePercent
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_ulTaskGetIdleRunTimePercent
+MPU_ulTaskGetIdleRunTimePercent:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
+ MPU_ulTaskGetIdleRunTimePercent_Priv:
+ b MPU_ulTaskGetIdleRunTimePercentImpl
+ MPU_ulTaskGetIdleRunTimePercent_Unpriv:
+ svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_ulTaskGetIdleRunTimeCounter
+MPU_ulTaskGetIdleRunTimeCounter:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
+ MPU_ulTaskGetIdleRunTimeCounter_Priv:
+ b MPU_ulTaskGetIdleRunTimeCounterImpl
+ MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
+ svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vTaskSetApplicationTaskTag
+MPU_vTaskSetApplicationTaskTag:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vTaskSetApplicationTaskTag_Unpriv
+ MPU_vTaskSetApplicationTaskTag_Priv:
+ b MPU_vTaskSetApplicationTaskTagImpl
+ MPU_vTaskSetApplicationTaskTag_Unpriv:
+ svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTaskGetApplicationTaskTag
+MPU_xTaskGetApplicationTaskTag:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskGetApplicationTaskTag_Unpriv
+ MPU_xTaskGetApplicationTaskTag_Priv:
+ b MPU_xTaskGetApplicationTaskTagImpl
+ MPU_xTaskGetApplicationTaskTag_Unpriv:
+ svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vTaskSetThreadLocalStoragePointer
+MPU_vTaskSetThreadLocalStoragePointer:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
+ MPU_vTaskSetThreadLocalStoragePointer_Priv:
+ b MPU_vTaskSetThreadLocalStoragePointerImpl
+ MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
+ svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
+MPU_pvTaskGetThreadLocalStoragePointer:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
+ MPU_pvTaskGetThreadLocalStoragePointer_Priv:
+ b MPU_pvTaskGetThreadLocalStoragePointerImpl
+ MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
+ svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_uxTaskGetSystemState
+MPU_uxTaskGetSystemState:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_uxTaskGetSystemState_Unpriv
+ MPU_uxTaskGetSystemState_Priv:
+ b MPU_uxTaskGetSystemStateImpl
+ MPU_uxTaskGetSystemState_Unpriv:
+ svc #SYSTEM_CALL_uxTaskGetSystemState
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_uxTaskGetStackHighWaterMark
+MPU_uxTaskGetStackHighWaterMark:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_uxTaskGetStackHighWaterMark_Unpriv
+ MPU_uxTaskGetStackHighWaterMark_Priv:
+ b MPU_uxTaskGetStackHighWaterMarkImpl
+ MPU_uxTaskGetStackHighWaterMark_Unpriv:
+ svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_uxTaskGetStackHighWaterMark2
+MPU_uxTaskGetStackHighWaterMark2:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
+ MPU_uxTaskGetStackHighWaterMark2_Priv:
+ b MPU_uxTaskGetStackHighWaterMark2Impl
+ MPU_uxTaskGetStackHighWaterMark2_Unpriv:
+ svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTaskGetCurrentTaskHandle
+MPU_xTaskGetCurrentTaskHandle:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskGetCurrentTaskHandle_Unpriv
+ MPU_xTaskGetCurrentTaskHandle_Priv:
+ b MPU_xTaskGetCurrentTaskHandleImpl
+ MPU_xTaskGetCurrentTaskHandle_Unpriv:
+ svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTaskGetSchedulerState
+MPU_xTaskGetSchedulerState:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskGetSchedulerState_Unpriv
+ MPU_xTaskGetSchedulerState_Priv:
+ b MPU_xTaskGetSchedulerStateImpl
+ MPU_xTaskGetSchedulerState_Unpriv:
+ svc #SYSTEM_CALL_xTaskGetSchedulerState
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vTaskSetTimeOutState
+MPU_vTaskSetTimeOutState:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vTaskSetTimeOutState_Unpriv
+ MPU_vTaskSetTimeOutState_Priv:
+ b MPU_vTaskSetTimeOutStateImpl
+ MPU_vTaskSetTimeOutState_Unpriv:
+ svc #SYSTEM_CALL_vTaskSetTimeOutState
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTaskCheckForTimeOut
+MPU_xTaskCheckForTimeOut:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskCheckForTimeOut_Unpriv
+ MPU_xTaskCheckForTimeOut_Priv:
+ b MPU_xTaskCheckForTimeOutImpl
+ MPU_xTaskCheckForTimeOut_Unpriv:
+ svc #SYSTEM_CALL_xTaskCheckForTimeOut
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTaskGenericNotifyEntry
+MPU_xTaskGenericNotifyEntry:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskGenericNotify_Unpriv
+ MPU_xTaskGenericNotify_Priv:
+ b MPU_xTaskGenericNotifyImpl
+ MPU_xTaskGenericNotify_Unpriv:
+ svc #SYSTEM_CALL_xTaskGenericNotify
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTaskGenericNotifyWaitEntry
+MPU_xTaskGenericNotifyWaitEntry:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskGenericNotifyWait_Unpriv
+ MPU_xTaskGenericNotifyWait_Priv:
+ b MPU_xTaskGenericNotifyWaitImpl
+ MPU_xTaskGenericNotifyWait_Unpriv:
+ svc #SYSTEM_CALL_xTaskGenericNotifyWait
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_ulTaskGenericNotifyTake
+MPU_ulTaskGenericNotifyTake:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_ulTaskGenericNotifyTake_Unpriv
+ MPU_ulTaskGenericNotifyTake_Priv:
+ b MPU_ulTaskGenericNotifyTakeImpl
+ MPU_ulTaskGenericNotifyTake_Unpriv:
+ svc #SYSTEM_CALL_ulTaskGenericNotifyTake
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTaskGenericNotifyStateClear
+MPU_xTaskGenericNotifyStateClear:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskGenericNotifyStateClear_Unpriv
+ MPU_xTaskGenericNotifyStateClear_Priv:
+ b MPU_xTaskGenericNotifyStateClearImpl
+ MPU_xTaskGenericNotifyStateClear_Unpriv:
+ svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_ulTaskGenericNotifyValueClear
+MPU_ulTaskGenericNotifyValueClear:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_ulTaskGenericNotifyValueClear_Unpriv
+ MPU_ulTaskGenericNotifyValueClear_Priv:
+ b MPU_ulTaskGenericNotifyValueClearImpl
+ MPU_ulTaskGenericNotifyValueClear_Unpriv:
+ svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xQueueGenericSend
+MPU_xQueueGenericSend:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xQueueGenericSend_Unpriv
+ MPU_xQueueGenericSend_Priv:
+ b MPU_xQueueGenericSendImpl
+ MPU_xQueueGenericSend_Unpriv:
+ svc #SYSTEM_CALL_xQueueGenericSend
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_uxQueueMessagesWaiting
+MPU_uxQueueMessagesWaiting:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_uxQueueMessagesWaiting_Unpriv
+ MPU_uxQueueMessagesWaiting_Priv:
+ b MPU_uxQueueMessagesWaitingImpl
+ MPU_uxQueueMessagesWaiting_Unpriv:
+ svc #SYSTEM_CALL_uxQueueMessagesWaiting
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_uxQueueSpacesAvailable
+MPU_uxQueueSpacesAvailable:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_uxQueueSpacesAvailable_Unpriv
+ MPU_uxQueueSpacesAvailable_Priv:
+ b MPU_uxQueueSpacesAvailableImpl
+ MPU_uxQueueSpacesAvailable_Unpriv:
+ svc #SYSTEM_CALL_uxQueueSpacesAvailable
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xQueueReceive
+MPU_xQueueReceive:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xQueueReceive_Unpriv
+ MPU_xQueueReceive_Priv:
+ b MPU_xQueueReceiveImpl
+ MPU_xQueueReceive_Unpriv:
+ svc #SYSTEM_CALL_xQueueReceive
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xQueuePeek
+MPU_xQueuePeek:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xQueuePeek_Unpriv
+ MPU_xQueuePeek_Priv:
+ b MPU_xQueuePeekImpl
+ MPU_xQueuePeek_Unpriv:
+ svc #SYSTEM_CALL_xQueuePeek
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xQueueSemaphoreTake
+MPU_xQueueSemaphoreTake:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xQueueSemaphoreTake_Unpriv
+ MPU_xQueueSemaphoreTake_Priv:
+ b MPU_xQueueSemaphoreTakeImpl
+ MPU_xQueueSemaphoreTake_Unpriv:
+ svc #SYSTEM_CALL_xQueueSemaphoreTake
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xQueueGetMutexHolder
+MPU_xQueueGetMutexHolder:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xQueueGetMutexHolder_Unpriv
+ MPU_xQueueGetMutexHolder_Priv:
+ b MPU_xQueueGetMutexHolderImpl
+ MPU_xQueueGetMutexHolder_Unpriv:
+ svc #SYSTEM_CALL_xQueueGetMutexHolder
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xQueueTakeMutexRecursive
+MPU_xQueueTakeMutexRecursive:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xQueueTakeMutexRecursive_Unpriv
+ MPU_xQueueTakeMutexRecursive_Priv:
+ b MPU_xQueueTakeMutexRecursiveImpl
+ MPU_xQueueTakeMutexRecursive_Unpriv:
+ svc #SYSTEM_CALL_xQueueTakeMutexRecursive
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xQueueGiveMutexRecursive
+MPU_xQueueGiveMutexRecursive:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xQueueGiveMutexRecursive_Unpriv
+ MPU_xQueueGiveMutexRecursive_Priv:
+ b MPU_xQueueGiveMutexRecursiveImpl
+ MPU_xQueueGiveMutexRecursive_Unpriv:
+ svc #SYSTEM_CALL_xQueueGiveMutexRecursive
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xQueueSelectFromSet
+MPU_xQueueSelectFromSet:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xQueueSelectFromSet_Unpriv
+ MPU_xQueueSelectFromSet_Priv:
+ b MPU_xQueueSelectFromSetImpl
+ MPU_xQueueSelectFromSet_Unpriv:
+ svc #SYSTEM_CALL_xQueueSelectFromSet
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xQueueAddToSet
+MPU_xQueueAddToSet:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xQueueAddToSet_Unpriv
+ MPU_xQueueAddToSet_Priv:
+ b MPU_xQueueAddToSetImpl
+ MPU_xQueueAddToSet_Unpriv:
+ svc #SYSTEM_CALL_xQueueAddToSet
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vQueueAddToRegistry
+MPU_vQueueAddToRegistry:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vQueueAddToRegistry_Unpriv
+ MPU_vQueueAddToRegistry_Priv:
+ b MPU_vQueueAddToRegistryImpl
+ MPU_vQueueAddToRegistry_Unpriv:
+ svc #SYSTEM_CALL_vQueueAddToRegistry
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vQueueUnregisterQueue
+MPU_vQueueUnregisterQueue:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vQueueUnregisterQueue_Unpriv
+ MPU_vQueueUnregisterQueue_Priv:
+ b MPU_vQueueUnregisterQueueImpl
+ MPU_vQueueUnregisterQueue_Unpriv:
+ svc #SYSTEM_CALL_vQueueUnregisterQueue
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_pcQueueGetName
+MPU_pcQueueGetName:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_pcQueueGetName_Unpriv
+ MPU_pcQueueGetName_Priv:
+ b MPU_pcQueueGetNameImpl
+ MPU_pcQueueGetName_Unpriv:
+ svc #SYSTEM_CALL_pcQueueGetName
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_pvTimerGetTimerID
+MPU_pvTimerGetTimerID:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_pvTimerGetTimerID_Unpriv
+ MPU_pvTimerGetTimerID_Priv:
+ b MPU_pvTimerGetTimerIDImpl
+ MPU_pvTimerGetTimerID_Unpriv:
+ svc #SYSTEM_CALL_pvTimerGetTimerID
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vTimerSetTimerID
+MPU_vTimerSetTimerID:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vTimerSetTimerID_Unpriv
+ MPU_vTimerSetTimerID_Priv:
+ b MPU_vTimerSetTimerIDImpl
+ MPU_vTimerSetTimerID_Unpriv:
+ svc #SYSTEM_CALL_vTimerSetTimerID
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTimerIsTimerActive
+MPU_xTimerIsTimerActive:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTimerIsTimerActive_Unpriv
+ MPU_xTimerIsTimerActive_Priv:
+ b MPU_xTimerIsTimerActiveImpl
+ MPU_xTimerIsTimerActive_Unpriv:
+ svc #SYSTEM_CALL_xTimerIsTimerActive
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
+MPU_xTimerGetTimerDaemonTaskHandle:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
+ MPU_xTimerGetTimerDaemonTaskHandle_Priv:
+ b MPU_xTimerGetTimerDaemonTaskHandleImpl
+ MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
+ svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTimerGenericCommandFromTask_Unpriv
+ MPU_xTimerGenericCommandFromTask_Priv:
+ b MPU_xTimerGenericCommandFromTaskImpl
+ MPU_xTimerGenericCommandFromTask_Unpriv:
+ svc #SYSTEM_CALL_xTimerGenericCommandFromTask
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_pcTimerGetName
+MPU_pcTimerGetName:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_pcTimerGetName_Unpriv
+ MPU_pcTimerGetName_Priv:
+ b MPU_pcTimerGetNameImpl
+ MPU_pcTimerGetName_Unpriv:
+ svc #SYSTEM_CALL_pcTimerGetName
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vTimerSetReloadMode
+MPU_vTimerSetReloadMode:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vTimerSetReloadMode_Unpriv
+ MPU_vTimerSetReloadMode_Priv:
+ b MPU_vTimerSetReloadModeImpl
+ MPU_vTimerSetReloadMode_Unpriv:
+ svc #SYSTEM_CALL_vTimerSetReloadMode
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTimerGetReloadMode
+MPU_xTimerGetReloadMode:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTimerGetReloadMode_Unpriv
+ MPU_xTimerGetReloadMode_Priv:
+ b MPU_xTimerGetReloadModeImpl
+ MPU_xTimerGetReloadMode_Unpriv:
+ svc #SYSTEM_CALL_xTimerGetReloadMode
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_uxTimerGetReloadMode
+MPU_uxTimerGetReloadMode:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_uxTimerGetReloadMode_Unpriv
+ MPU_uxTimerGetReloadMode_Priv:
+ b MPU_uxTimerGetReloadModeImpl
+ MPU_uxTimerGetReloadMode_Unpriv:
+ svc #SYSTEM_CALL_uxTimerGetReloadMode
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTimerGetPeriod
+MPU_xTimerGetPeriod:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTimerGetPeriod_Unpriv
+ MPU_xTimerGetPeriod_Priv:
+ b MPU_xTimerGetPeriodImpl
+ MPU_xTimerGetPeriod_Unpriv:
+ svc #SYSTEM_CALL_xTimerGetPeriod
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTimerGetExpiryTime
+MPU_xTimerGetExpiryTime:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTimerGetExpiryTime_Unpriv
+ MPU_xTimerGetExpiryTime_Priv:
+ b MPU_xTimerGetExpiryTimeImpl
+ MPU_xTimerGetExpiryTime_Unpriv:
+ svc #SYSTEM_CALL_xTimerGetExpiryTime
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xEventGroupWaitBitsEntry
+MPU_xEventGroupWaitBitsEntry:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xEventGroupWaitBits_Unpriv
+ MPU_xEventGroupWaitBits_Priv:
+ b MPU_xEventGroupWaitBitsImpl
+ MPU_xEventGroupWaitBits_Unpriv:
+ svc #SYSTEM_CALL_xEventGroupWaitBits
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xEventGroupClearBits
+MPU_xEventGroupClearBits:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xEventGroupClearBits_Unpriv
+ MPU_xEventGroupClearBits_Priv:
+ b MPU_xEventGroupClearBitsImpl
+ MPU_xEventGroupClearBits_Unpriv:
+ svc #SYSTEM_CALL_xEventGroupClearBits
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xEventGroupSetBits
+MPU_xEventGroupSetBits:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xEventGroupSetBits_Unpriv
+ MPU_xEventGroupSetBits_Priv:
+ b MPU_xEventGroupSetBitsImpl
+ MPU_xEventGroupSetBits_Unpriv:
+ svc #SYSTEM_CALL_xEventGroupSetBits
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xEventGroupSync
+MPU_xEventGroupSync:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xEventGroupSync_Unpriv
+ MPU_xEventGroupSync_Priv:
+ b MPU_xEventGroupSyncImpl
+ MPU_xEventGroupSync_Unpriv:
+ svc #SYSTEM_CALL_xEventGroupSync
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_uxEventGroupGetNumber
+MPU_uxEventGroupGetNumber:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_uxEventGroupGetNumber_Unpriv
+ MPU_uxEventGroupGetNumber_Priv:
+ b MPU_uxEventGroupGetNumberImpl
+ MPU_uxEventGroupGetNumber_Unpriv:
+ svc #SYSTEM_CALL_uxEventGroupGetNumber
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vEventGroupSetNumber
+MPU_vEventGroupSetNumber:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vEventGroupSetNumber_Unpriv
+ MPU_vEventGroupSetNumber_Priv:
+ b MPU_vEventGroupSetNumberImpl
+ MPU_vEventGroupSetNumber_Unpriv:
+ svc #SYSTEM_CALL_vEventGroupSetNumber
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xStreamBufferSend
+MPU_xStreamBufferSend:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xStreamBufferSend_Unpriv
+ MPU_xStreamBufferSend_Priv:
+ b MPU_xStreamBufferSendImpl
+ MPU_xStreamBufferSend_Unpriv:
+ svc #SYSTEM_CALL_xStreamBufferSend
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xStreamBufferReceive
+MPU_xStreamBufferReceive:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xStreamBufferReceive_Unpriv
+ MPU_xStreamBufferReceive_Priv:
+ b MPU_xStreamBufferReceiveImpl
+ MPU_xStreamBufferReceive_Unpriv:
+ svc #SYSTEM_CALL_xStreamBufferReceive
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xStreamBufferIsFull
+MPU_xStreamBufferIsFull:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xStreamBufferIsFull_Unpriv
+ MPU_xStreamBufferIsFull_Priv:
+ b MPU_xStreamBufferIsFullImpl
+ MPU_xStreamBufferIsFull_Unpriv:
+ svc #SYSTEM_CALL_xStreamBufferIsFull
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xStreamBufferIsEmpty
+MPU_xStreamBufferIsEmpty:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xStreamBufferIsEmpty_Unpriv
+ MPU_xStreamBufferIsEmpty_Priv:
+ b MPU_xStreamBufferIsEmptyImpl
+ MPU_xStreamBufferIsEmpty_Unpriv:
+ svc #SYSTEM_CALL_xStreamBufferIsEmpty
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xStreamBufferSpacesAvailable
+MPU_xStreamBufferSpacesAvailable:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xStreamBufferSpacesAvailable_Unpriv
+ MPU_xStreamBufferSpacesAvailable_Priv:
+ b MPU_xStreamBufferSpacesAvailableImpl
+ MPU_xStreamBufferSpacesAvailable_Unpriv:
+ svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xStreamBufferBytesAvailable
+MPU_xStreamBufferBytesAvailable:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xStreamBufferBytesAvailable_Unpriv
+ MPU_xStreamBufferBytesAvailable_Priv:
+ b MPU_xStreamBufferBytesAvailableImpl
+ MPU_xStreamBufferBytesAvailable_Unpriv:
+ svc #SYSTEM_CALL_xStreamBufferBytesAvailable
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xStreamBufferSetTriggerLevel
+MPU_xStreamBufferSetTriggerLevel:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xStreamBufferSetTriggerLevel_Unpriv
+ MPU_xStreamBufferSetTriggerLevel_Priv:
+ b MPU_xStreamBufferSetTriggerLevelImpl
+ MPU_xStreamBufferSetTriggerLevel_Unpriv:
+ svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xStreamBufferNextMessageLengthBytes
+MPU_xStreamBufferNextMessageLengthBytes:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
+ MPU_xStreamBufferNextMessageLengthBytes_Priv:
+ b MPU_xStreamBufferNextMessageLengthBytesImpl
+ MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
+ svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
+/*-----------------------------------------------------------*/
+
+/* Default weak implementations in case one is not available from
+ * mpu_wrappers because of config options. */
+
+ PUBWEAK MPU_xTaskDelayUntilImpl
+MPU_xTaskDelayUntilImpl:
+ b MPU_xTaskDelayUntilImpl
+
+ PUBWEAK MPU_xTaskAbortDelayImpl
+MPU_xTaskAbortDelayImpl:
+ b MPU_xTaskAbortDelayImpl
+
+ PUBWEAK MPU_vTaskDelayImpl
+MPU_vTaskDelayImpl:
+ b MPU_vTaskDelayImpl
+
+ PUBWEAK MPU_uxTaskPriorityGetImpl
+MPU_uxTaskPriorityGetImpl:
+ b MPU_uxTaskPriorityGetImpl
+
+ PUBWEAK MPU_eTaskGetStateImpl
+MPU_eTaskGetStateImpl:
+ b MPU_eTaskGetStateImpl
+
+ PUBWEAK MPU_vTaskGetInfoImpl
+MPU_vTaskGetInfoImpl:
+ b MPU_vTaskGetInfoImpl
+
+ PUBWEAK MPU_xTaskGetIdleTaskHandleImpl
+MPU_xTaskGetIdleTaskHandleImpl:
+ b MPU_xTaskGetIdleTaskHandleImpl
+
+ PUBWEAK MPU_vTaskSuspendImpl
+MPU_vTaskSuspendImpl:
+ b MPU_vTaskSuspendImpl
+
+ PUBWEAK MPU_vTaskResumeImpl
+MPU_vTaskResumeImpl:
+ b MPU_vTaskResumeImpl
+
+ PUBWEAK MPU_xTaskGetTickCountImpl
+MPU_xTaskGetTickCountImpl:
+ b MPU_xTaskGetTickCountImpl
+
+ PUBWEAK MPU_uxTaskGetNumberOfTasksImpl
+MPU_uxTaskGetNumberOfTasksImpl:
+ b MPU_uxTaskGetNumberOfTasksImpl
+
+ PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
+MPU_ulTaskGetRunTimeCounterImpl:
+ b MPU_ulTaskGetRunTimeCounterImpl
+
+ PUBWEAK MPU_ulTaskGetRunTimePercentImpl
+MPU_ulTaskGetRunTimePercentImpl:
+ b MPU_ulTaskGetRunTimePercentImpl
+
+ PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl
+MPU_ulTaskGetIdleRunTimePercentImpl:
+ b MPU_ulTaskGetIdleRunTimePercentImpl
+
+ PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl
+MPU_ulTaskGetIdleRunTimeCounterImpl:
+ b MPU_ulTaskGetIdleRunTimeCounterImpl
+
+ PUBWEAK MPU_vTaskSetApplicationTaskTagImpl
+MPU_vTaskSetApplicationTaskTagImpl:
+ b MPU_vTaskSetApplicationTaskTagImpl
+
+ PUBWEAK MPU_xTaskGetApplicationTaskTagImpl
+MPU_xTaskGetApplicationTaskTagImpl:
+ b MPU_xTaskGetApplicationTaskTagImpl
+
+ PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl
+MPU_vTaskSetThreadLocalStoragePointerImpl:
+ b MPU_vTaskSetThreadLocalStoragePointerImpl
+
+ PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl
+MPU_pvTaskGetThreadLocalStoragePointerImpl:
+ b MPU_pvTaskGetThreadLocalStoragePointerImpl
+
+ PUBWEAK MPU_uxTaskGetSystemStateImpl
+MPU_uxTaskGetSystemStateImpl:
+ b MPU_uxTaskGetSystemStateImpl
+
+ PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl
+MPU_uxTaskGetStackHighWaterMarkImpl:
+ b MPU_uxTaskGetStackHighWaterMarkImpl
+
+ PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl
+MPU_uxTaskGetStackHighWaterMark2Impl:
+ b MPU_uxTaskGetStackHighWaterMark2Impl
+
+ PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl
+MPU_xTaskGetCurrentTaskHandleImpl:
+ b MPU_xTaskGetCurrentTaskHandleImpl
+
+ PUBWEAK MPU_xTaskGetSchedulerStateImpl
+MPU_xTaskGetSchedulerStateImpl:
+ b MPU_xTaskGetSchedulerStateImpl
+
+ PUBWEAK MPU_vTaskSetTimeOutStateImpl
+MPU_vTaskSetTimeOutStateImpl:
+ b MPU_vTaskSetTimeOutStateImpl
+
+ PUBWEAK MPU_xTaskCheckForTimeOutImpl
+MPU_xTaskCheckForTimeOutImpl:
+ b MPU_xTaskCheckForTimeOutImpl
+
+ PUBWEAK MPU_xTaskGenericNotifyImpl
+MPU_xTaskGenericNotifyImpl:
+ b MPU_xTaskGenericNotifyImpl
+
+ PUBWEAK MPU_xTaskGenericNotifyWaitImpl
+MPU_xTaskGenericNotifyWaitImpl:
+ b MPU_xTaskGenericNotifyWaitImpl
+
+ PUBWEAK MPU_ulTaskGenericNotifyTakeImpl
+MPU_ulTaskGenericNotifyTakeImpl:
+ b MPU_ulTaskGenericNotifyTakeImpl
+
+ PUBWEAK MPU_xTaskGenericNotifyStateClearImpl
+MPU_xTaskGenericNotifyStateClearImpl:
+ b MPU_xTaskGenericNotifyStateClearImpl
+
+ PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl
+MPU_ulTaskGenericNotifyValueClearImpl:
+ b MPU_ulTaskGenericNotifyValueClearImpl
+
+ PUBWEAK MPU_xQueueGenericSendImpl
+MPU_xQueueGenericSendImpl:
+ b MPU_xQueueGenericSendImpl
+
+ PUBWEAK MPU_uxQueueMessagesWaitingImpl
+MPU_uxQueueMessagesWaitingImpl:
+ b MPU_uxQueueMessagesWaitingImpl
+
+ PUBWEAK MPU_uxQueueSpacesAvailableImpl
+MPU_uxQueueSpacesAvailableImpl:
+ b MPU_uxQueueSpacesAvailableImpl
+
+ PUBWEAK MPU_xQueueReceiveImpl
+MPU_xQueueReceiveImpl:
+ b MPU_xQueueReceiveImpl
+
+ PUBWEAK MPU_xQueuePeekImpl
+MPU_xQueuePeekImpl:
+ b MPU_xQueuePeekImpl
+
+ PUBWEAK MPU_xQueueSemaphoreTakeImpl
+MPU_xQueueSemaphoreTakeImpl:
+ b MPU_xQueueSemaphoreTakeImpl
+
+ PUBWEAK MPU_xQueueGetMutexHolderImpl
+MPU_xQueueGetMutexHolderImpl:
+ b MPU_xQueueGetMutexHolderImpl
+
+ PUBWEAK MPU_xQueueTakeMutexRecursiveImpl
+MPU_xQueueTakeMutexRecursiveImpl:
+ b MPU_xQueueTakeMutexRecursiveImpl
+
+ PUBWEAK MPU_xQueueGiveMutexRecursiveImpl
+MPU_xQueueGiveMutexRecursiveImpl:
+ b MPU_xQueueGiveMutexRecursiveImpl
+
+ PUBWEAK MPU_xQueueSelectFromSetImpl
+MPU_xQueueSelectFromSetImpl:
+ b MPU_xQueueSelectFromSetImpl
+
+ PUBWEAK MPU_xQueueAddToSetImpl
+MPU_xQueueAddToSetImpl:
+ b MPU_xQueueAddToSetImpl
+
+ PUBWEAK MPU_vQueueAddToRegistryImpl
+MPU_vQueueAddToRegistryImpl:
+ b MPU_vQueueAddToRegistryImpl
+
+ PUBWEAK MPU_vQueueUnregisterQueueImpl
+MPU_vQueueUnregisterQueueImpl:
+ b MPU_vQueueUnregisterQueueImpl
+
+ PUBWEAK MPU_pcQueueGetNameImpl
+MPU_pcQueueGetNameImpl:
+ b MPU_pcQueueGetNameImpl
+
+ PUBWEAK MPU_pvTimerGetTimerIDImpl
+MPU_pvTimerGetTimerIDImpl:
+ b MPU_pvTimerGetTimerIDImpl
+
+ PUBWEAK MPU_vTimerSetTimerIDImpl
+MPU_vTimerSetTimerIDImpl:
+ b MPU_vTimerSetTimerIDImpl
+
+ PUBWEAK MPU_xTimerIsTimerActiveImpl
+MPU_xTimerIsTimerActiveImpl:
+ b MPU_xTimerIsTimerActiveImpl
+
+ PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl
+MPU_xTimerGetTimerDaemonTaskHandleImpl:
+ b MPU_xTimerGetTimerDaemonTaskHandleImpl
+
+ PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+ b MPU_xTimerGenericCommandFromTaskImpl
+
+ PUBWEAK MPU_pcTimerGetNameImpl
+MPU_pcTimerGetNameImpl:
+ b MPU_pcTimerGetNameImpl
+
+ PUBWEAK MPU_vTimerSetReloadModeImpl
+MPU_vTimerSetReloadModeImpl:
+ b MPU_vTimerSetReloadModeImpl
+
+ PUBWEAK MPU_xTimerGetReloadModeImpl
+MPU_xTimerGetReloadModeImpl:
+ b MPU_xTimerGetReloadModeImpl
+
+ PUBWEAK MPU_uxTimerGetReloadModeImpl
+MPU_uxTimerGetReloadModeImpl:
+ b MPU_uxTimerGetReloadModeImpl
+
+ PUBWEAK MPU_xTimerGetPeriodImpl
+MPU_xTimerGetPeriodImpl:
+ b MPU_xTimerGetPeriodImpl
+
+ PUBWEAK MPU_xTimerGetExpiryTimeImpl
+MPU_xTimerGetExpiryTimeImpl:
+ b MPU_xTimerGetExpiryTimeImpl
+
+ PUBWEAK MPU_xEventGroupWaitBitsImpl
+MPU_xEventGroupWaitBitsImpl:
+ b MPU_xEventGroupWaitBitsImpl
+
+ PUBWEAK MPU_xEventGroupClearBitsImpl
+MPU_xEventGroupClearBitsImpl:
+ b MPU_xEventGroupClearBitsImpl
+
+ PUBWEAK MPU_xEventGroupSetBitsImpl
+MPU_xEventGroupSetBitsImpl:
+ b MPU_xEventGroupSetBitsImpl
+
+ PUBWEAK MPU_xEventGroupSyncImpl
+MPU_xEventGroupSyncImpl:
+ b MPU_xEventGroupSyncImpl
+
+ PUBWEAK MPU_uxEventGroupGetNumberImpl
+MPU_uxEventGroupGetNumberImpl:
+ b MPU_uxEventGroupGetNumberImpl
+
+ PUBWEAK MPU_vEventGroupSetNumberImpl
+MPU_vEventGroupSetNumberImpl:
+ b MPU_vEventGroupSetNumberImpl
+
+ PUBWEAK MPU_xStreamBufferSendImpl
+MPU_xStreamBufferSendImpl:
+ b MPU_xStreamBufferSendImpl
+
+ PUBWEAK MPU_xStreamBufferReceiveImpl
+MPU_xStreamBufferReceiveImpl:
+ b MPU_xStreamBufferReceiveImpl
+
+ PUBWEAK MPU_xStreamBufferIsFullImpl
+MPU_xStreamBufferIsFullImpl:
+ b MPU_xStreamBufferIsFullImpl
+
+ PUBWEAK MPU_xStreamBufferIsEmptyImpl
+MPU_xStreamBufferIsEmptyImpl:
+ b MPU_xStreamBufferIsEmptyImpl
+
+ PUBWEAK MPU_xStreamBufferSpacesAvailableImpl
+MPU_xStreamBufferSpacesAvailableImpl:
+ b MPU_xStreamBufferSpacesAvailableImpl
+
+ PUBWEAK MPU_xStreamBufferBytesAvailableImpl
+MPU_xStreamBufferBytesAvailableImpl:
+ b MPU_xStreamBufferBytesAvailableImpl
+
+ PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl
+MPU_xStreamBufferSetTriggerLevelImpl:
+ b MPU_xStreamBufferSetTriggerLevelImpl
+
+ PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl
+MPU_xStreamBufferNextMessageLengthBytesImpl:
+ b MPU_xStreamBufferNextMessageLengthBytesImpl
+
+/*-----------------------------------------------------------*/
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+ END
diff --git a/portable/IAR/ARM_CM52/non_secure/port.c b/portable/IAR/ARM_CM52/non_secure/port.c
new file mode 100644
index 0000000..76d2b24
--- /dev/null
+++ b/portable/IAR/ARM_CM52/non_secure/port.c
@@ -0,0 +1,2280 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU includes. */
+#include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if ( configENABLE_TRUSTZONE == 1 )
+ /* Secure components includes. */
+ #include "secure_context.h"
+ #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration settings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+ #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+ #define portUSE_PSPLIM_REGISTER 0
+#else
+ #define portUSE_PSPLIM_REGISTER 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
+#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
+#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used during system call enter and exit.
+ */
+#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE ( 3UL )
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS ( 20UL )
+#define portCPACR_CP11_POS ( 22UL )
+
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS ( 31UL )
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS ( 30UL )
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Offsets in the stack to the parameters when inside the SVC handler.
+ */
+#define portOFFSET_TO_LR ( 5 )
+#define portOFFSET_TO_PC ( 6 )
+#define portOFFSET_TO_PSR ( 7 )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
+
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+
+ /* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+ #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE_BIT ( 1UL << 0UL )
+
+/* Extract first address of the MPU region as encoded in the
+ * RBAR (Region Base Address Register) value. */
+#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
+ ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK )
+
+/* Extract last address of the MPU region as encoded in the
+ * RLAR (Region Limit Address Register) value. */
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
+ ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
+
+/* Does addr lies within [start, end] address range? */
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
+ ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
+
+/* Is the access request satisfied by the available permissions? */
+#define portIS_AUTHORIZED( accessRequest, permissions ) \
+ ( ( ( permissions ) & ( accessRequest ) ) == accessRequest )
+
+/* Max value that fits in a uint32_t type. */
+#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The maximum 24-bit number.
+ *
+ * It is needed because the systick is a 24-bit counter.
+ */
+#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
+
+/**
+ * @brief A fiddle factor to estimate the number of SysTick counts that would
+ * have occurred while the SysTick counter is stopped during tickless idle
+ * calculations.
+ */
+#define portMISSED_COUNTS_FACTOR ( 94UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR ( 0x01000000 )
+
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF FD
+ * 1111 1111 1111 1111 1111 1111 1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )
+#else
+
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF BC
+ * 1111 1111 1111 1111 1111 1111 1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ * Bit[0] = 0 ==> The task is privileged.
+ * Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
+
+/**
+ * @brief Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register.
+ */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS 1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT 0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+ #define portCONTROL_UPAC_EN ( 1UL << 7UL )
+ #define portCONTROL_PAC_EN ( 1UL << 6UL )
+ #define portCONTROL_UBTI_EN ( 1UL << 5UL )
+ #define portCONTROL_BTI_EN ( 1UL << 4UL )
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief Extract MPU region's access permissions from the Region Base Address
+ * Register (RBAR) value.
+ *
+ * @param ulRBARValue RBAR value for the MPU region.
+ *
+ * @return uint32_t Access permissions.
+ */
+ static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
+
+#if ( configENABLE_MPU == 1 )
+
+ /**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_FPU == 1 )
+
+ /**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ /**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ *
+ * The implementation in this file is weak to allow application writers to
+ * change the timer used to generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether the current execution context is interrupt.
+ *
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE
+ * otherwise.
+ */
+BaseType_t xPortIsInsideInterrupt( void );
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
+ */
+ void vSystemCallEnter( uint32_t * pulTaskStack,
+ uint32_t ulLR,
+ uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief Raise SVC for exiting from a system call.
+ */
+ void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+ void vSystemCallExit( uint32_t * pulSystemCallStack,
+ uint32_t ulLR ) PRIVILEGED_FUNCTION;
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+#if ( configENABLE_MPU == 1 )
+
+ /**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+ PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if ( configENABLE_TRUSTZONE == 1 )
+
+ /**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+ PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+ /**
+ * @brief The number of SysTick increments that make up one tick period.
+ */
+ PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
+
+ /**
+ * @brief The maximum number of tick periods that can be suppressed is
+ * limited by the 24 bit resolution of the SysTick timer.
+ */
+ PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
+
+ /**
+ * @brief Compensate for the CPU cycles that pass while the SysTick is
+ * stopped (low power functionality only).
+ */
+ PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+ __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+ {
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
+ TickType_t xModifiableIdleTime;
+
+ /* Make sure the SysTick reload value does not overflow the counter. */
+ if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+ {
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+ }
+
+ /* Enter a critical section but don't use the taskENTER_CRITICAL()
+ * method as that will mask interrupts that should exit sleep mode. */
+ __asm volatile ( "cpsid i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* If a context switch is pending or a task is waiting for the scheduler
+ * to be unsuspended then abandon the low power entry. */
+ if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+ {
+ /* Re-enable interrupts - see comments above the cpsid instruction
+ * above. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ }
+ else
+ {
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
+ /* Set the new reload value. */
+ portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+ /* Clear the SysTick count flag and set the count value back to
+ * zero. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Restart SysTick. */
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+ * set its parameter to 0 to indicate that its implementation contains
+ * its own wait for interrupt or wait for event instruction, and so wfi
+ * should not be executed again. However, the original expected idle
+ * time variable must remain unmodified, so a copy is taken. */
+ xModifiableIdleTime = xExpectedIdleTime;
+ configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+ if( xModifiableIdleTime > 0 )
+ {
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "wfi" );
+ __asm volatile ( "isb" );
+ }
+
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+ /* Re-enable interrupts to allow the interrupt that brought the MCU
+ * out of sleep mode to execute immediately. See comments above
+ * the cpsid instruction above. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* Disable interrupts again because the clock is about to be stopped
+ * and interrupts that execute while the clock is stopped will increase
+ * any slippage between the time maintained by the RTOS and calendar
+ * time. */
+ __asm volatile ( "cpsid i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* Disable the SysTick clock without reading the
+ * portNVIC_SYSTICK_CTRL_REG register to ensure the
+ * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
+ * the time the SysTick is stopped for is accounted for as best it can
+ * be, but using the tickless mode will inevitably result in some tiny
+ * drift of the time maintained by the kernel with respect to calendar
+ * time*/
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Determine whether the SysTick has already counted to zero. */
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ uint32_t ulCalculatedLoadValue;
+
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+ /* Don't allow a tiny value, or values that have somehow
+ * underflowed because the post sleep hook did something
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ {
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+ /* As the pending tick will be processed as soon as this
+ * function exits, the tick value maintained by the tick is stepped
+ * forward by one less than the time spent waiting. */
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+ }
+ else
+ {
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
+ * periods (not the ulReload value which accounted for part
+ * ticks). */
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
+
+ /* How many complete tick periods passed while the processor
+ * was waiting? */
+ ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+ /* The reload value is set to whatever fraction of a single tick
+ * period remains. */
+ portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+ }
+
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
+ vTaskStepTick( ulCompleteTickPeriods );
+
+ /* Exit with interrupts enabled. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ }
+ }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Calculate the constants required to configure the tick interrupt. */
+ #if ( configUSE_TICKLESS_IDLE == 1 )
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
+ #endif /* configUSE_TICKLESS_IDLE */
+
+ /* Stop and reset SysTick.
+ *
+ * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+ * enable SysTick without first selecting a valid clock source. We trigger
+ * the bug if we change clock sources from a clock with a zero clock period
+ * to one with a nonzero clock period and enable Systick at the same time.
+ * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+ * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+ volatile uint32_t ulDummy = 0UL;
+
+ /* A function that implements a task must not exit or attempt to return to
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()
+ * to be triggered if configASSERT() is defined, then stop here so
+ * application writers can catch the error. */
+ configASSERT( ulCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+
+ while( ulDummy == 0 )
+ {
+ /* This file calls prvTaskExitError() after the scheduler has been
+ * started to remove a compiler warning about the function being
+ * defined but never called. ulDummy is used purely to quieten other
+ * warnings about code appearing after this function is called - making
+ * ulDummy volatile makes the compiler think the function could return
+ * and therefore not output an 'unreachable code' warning for code that
+ * appears after it. */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulAccessPermissions = 0;
+
+ if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY )
+ {
+ ulAccessPermissions = tskMPU_READ_PERMISSION;
+ }
+
+ if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE )
+ {
+ ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION );
+ }
+
+ return ulAccessPermissions;
+ }
+
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_functions_start__;
+ extern uint32_t * __privileged_functions_end__;
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ extern uint32_t * __unprivileged_flash_start__;
+ extern uint32_t * __unprivileged_flash_end__;
+ extern uint32_t * __privileged_sram_start__;
+ extern uint32_t * __privileged_sram_end__;
+ #else /* if defined( __ARMCC_VERSION ) */
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_functions_start__[];
+ extern uint32_t __privileged_functions_end__[];
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ extern uint32_t __unprivileged_flash_start__[];
+ extern uint32_t __unprivileged_flash_end__[];
+ extern uint32_t __privileged_sram_start__[];
+ extern uint32_t __privileged_sram_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+
+ /* The only permitted number of regions are 8 or 16. */
+ configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
+
+ /* MAIR0 - Index 0. */
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ /* MAIR0 - Index 1. */
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* Setup privileged flash as Read Only so that privileged tasks can
+ * read it but not modify. */
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged flash as Read Only by both privileged and
+ * unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged syscalls flash as Read Only by both privileged
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup RAM containing kernel data for privileged access only. */
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Enable mem fault. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
+
+ /* Enable MPU with privileged background access i.e. unmapped
+ * regions have privileged access. */
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
+ }
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_FPU == 1 )
+
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ /* Enable non-secure access to the FPU. */
+ SecureInit_EnableNSFPUAccess();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+ * unprivileged code should be able to access FPU. CP11 should be
+ * programmed to the same value as CP10. */
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+ );
+
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+ * context on exception entry and restore on exception return.
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+ }
+
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Set a PendSV to request a context switch. */
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ portDISABLE_INTERRUPTS();
+ ulCriticalNesting++;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ configASSERT( ulCriticalNesting );
+ ulCriticalNesting--;
+
+ if( ulCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+ uint32_t ulPreviousMask;
+
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ traceISR_EXIT_TO_SCHEDULER();
+ /* Pend a context switch. */
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+ }
+ else
+ {
+ traceISR_EXIT();
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ uint32_t ulPC;
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ uint32_t ulR0, ulR1;
+ extern TaskHandle_t pxCurrentTCB;
+ #if ( configENABLE_MPU == 1 )
+ uint32_t ulControl, ulIsTaskPrivileged;
+ #endif /* configENABLE_MPU */
+ #endif /* configENABLE_TRUSTZONE */
+ uint8_t ucSVCNumber;
+
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+ * R12, LR, PC, xPSR. */
+ ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ];
+ ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+ switch( ucSVCNumber )
+ {
+ #if ( configENABLE_TRUSTZONE == 1 )
+ case portSVC_ALLOCATE_SECURE_CONTEXT:
+
+ /* R0 contains the stack size passed as parameter to the
+ * vPortAllocateSecureContext function. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+
+ #if ( configENABLE_MPU == 1 )
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+ }
+ #else /* if ( configENABLE_MPU == 1 ) */
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+ }
+ #endif /* configENABLE_MPU */
+
+ configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+ SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+ break;
+
+ case portSVC_FREE_SECURE_CONTEXT:
+
+ /* R0 contains TCB being freed and R1 contains the secure
+ * context handle to be freed. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+ ulR1 = pulCallerStackAddress[ 1 ];
+
+ /* Free the secure context. */
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+ break;
+ #endif /* configENABLE_TRUSTZONE */
+
+ case portSVC_START_SCHEDULER:
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
+
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ #if ( configENABLE_FPU == 1 )
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
+ #endif /* configENABLE_FPU */
+
+ /* Setup the context of the first task so that the first task starts
+ * executing. */
+ vRestoreContextOfFirstTask();
+ break;
+
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ case portSVC_RAISE_PRIVILEGE:
+
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ vRaisePrivilege();
+ }
+ break;
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ #if ( configENABLE_MPU == 1 )
+ case portSVC_YIELD:
+ vPortYield();
+ break;
+ #endif /* configENABLE_MPU == 1 */
+
+ default:
+ /* Incorrect SVC call. */
+ configASSERT( pdFALSE );
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ void vSystemCallEnter( uint32_t * pulTaskStack,
+ uint32_t ulLR,
+ uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
+ {
+ extern TaskHandle_t pxCurrentTCB;
+ extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
+ xMPU_SETTINGS * pxMpuSettings;
+ uint32_t * pulSystemCallStack;
+ uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
+
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ #endif /* #if defined( __ARMCC_VERSION ) */
+
+ ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+ pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+
+ /* Checks:
+ * 1. SVC is raised from the system call section (i.e. application is
+ * not raising SVC directly).
+ * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+ * it is non-NULL only during the execution of a system call (i.e.
+ * between system call enter and exit).
+ * 3. System call is not for a kernel API disabled by the configuration
+ * in FreeRTOSConfig.h.
+ * 4. We do not need to check that ucSystemCallNumber is within range
+ * because the assembly SVC handler checks that before calling
+ * this function.
+ */
+ if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+ ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+ ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
+ {
+ pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+ /* Hardware Saved Stack Frame Size upon Exception entry:
+ * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+ * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+ */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ {
+ if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+ {
+ /* Extended frame i.e. FPU in use. */
+ ulHardwareSavedExceptionFrameSize = 26;
+ __asm volatile (
+ " vpush {s0} \n" /* Trigger lazy stacking. */
+ " vpop {s0} \n" /* Nullify the affect of the above instruction. */
+ ::: "memory"
+ );
+ }
+ else
+ {
+ /* Standard frame i.e. FPU not in use. */
+ ulHardwareSavedExceptionFrameSize = 8;
+ }
+ }
+ #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ {
+ ulHardwareSavedExceptionFrameSize = 8;
+ }
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+
+ /* Make space on the system call stack for the stack frame. */
+ pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
+
+ /* Copy the stack frame. */
+ for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
+ {
+ pulSystemCallStack[ i ] = pulTaskStack[ i ];
+ }
+
+ /* Store the value of the Link Register before the SVC was raised.
+ * It contains the address of the caller of the System Call entry
+ * point (i.e. the caller of the MPU_<API>). We need to restore it
+ * when we exit from the system call. */
+ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
+ /* Store the value of the PSPLIM register before the SVC was raised.
+ * We need to restore it when we exit from the system call. */
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
+
+ /* Use the pulSystemCallStack in thread mode. */
+ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ }
+ #endif
+
+ /* Start executing the system call upon returning from this handler. */
+ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
+ /* Raise a request to exit from the system call upon finishing the
+ * system call. */
+ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
+ /* Remember the location where we should copy the stack frame when we exit from
+ * the system call. */
+ pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
+
+ /* Record if the hardware used padding to force the stack pointer
+ * to be double word aligned. */
+ if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+ {
+ pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
+ }
+ else
+ {
+ pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
+ }
+
+ /* We ensure in pxPortInitialiseStack that the system call stack is
+ * double word aligned and therefore, there is no need of padding.
+ * Clear the bit[9] of stacked xPSR. */
+ pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+ /* Raise the privilege for the duration of the system call. */
+ __asm volatile (
+ " mrs r0, control \n" /* Obtain current control value. */
+ " movs r1, #1 \n" /* r1 = 1. */
+ " bics r0, r1 \n" /* Clear nPRIV bit. */
+ " msr control, r0 \n" /* Write back new control value. */
+ ::: "r0", "r1", "memory"
+ );
+ }
+ }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
+ }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ void vSystemCallExit( uint32_t * pulSystemCallStack,
+ uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+ {
+ extern TaskHandle_t pxCurrentTCB;
+ xMPU_SETTINGS * pxMpuSettings;
+ uint32_t * pulTaskStack;
+ uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
+
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_functions_start__;
+ extern uint32_t * __privileged_functions_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_functions_start__[];
+ extern uint32_t __privileged_functions_end__[];
+ #endif /* #if defined( __ARMCC_VERSION ) */
+
+ ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+ pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+
+ /* Checks:
+ * 1. SVC is raised from the privileged code (i.e. application is not
+ * raising SVC directly). This SVC is only raised from
+ * vRequestSystemCallExit which is in the privileged code section.
+ * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+ * this means that we previously entered a system call and the
+ * application is not attempting to exit without entering a system
+ * call.
+ */
+ if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+ ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+ ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
+ {
+ pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+ /* Hardware Saved Stack Frame Size upon Exception entry:
+ * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+ * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+ */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ {
+ if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+ {
+ /* Extended frame i.e. FPU in use. */
+ ulHardwareSavedExceptionFrameSize = 26;
+ __asm volatile (
+ " vpush {s0} \n" /* Trigger lazy stacking. */
+ " vpop {s0} \n" /* Nullify the affect of the above instruction. */
+ ::: "memory"
+ );
+ }
+ else
+ {
+ /* Standard frame i.e. FPU not in use. */
+ ulHardwareSavedExceptionFrameSize = 8;
+ }
+ }
+ #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ {
+ ulHardwareSavedExceptionFrameSize = 8;
+ }
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+
+ /* Make space on the task stack for the stack frame. */
+ pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
+
+ /* Copy the stack frame. */
+ for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
+ {
+ pulTaskStack[ i ] = pulSystemCallStack[ i ];
+ }
+
+ /* Use the pulTaskStack in thread mode. */
+ __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+ /* Return to the caller of the System Call entry point (i.e. the
+ * caller of the MPU_<API>). */
+ pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+ /* Ensure that LR has a valid value.*/
+ pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+ /* Restore the PSPLIM register to what it was at the time of
+ * system call entry. */
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
+
+ /* If the hardware used padding to force the stack pointer
+ * to be double word aligned, set the stacked xPSR bit[9],
+ * otherwise clear it. */
+ if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+ {
+ pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
+ }
+ else
+ {
+ pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+ }
+
+ /* This is not NULL only for the duration of the system call. */
+ pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+ /* Drop the privilege before returning to the thread mode. */
+ __asm volatile (
+ " mrs r0, control \n" /* Obtain current control value. */
+ " movs r1, #1 \n" /* r1 = 1. */
+ " orrs r0, r1 \n" /* Set nPRIV bit. */
+ " msr control, r0 \n" /* Write back new control value. */
+ ::: "r0", "r1", "memory"
+ );
+ }
+ }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
+ {
+ BaseType_t xTaskIsPrivileged = pdFALSE;
+ const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+ if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ {
+ xTaskIsPrivileged = pdTRUE;
+ }
+
+ return xTaskIsPrivileged;
+ }
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ StackType_t * pxEndOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters,
+ BaseType_t xRunPrivileged,
+ xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulIndex = 0;
+ uint32_t ulControl = 0x0;
+
+ xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+ ulIndex++;
+
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
+ ulIndex++;
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+ ulIndex++;
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
+ ulIndex++;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Check PACBTI security feature configuration before pushing the
+ * CONTROL register's value on task's TCB. */
+ ulControl = prvConfigurePACBTI( pdFALSE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
+ if( xRunPrivileged == pdTRUE )
+ {
+ xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
+ ulIndex++;
+ }
+ else
+ {
+ xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
+ ulIndex++;
+ }
+
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+ ulIndex++;
+
+ #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+ {
+ /* Ensure that the system call stack is double word aligned. */
+ xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+ xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+ ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+ xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+ xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+ ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+ ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+ /* This is not NULL only for the duration of a system call. */
+ xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+ }
+ #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+ ulIndex++;
+ }
+ }
+ #endif /* configENABLE_PAC */
+
+ return &( xMPUSettings->ulContext[ ulIndex ] );
+ }
+
+#else /* configENABLE_MPU */
+
+ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ StackType_t * pxEndOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters ) /* PRIVILEGED_FUNCTION */
+ {
+ /* Simulate the stack frame as it would be created by a context switch
+ * interrupt. */
+ #if ( portPRELOAD_REGISTERS == 0 )
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #else /* portPRELOAD_REGISTERS */
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #endif /* portPRELOAD_REGISTERS */
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = ulTaskPacKey[ i ];
+ }
+ }
+ #endif /* configENABLE_PAC */
+
+ return pxTopOfStack;
+ }
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+ * for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * SVC_Handler and PendSV_Handler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+ {
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+ {
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * First, determine the number of priority bits available. Write to all
+ * possible bits in the priority setting for SVCall. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Check that the bits not implemented in hardware are zero in
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
+
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
+ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+ portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Set the CONTROL register value based on PACBTI security feature
+ * configuration before starting the first task. */
+ ( void ) prvConfigurePACBTI( pdTRUE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
+ #if ( configENABLE_MPU == 1 )
+ {
+ /* Setup the Memory Protection Unit (MPU). */
+ prvSetupMPU();
+ }
+ #endif /* configENABLE_MPU */
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ * here already. */
+ vPortSetupTimerInterrupt();
+
+ /* Initialize the critical nesting count ready for the first task. */
+ ulCriticalNesting = 0;
+
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+ {
+ xSchedulerRunning = pdTRUE;
+ }
+ #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
+
+ /* Start the first task. */
+ vStartFirstTask();
+
+ /* Should never get here as the tasks will now be executing. Call the task
+ * exit error function to prevent compiler warnings about a static function
+ * not being called in the case that the application writer overrides this
+ * functionality by defining configTASK_RETURN_ADDRESS. Call
+ * vTaskSwitchContext() so link time optimization does not remove the
+ * symbol. */
+ vTaskSwitchContext();
+ prvTaskExitError();
+
+ /* Should not get here. */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Not implemented in ports where there is nothing to return to.
+ * Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+ const struct xMEMORY_REGION * const xRegions,
+ StackType_t * pxBottomOfStack,
+ configSTACK_DEPTH_TYPE uxStackDepth )
+ {
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+ int32_t lIndex = 0;
+
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_sram_start__;
+ extern uint32_t * __privileged_sram_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_sram_start__[];
+ extern uint32_t __privileged_sram_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+
+ /* Setup MAIR0. */
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* This function is called automatically when the task is created - in
+ * which case the stack region parameters will be valid. At all other
+ * times the stack parameters will not be valid and it is assumed that
+ * the stack region has already been configured. */
+ if( uxStackDepth > 0 )
+ {
+ ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
+
+ /* If the stack is within the privileged SRAM, do not protect it
+ * using a separate MPU region. This is needed because privileged
+ * SRAM is already protected using an MPU region and ARMv8-M does
+ * not allow overlapping MPU regions. */
+ if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+ ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
+ {
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
+ }
+ else
+ {
+ /* Define the region that allows access to the stack. */
+ ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+ }
+ }
+
+ /* User supplied configurable regions. */
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+ {
+ /* If xRegions is NULL i.e. the task has not specified any MPU
+ * region, the else part ensures that all the configurable MPU
+ * regions are invalidated. */
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+ {
+ /* Translate the generic region definition contained in xRegions
+ * into the ARMv8 specific MPU settings that are then stored in
+ * xMPUSettings. */
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ /* Start address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE );
+
+ /* RO/RW. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+ }
+ else
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+ }
+
+ /* XN. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+ }
+
+ /* End Address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* PXN. */
+ #if ( portARMV8M_MINOR_VERSION >= 1 )
+ {
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+ }
+ }
+ #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
+ /* Normal memory/ Device memory. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+ {
+ /* Attr1 in MAIR0 is configured as device memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+ }
+ else
+ {
+ /* Attr0 in MAIR0 is configured as normal memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+ }
+ }
+ else
+ {
+ /* Invalidate the region. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+ }
+
+ lIndex++;
+ }
+ }
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
+ uint32_t ulBufferLength,
+ uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
+
+ {
+ uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
+ BaseType_t xAccessGranted = pdFALSE;
+ const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ {
+ xAccessGranted = pdTRUE;
+ }
+ else
+ {
+ if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
+ {
+ ulBufferStartAddress = ( uint32_t ) pvBuffer;
+ ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
+
+ for( i = 0; i < portTOTAL_NUM_REGIONS; i++ )
+ {
+ /* Is the MPU region enabled? */
+ if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE )
+ {
+ if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
+ portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ),
+ portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) &&
+ portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
+ portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ),
+ portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) &&
+ portIS_AUTHORIZED( ulAccessRequested,
+ prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) )
+ {
+ xAccessGranted = pdTRUE;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ return xAccessGranted;
+ }
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortIsInsideInterrupt( void )
+{
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
+
+ /* Obtain the number of the currently executing interrupt. Interrupt Program
+ * Status Register (IPSR) holds the exception number of the currently-executing
+ * exception or zero for Thread mode.*/
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ if( ulCurrentInterrupt == 0 )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+ void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+ int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+ xMPU_SETTINGS * xTaskMpuSettings;
+
+ ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+ ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+ xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+ xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+ }
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+ void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+ int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+ xMPU_SETTINGS * xTaskMpuSettings;
+
+ ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+ ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+ xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+ xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+ }
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+ BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+ BaseType_t xAccessGranted = pdFALSE;
+ const xMPU_SETTINGS * xTaskMpuSettings;
+
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else
+ {
+ xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+ ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+ ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+ if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ {
+ xAccessGranted = pdTRUE;
+ }
+ else
+ {
+ if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+ {
+ xAccessGranted = pdTRUE;
+ }
+ }
+ }
+
+ return xAccessGranted;
+ }
+
+ #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+ BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+ {
+ ( void ) lInternalIndexOfKernelObject;
+
+ /* If Access Control List feature is not used, all the tasks have
+ * access to all the kernel objects. */
+ return pdTRUE;
+ }
+
+ #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+ {
+ uint32_t ulControl = 0x0;
+
+ /* Ensure that PACBTI is implemented. */
+ configASSERT( portID_ISAR5_REG != 0x0 );
+
+ /* Enable UsageFault exception. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+ }
+ #endif
+
+ #if ( configENABLE_BTI == 1 )
+ {
+ ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+ }
+ #endif
+
+ if( xWriteControlRegister == pdTRUE )
+ {
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+ }
+
+ return ulControl;
+ }
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM52/non_secure/portasm.h b/portable/IAR/ARM_CM52/non_secure/portasm.h
new file mode 100644
index 0000000..b7021b0
--- /dev/null
+++ b/portable/IAR/ARM_CM52/non_secure/portasm.h
@@ -0,0 +1,114 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kernel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/portable/IAR/ARM_CM52/non_secure/portasm.s b/portable/IAR/ARM_CM52/non_secure/portasm.s
new file mode 100644
index 0000000..8d59888
--- /dev/null
+++ b/portable/IAR/ARM_CM52/non_secure/portasm.s
@@ -0,0 +1,543 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+/* Including FreeRTOSConfig.h here will cause build errors if the header file
+contains code not understood by the assembler - for example the 'extern' keyword.
+To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
+the code is included in C files but excluded by the preprocessor in assembly
+files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
+#include "FreeRTOSConfig.h"
+
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
+#ifndef configUSE_MPU_WRAPPERS_V1
+ #define configUSE_MPU_WRAPPERS_V1 0
+#endif
+
+ EXTERN pxCurrentTCB
+ EXTERN xSecureContext
+ EXTERN vTaskSwitchContext
+ EXTERN vPortSVCHandler_C
+ EXTERN SecureContext_SaveContext
+ EXTERN SecureContext_LoadContext
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+ EXTERN vSystemCallEnter
+ EXTERN vSystemCallExit
+#endif
+
+ PUBLIC xIsPrivileged
+ PUBLIC vResetPrivilege
+ PUBLIC vPortAllocateSecureContext
+ PUBLIC vRestoreContextOfFirstTask
+ PUBLIC vRaisePrivilege
+ PUBLIC vStartFirstTask
+ PUBLIC ulSetInterruptMask
+ PUBLIC vClearInterruptMask
+ PUBLIC PendSV_Handler
+ PUBLIC SVC_Handler
+ PUBLIC vPortFreeSecureContext
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+ SECTION .text:CODE:NOROOT(2)
+ THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+ mrs r0, control /* r0 = CONTROL. */
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ ite ne
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
+ bx lr /* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+ mrs r0, control /* r0 = CONTROL. */
+ orr r0, r0, #1 /* r0 = r0 | 1. */
+ msr control, r0 /* CONTROL = r0. */
+ bx lr /* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vPortAllocateSecureContext:
+ svc 100 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */
+ bx lr /* Return. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+ SECTION privileged_functions:CODE:NOROOT(2)
+ THUMB
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+vRestoreContextOfFirstTask:
+ program_mpu_first_task:
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r0, [r3] /* r0 = pxCurrentTCB. */
+
+ dmb /* Complete outstanding transfers before disabling MPU. */
+ ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r2, [r1] /* Read the value of MPU_CTRL. */
+ bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+ str r2, [r1] /* Disable MPU. */
+
+ adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+ ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ str r1, [r2] /* Program MAIR0. */
+
+ adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+ ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
+
+ movs r3, #4 /* r3 = 4. */
+ str r3, [r1] /* Program RNR = 4. */
+ ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */
+ stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ movs r3, #8 /* r3 = 8. */
+ str r3, [r1] /* Program RNR = 8. */
+ ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */
+ stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ movs r3, #12 /* r3 = 12. */
+ str r3, [r1] /* Program RNR = 12. */
+ ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */
+ stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ #endif /* configTOTAL_MPU_REGIONS == 16 */
+
+ ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r2, [r1] /* Read the value of MPU_CTRL. */
+ orr r2, #1 /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
+ str r2, [r1] /* Enable MPU. */
+ dsb /* Force memory writes before continuing. */
+
+ restore_context_first_task:
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r1, [r3] /* r1 = pxCurrentTCB.*/
+ ldr r2, [r1] /* r2 = Location of saved context in TCB. */
+
+ restore_special_regs_first_task:
+ #if ( configENABLE_PAC == 1 )
+ ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */
+ msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_1, r4
+ msr PAC_KEY_P_2, r5
+ msr PAC_KEY_P_3, r6
+ clrm {r3-r6} /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+ ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
+ msr psp, r3
+ msr psplim, r4
+ msr control, r5
+ ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ str r0, [r4] /* Restore xSecureContext. */
+
+ restore_general_regs_first_task:
+ ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */
+ stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */
+ ldmdb r2!, {r4-r11} /* r4-r11 restored. */
+
+ restore_context_done_first_task:
+ str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */
+ mov r0, #0
+ msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
+ bx lr
+
+#else /* configENABLE_MPU */
+
+vRestoreContextOfFirstTask:
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r3, [r2] /* Read pxCurrentTCB. */
+ ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_PAC == 1 )
+ ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */
+ msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_2, r2
+ msr PAC_KEY_P_1, r3
+ msr PAC_KEY_P_0, r4
+ clrm {r1-r4} /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
+ ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+ ldr r4, =xSecureContext
+ str r1, [r4] /* Set xSecureContext to this task's value for the same. */
+ msr psplim, r2 /* Set this task's PSPLIM value. */
+ mrs r1, control /* Obtain current control register value. */
+ orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
+ msr control, r1 /* Write back the new control register value. */
+ adds r0, #32 /* Discard everything up to r0. */
+ msr psp, r0 /* This is now the new top of stack to use in the task. */
+ isb
+ mov r0, #0
+ msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
+ bx r3 /* Finally, branch to EXC_RETURN. */
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+ mrs r0, control /* Read the CONTROL register. */
+ bic r0, r0, #1 /* Clear the bit 0. */
+ msr control, r0 /* Write back the new CONTROL value. */
+ bx lr /* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+ ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
+ ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
+ ldr r0, [r0] /* The first entry in vector table is stack pointer. */
+ msr msp, r0 /* Set the MSP back to the start of the stack. */
+ cpsie i /* Globally enable interrupts. */
+ cpsie f
+ dsb
+ isb
+ svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMask:
+ mrs r0, basepri /* r0 = basepri. Return original basepri value. */
+ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+ msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ dsb
+ isb
+ bx lr /* Return. */
+/*-----------------------------------------------------------*/
+
+vClearInterruptMask:
+ msr basepri, r0 /* basepri = ulMask. */
+ dsb
+ isb
+ bx lr /* Return. */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+PendSV_Handler:
+ ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+ ldr r2, [r1] /* r2 = Location in TCB where the context should be saved. */
+
+ cbz r0, save_ns_context /* No secure context to save. */
+ save_s_context:
+ push {r0-r2, lr}
+ bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ pop {r0-r2, lr}
+
+ save_ns_context:
+ mov r3, lr /* r3 = LR (EXC_RETURN). */
+ lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ bmi save_special_regs /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+
+ save_general_regs:
+ mrs r3, psp
+
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ add r3, r3, #0x20 /* Move r3 to location where s0 is saved. */
+ tst lr, #0x10
+ ittt eq
+ vstmiaeq r2!, {s16-s31} /* Store s16-s31. */
+ vldmiaeq r3, {s0-s16} /* Copy hardware saved FP context into s0-s16. */
+ vstmiaeq r2!, {s0-s16} /* Store hardware saved FP context. */
+ sub r3, r3, #0x20 /* Set r3 back to the location of hardware saved context. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+
+ stmia r2!, {r4-r11} /* Store r4-r11. */
+ ldmia r3, {r4-r11} /* Copy the hardware saved context into r4-r11. */
+ stmia r2!, {r4-r11} /* Store the hardware saved context. */
+
+ save_special_regs:
+ mrs r3, psp /* r3 = PSP. */
+ mrs r4, psplim /* r4 = PSPLIM. */
+ mrs r5, control /* r5 = CONTROL. */
+ stmia r2!, {r0, r3-r5, lr} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+ #if ( configENABLE_PAC == 1 )
+ mrs r3, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */
+ mrs r4, PAC_KEY_P_1
+ mrs r5, PAC_KEY_P_2
+ mrs r6, PAC_KEY_P_3
+ stmia r2!, {r3-r6} /* Store the task's dedicated PAC key on the task's context. */
+ clrm {r3-r6} /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+
+ str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */
+
+ select_next_task:
+ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+ msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ dsb
+ isb
+ bl vTaskSwitchContext
+ mov r0, #0 /* r0 = 0. */
+ msr basepri, r0 /* Enable interrupts. */
+
+ program_mpu:
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r0, [r3] /* r0 = pxCurrentTCB.*/
+
+ dmb /* Complete outstanding transfers before disabling MPU. */
+ ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r2, [r1] /* Read the value of MPU_CTRL. */
+ bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+ str r2, [r1] /* Disable MPU. */
+
+ adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+ ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ str r1, [r2] /* Program MAIR0. */
+
+ adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+ ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
+
+ movs r3, #4 /* r3 = 4. */
+ str r3, [r1] /* Program RNR = 4. */
+ ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ movs r3, #8 /* r3 = 8. */
+ str r3, [r1] /* Program RNR = 8. */
+ ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ movs r3, #12 /* r3 = 12. */
+ str r3, [r1] /* Program RNR = 12. */
+ ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ #endif /* configTOTAL_MPU_REGIONS == 16 */
+
+ ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r2, [r1] /* Read the value of MPU_CTRL. */
+ orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+ str r2, [r1] /* Enable MPU. */
+ dsb /* Force memory writes before continuing. */
+
+ restore_context:
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r1, [r3] /* r1 = pxCurrentTCB.*/
+ ldr r2, [r1] /* r2 = Location of saved context in TCB. */
+
+ restore_special_regs:
+ #if ( configENABLE_PAC == 1 )
+ ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */
+ msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_1, r4
+ msr PAC_KEY_P_2, r5
+ msr PAC_KEY_P_3, r6
+ clrm {r3-r6} /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+ ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
+ msr psp, r3
+ msr psplim, r4
+ msr control, r5
+ ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ str r0, [r4] /* Restore xSecureContext. */
+ cbz r0, restore_ns_context /* No secure context to restore. */
+
+ restore_s_context:
+ push {r1-r3, lr}
+ bl SecureContext_LoadContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ pop {r1-r3, lr}
+
+ restore_ns_context:
+ mov r0, lr /* r0 = LR (EXC_RETURN). */
+ lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+
+ restore_general_regs:
+ ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */
+ stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */
+ ldmdb r2!, {r4-r11} /* r4-r11 restored. */
+
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ tst lr, #0x10
+ ittt eq
+ vldmdbeq r2!, {s0-s16} /* s0-s16 contain hardware saved FP context. */
+ vstmiaeq r3!, {s0-s16} /* Copy hardware saved FP context on the task stack. */
+ vldmdbeq r2!, {s16-s31} /* Restore s16-s31. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+
+ restore_context_done:
+ str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */
+ bx lr
+
+#else /* configENABLE_MPU */
+
+PendSV_Handler:
+ ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+ mrs r2, psp /* Read PSP in r2. */
+
+ cbz r0, save_ns_context /* No secure context to save. */
+ save_s_context:
+ push {r0-r2, lr}
+ bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ pop {r0-r2, lr}
+
+ save_ns_context:
+ mov r3, lr /* r3 = LR. */
+ lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ bmi save_special_regs /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */
+
+ save_general_regs:
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ it eq
+ vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+ stmdb r2!, {r4-r11} /* Store the registers that are not saved automatically. */
+
+ save_special_regs:
+ mrs r3, psplim /* r3 = PSPLIM. */
+ stmdb r2!, {r0, r3, lr} /* Store xSecureContext, PSPLIM and LR on the stack. */
+ #if ( configENABLE_PAC == 1 )
+ mrs r3, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */
+ mrs r4, PAC_KEY_P_2
+ mrs r5, PAC_KEY_P_1
+ mrs r6, PAC_KEY_P_0
+ stmdb r2!, {r3-r6} /* Store the task's dedicated PAC key on the stack. */
+ clrm {r3-r6} /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+
+ str r2, [r1] /* Save the new top of stack in TCB. */
+
+ select_next_task:
+ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+ msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ dsb
+ isb
+ bl vTaskSwitchContext
+ mov r0, #0 /* r0 = 0. */
+ msr basepri, r0 /* Enable interrupts. */
+
+ restore_context:
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r1, [r3] /* Read pxCurrentTCB. */
+ ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+
+ restore_special_regs:
+ #if ( configENABLE_PAC == 1 )
+ ldmia r2!, {r3-r6} /* Read task's dedicated PAC key from stack. */
+ msr PAC_KEY_P_3, r3 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_2, r4
+ msr PAC_KEY_P_1, r5
+ msr PAC_KEY_P_0, r6
+ clrm {r3-r6} /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+ ldmia r2!, {r0, r3, lr} http://files.iar.com/ftp/pub/box/bxarm-9.60.3.deb/* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */
+ msr psplim, r3 /* Restore the PSPLIM register value for the task. */
+ ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ str r0, [r3] /* Restore the task's xSecureContext. */
+ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
+
+ restore_s_context:
+ push {r1-r3, lr}
+ bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ pop {r1-r3, lr}
+
+ restore_ns_context:
+ mov r0, lr /* r0 = LR (EXC_RETURN). */
+ lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+
+ restore_general_regs:
+ ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ it eq
+ vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+
+ restore_context_done:
+ msr psp, r2 /* Remember the new top of stack for the task. */
+ bx lr
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+SVC_Handler:
+ tst lr, #4
+ ite eq
+ mrseq r0, msp
+ mrsne r0, psp
+
+ ldr r1, [r0, #24]
+ ldrb r2, [r1, #-2]
+ cmp r2, #NUM_SYSTEM_CALLS
+ blt syscall_enter
+ cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */
+ beq syscall_exit
+ b vPortSVCHandler_C
+
+ syscall_enter:
+ mov r1, lr
+ b vSystemCallEnter
+
+ syscall_exit:
+ mov r1, lr
+ b vSystemCallExit
+
+#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+SVC_Handler:
+ tst lr, #4
+ ite eq
+ mrseq r0, msp
+ mrsne r0, psp
+ b vPortSVCHandler_C
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+vPortFreeSecureContext:
+ /* r0 = uint32_t *pulTCB. */
+ ldr r2, [r0] /* The first item in the TCB is the top of the stack. */
+ ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */
+ cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */
+ it ne
+ svcne 101 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */
+ bx lr /* Return. */
+/*-----------------------------------------------------------*/
+
+ END
diff --git a/portable/IAR/ARM_CM52/non_secure/portmacro.h b/portable/IAR/ARM_CM52/non_secure/portmacro.h
new file mode 100644
index 0000000..19de84e
--- /dev/null
+++ b/portable/IAR/ARM_CM52/non_secure/portmacro.h
@@ -0,0 +1,87 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright (c) 2025 Arm Technology (China) Co., Ltd.All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_MVE
+ #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.
+#endif /* configENABLE_MVE */
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME "Cortex-M52"
+#define portHAS_ARMV8M_MAIN_EXTENSION 1
+#define portARMV8M_MINOR_VERSION 1
+#define portDONT_DISCARD __root
+/*-----------------------------------------------------------*/
+
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+#pragma diag_suppress=Be006
+#pragma diag_suppress=Pa082
+/*-----------------------------------------------------------*/
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
diff --git a/portable/IAR/ARM_CM52/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM52/non_secure/portmacrocommon.h
new file mode 100644
index 0000000..f373bca
--- /dev/null
+++ b/portable/IAR/ARM_CM52/non_secure/portmacrocommon.h
@@ -0,0 +1,582 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern BaseType_t xPortIsInsideInterrupt( void );
+
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+ /**
+ * @brief Generates 128-bit task's random PAC key.
+ *
+ * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+ * filled with a 128-bit random number.
+ */
+ void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
+
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+ /* Define to 8 for backward compatibility. */
+ #define configTOTAL_MPU_REGIONS ( 8UL )
+#endif
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ * Bit[7:4] - 0000 - Device Memory
+ * Bit[3:2] - 00 --> Device-nGnRnE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
+ * Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ /**
+ * @brief Settings to define an MPU region.
+ */
+ typedef struct MPURegionSettings
+ {
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+ } MPURegionSettings_t;
+
+ #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+ #ifndef configSYSTEM_CALL_STACK_SIZE
+ #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
+ #endif
+
+ /**
+ * @brief System call stack.
+ */
+ typedef struct SYSTEM_CALL_STACK_INFO
+ {
+ uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
+ uint32_t * pulSystemCallStack;
+ uint32_t * pulSystemCallStackLimit;
+ uint32_t * pulTaskStack;
+ uint32_t ulLinkRegisterAtSystemCallEntry;
+ uint32_t ulStackLimitRegisterAtSystemCallEntry;
+ } xSYSTEM_CALL_STACK_INFO;
+
+ #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+ /**
+ * @brief MPU settings as stored in the TCB.
+ */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+ * 16 17 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 71
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ * 16 17 8 8 5 1
+ */
+ #define MAX_CONTEXT_SIZE 55
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | | | PC, xPSR | EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+ * 16 17 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 70
+
+ #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | |
+ * | | | | PC, xPSR | EXC_RETURN | |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ * 16 17 8 8 4 1
+ */
+ #define MAX_CONTEXT_SIZE 54
+
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +----------+-----------------+------------------------------+------------+-----+
+ *
+ * <---------><----------------><------------------------------><-----------><---->
+ * 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 38
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ * 8 8 5 1
+ */
+ #define MAX_CONTEXT_SIZE 22
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+----------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | PC, xPSR | EXC_RETURN | | |
+ * +----------+-----------------+----------------------+------------+-----+
+ *
+ * <---------><----------------><----------------------><-----------><---->
+ * 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 37
+
+ #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+
+ /*
+ * +----------+-----------------+----------------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | |
+ * | | PC, xPSR | EXC_RETURN | |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ * 8 8 4 1
+ */
+ #define MAX_CONTEXT_SIZE 21
+
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+
+ /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+ #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+ #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+
+ /* Size of an Access Control List (ACL) entry in bits. */
+ #define portACL_ENTRY_SIZE_BITS ( 32U )
+
+ typedef struct MPU_SETTINGS
+ {
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+ uint32_t ulContext[ MAX_CONTEXT_SIZE ];
+ uint32_t ulTaskFlags;
+
+ #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+ xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+ #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+ uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
+ #endif
+ #endif
+ } xMPU_SETTINGS;
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#if ( configASSERT_DEFINED == 1 )
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT 100
+#define portSVC_FREE_SECURE_CONTEXT 101
+#define portSVC_START_SCHEDULER 102
+#define portSVC_RAISE_PRIVILEGE 103
+#define portSVC_SYSTEM_CALL_EXIT 104
+#define portSVC_YIELD 105
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#if ( configENABLE_MPU == 1 )
+ #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() vPortYield()
+#else
+ #define portYIELD() vPortYield()
+ #define portYIELD_WITHIN_API() vPortYield()
+#endif
+
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ extern BaseType_t xPortIsTaskPrivileged( void );
+
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #else
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+ #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+ static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint32_t ulReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ulReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+ #endif
+
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+ #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+ #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACROCOMMON_H */
diff --git a/portable/IAR/ARM_CM52/secure/secure_context.c b/portable/IAR/ARM_CM52/secure/secure_context.c
new file mode 100644
index 0000000..3aa335e
--- /dev/null
+++ b/portable/IAR/ARM_CM52/secure/secure_context.c
@@ -0,0 +1,354 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED 0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03
+
+/**
+ * @brief Size of stack seal values in bytes.
+ */
+#define securecontextSTACK_SEAL_SIZE 8
+
+/**
+ * @brief Stack seal value as recommended by ARM.
+ */
+#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5
+
+/**
+ * @brief Maximum number of secure contexts.
+ */
+#ifndef secureconfigMAX_SECURE_CONTEXTS
+ #define secureconfigMAX_SECURE_CONTEXTS 8UL
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Pre-allocated array of secure contexts.
+ */
+SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ];
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Get a free secure context for a task from the secure context pool (xSecureContexts).
+ *
+ * This function ensures that only one secure context is allocated for a task.
+ *
+ * @param[in] pvTaskHandle The task handle for which the secure context is allocated.
+ *
+ * @return Index of a free secure context in the xSecureContexts array.
+ */
+static uint32_t ulGetSecureContext( void * pvTaskHandle );
+
+/**
+ * @brief Return the secure context to the secure context pool (xSecureContexts).
+ *
+ * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array.
+ */
+static void vReturnSecureContext( uint32_t ulSecureContextIndex );
+
+/* These are implemented in assembly. */
+extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext );
+extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext );
+/*-----------------------------------------------------------*/
+
+static uint32_t ulGetSecureContext( void * pvTaskHandle )
+{
+ /* Start with invalid index. */
+ uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
+
+ for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
+ {
+ if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) &&
+ ( xSecureContexts[ i ].pucStackLimit == NULL ) &&
+ ( xSecureContexts[ i ].pucStackStart == NULL ) &&
+ ( xSecureContexts[ i ].pvTaskHandle == NULL ) &&
+ ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) )
+ {
+ ulSecureContextIndex = i;
+ }
+ else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle )
+ {
+ /* A task can only have one secure context. Do not allocate a second
+ * context for the same task. */
+ ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
+ break;
+ }
+ }
+
+ return ulSecureContextIndex;
+}
+/*-----------------------------------------------------------*/
+
+static void vReturnSecureContext( uint32_t ulSecureContextIndex )
+{
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL;
+ xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL;
+ xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL;
+ xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+ uint32_t ulIPSR, i;
+ static uint32_t ulSecureContextsInitialized = 0;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) )
+ {
+ /* Ensure to initialize secure contexts only once. */
+ ulSecureContextsInitialized = 1;
+
+ /* No stack for thread mode until a task's context is loaded. */
+ secureportSET_PSPLIM( securecontextNO_STACK );
+ secureportSET_PSP( securecontextNO_STACK );
+
+ /* Initialize all secure contexts. */
+ for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
+ {
+ xSecureContexts[ i ].pucCurrentStackPointer = NULL;
+ xSecureContexts[ i ].pucStackLimit = NULL;
+ xSecureContexts[ i ].pucStackStart = NULL;
+ xSecureContexts[ i ].pvTaskHandle = NULL;
+ }
+
+ #if ( configENABLE_MPU == 1 )
+ {
+ /* Configure thread mode to use PSP and to be unprivileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+ }
+ #else /* configENABLE_MPU */
+ {
+ /* Configure thread mode to use PSP and to be privileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+ }
+ #endif /* configENABLE_MPU */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+ uint32_t ulIsTaskPrivileged,
+ void * pvTaskHandle )
+#else /* configENABLE_MPU */
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+ void * pvTaskHandle )
+#endif /* configENABLE_MPU */
+{
+ uint8_t * pucStackMemory = NULL;
+ uint8_t * pucStackLimit;
+ uint32_t ulIPSR, ulSecureContextIndex;
+ SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID;
+
+ #if ( configENABLE_MPU == 1 )
+ uint32_t * pulCurrentStackPointer = NULL;
+ #endif /* configENABLE_MPU */
+
+ /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit
+ * Register (PSPLIM) value. */
+ secureportREAD_IPSR( ulIPSR );
+ secureportREAD_PSPLIM( pucStackLimit );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode.
+ * Also do nothing, if a secure context us already loaded. PSPLIM is set to
+ * securecontextNO_STACK when no secure context is loaded. */
+ if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
+ {
+ /* Obtain a free secure context. */
+ ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
+
+ /* Were we able to get a free context? */
+ if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS )
+ {
+ /* Allocate the stack space. */
+ pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE );
+
+ if( pucStackMemory != NULL )
+ {
+ /* Since stack grows down, the starting point will be the last
+ * location. Note that this location is next to the last
+ * allocated byte for stack (excluding the space for seal values)
+ * because the hardware decrements the stack pointer before
+ * writing i.e. if stack pointer is 0x2, a push operation will
+ * decrement the stack pointer to 0x1 and then write at 0x1. */
+ xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
+
+ /* Seal the created secure process stack. */
+ *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+ *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+
+ /* The stack cannot go beyond this location. This value is
+ * programmed in the PSPLIM register on context switch.*/
+ xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory;
+
+ xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
+
+ #if ( configENABLE_MPU == 1 )
+ {
+ /* Store the correct CONTROL value for the task on the stack.
+ * This value is programmed in the CONTROL register on
+ * context switch. */
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ pulCurrentStackPointer--;
+
+ if( ulIsTaskPrivileged )
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+ }
+ else
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+ }
+
+ /* Store the current stack pointer. This value is programmed in
+ * the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ }
+ #else /* configENABLE_MPU */
+ {
+ /* Current SP is set to the starting of the stack. This
+ * value programmed in the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ }
+ #endif /* configENABLE_MPU */
+
+ /* Ensure to never return 0 as a valid context handle. */
+ xSecureContextHandle = ulSecureContextIndex + 1UL;
+ }
+ }
+ }
+
+ return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
+{
+ uint32_t ulIPSR, ulSecureContextIndex;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* Only free if a valid context handle is passed. */
+ if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
+ {
+ ulSecureContextIndex = xSecureContextHandle - 1UL;
+
+ /* Ensure that the secure context being deleted is associated with
+ * the task. */
+ if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle )
+ {
+ /* Free the stack space. */
+ vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit );
+
+ /* Return the secure context back to the free secure contexts pool. */
+ vReturnSecureContext( ulSecureContextIndex );
+ }
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
+{
+ uint8_t * pucStackLimit;
+ uint32_t ulSecureContextIndex;
+
+ if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
+ {
+ ulSecureContextIndex = xSecureContextHandle - 1UL;
+
+ secureportREAD_PSPLIM( pucStackLimit );
+
+ /* Ensure that no secure context is loaded and the task is loading it's
+ * own context. */
+ if( ( pucStackLimit == securecontextNO_STACK ) &&
+ ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
+ {
+ SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
+{
+ uint8_t * pucStackLimit;
+ uint32_t ulSecureContextIndex;
+
+ if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
+ {
+ ulSecureContextIndex = xSecureContextHandle - 1UL;
+
+ secureportREAD_PSPLIM( pucStackLimit );
+
+ /* Ensure that task's context is loaded and the task is saving it's own
+ * context. */
+ if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
+ ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
+ {
+ SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM52/secure/secure_context.h b/portable/IAR/ARM_CM52/secure/secure_context.h
new file mode 100644
index 0000000..e36a8e4
--- /dev/null
+++ b/portable/IAR/ARM_CM52/secure/secure_context.h
@@ -0,0 +1,138 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no secure context is loaded.
+ */
+#define securecontextNO_STACK 0x0
+
+/**
+ * @brief Invalid context ID.
+ */
+#define securecontextINVALID_CONTEXT_ID 0UL
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent a secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first address of the allocated memory.
+ */
+typedef struct SecureContext
+{
+ uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
+ uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */
+ uint8_t * pucStackStart; /**< First location of the stack memory. */
+ void * pvTaskHandle; /**< Task handle of the task this context is associated with. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Opaque handle for a secure context.
+ */
+typedef uint32_t SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if ( configENABLE_MPU == 1 )
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+ uint32_t ulIsTaskPrivileged,
+ void * pvTaskHandle );
+#else /* configENABLE_MPU */
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+ void * pvTaskHandle );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/portable/IAR/ARM_CM52/secure/secure_context_port_asm.s b/portable/IAR/ARM_CM52/secure/secure_context_port_asm.s
new file mode 100644
index 0000000..27a8f393
--- /dev/null
+++ b/portable/IAR/ARM_CM52/secure/secure_context_port_asm.s
@@ -0,0 +1,86 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+ SECTION .text:CODE:NOROOT(2)
+ THUMB
+
+/* Including FreeRTOSConfig.h here will cause build errors if the header file
+contains code not understood by the assembler - for example the 'extern' keyword.
+To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
+the code is included in C files but excluded by the preprocessor in assembly
+files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
+#include "FreeRTOSConfig.h"
+
+ PUBLIC SecureContext_LoadContextAsm
+ PUBLIC SecureContext_SaveContextAsm
+/*-----------------------------------------------------------*/
+
+SecureContext_LoadContextAsm:
+ /* pxSecureContext value is in r0. */
+ mrs r1, ipsr /* r1 = IPSR. */
+ cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
+ ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
+
+#if ( configENABLE_MPU == 1 )
+ ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+ msr control, r3 /* CONTROL = r3. */
+#endif /* configENABLE_MPU */
+
+ msr psplim, r2 /* PSPLIM = r2. */
+ msr psp, r1 /* PSP = r1. */
+
+ load_ctx_therad_mode:
+ bx lr
+/*-----------------------------------------------------------*/
+
+SecureContext_SaveContextAsm:
+ /* pxSecureContext value is in r0. */
+ mrs r1, ipsr /* r1 = IPSR. */
+ cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
+ mrs r1, psp /* r1 = PSP. */
+
+#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */
+ vldmia r1!, {s0} /* Nullify the effect of the previous statement. */
+#endif /* configENABLE_FPU || configENABLE_MVE */
+
+#if ( configENABLE_MPU == 1 )
+ mrs r2, control /* r2 = CONTROL. */
+ stmdb r1!, {r2} /* Store CONTROL value on the stack. */
+#endif /* configENABLE_MPU */
+
+ str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
+ movs r1, #0 /* r1 = securecontextNO_STACK. */
+ msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */
+ msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+
+ save_ctx_therad_mode:
+ bx lr
+/*-----------------------------------------------------------*/
+
+ END
diff --git a/portable/IAR/ARM_CM52/secure/secure_heap.c b/portable/IAR/ARM_CM52/secure/secure_heap.c
new file mode 100644
index 0000000..896b53e
--- /dev/null
+++ b/portable/IAR/ARM_CM52/secure/secure_heap.c
@@ -0,0 +1,485 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Configuration includes. */
+#include "FreeRTOSConfig.h"
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#ifndef secureconfigTOTAL_HEAP_SIZE
+ #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )
+#endif
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+ #define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+ #define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+ #define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block. When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) )
+#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK )
+#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
+
+/* The application writer has already defined the array used for the RTOS
+* heap - probably so it can be placed in a special segment or address. */
+ extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+ static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+ struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */
+ size_t xBlockSize; /**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart;
+static BlockLink_t * pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+ BlockLink_t * pxFirstFreeBlock;
+ uint8_t * pucAlignedHeap;
+ size_t uxAddress;
+ size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+ /* Ensure the heap starts on a correctly aligned boundary. */
+ uxAddress = ( size_t ) ucHeap;
+
+ if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+ {
+ uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+ xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+ }
+
+ pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+ /* xStart is used to hold a pointer to the first item in the list of free
+ * blocks. The void cast is used to prevent compiler warnings. */
+ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+ xStart.xBlockSize = ( size_t ) 0;
+
+ /* pxEnd is used to mark the end of the list of free blocks and is inserted
+ * at the end of the heap space. */
+ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+ uxAddress -= xHeapStructSize;
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+ pxEnd = ( void * ) uxAddress;
+ pxEnd->xBlockSize = 0;
+ pxEnd->pxNextFreeBlock = NULL;
+
+ /* To start with there is a single free block that is sized to take up the
+ * entire heap space, minus the space taken by pxEnd. */
+ pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+ pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+ pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+ /* Only one block exists - and it covers the entire usable heap space. */
+ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+ xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
+{
+ BlockLink_t * pxIterator;
+ uint8_t * puc;
+
+ /* Iterate through the list until a block is found that has a higher address
+ * than the block being inserted. */
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+ {
+ /* Nothing to do here, just iterate to the right position. */
+ }
+
+ /* Do the block being inserted, and the block it is being inserted after
+ * make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxIterator;
+
+ if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+ {
+ pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+ pxBlockToInsert = pxIterator;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Do the block being inserted, and the block it is being inserted before
+ * make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxBlockToInsert;
+
+ if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+ {
+ if( pxIterator->pxNextFreeBlock != pxEnd )
+ {
+ /* Form one big block from the two blocks. */
+ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxEnd;
+ }
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+ }
+
+ /* If the block being inserted plugged a gap, so was merged with the block
+ * before and the block after, then it's pxNextFreeBlock pointer will have
+ * already been set, and should not be set here as that would make it point
+ * to itself. */
+ if( pxIterator != pxBlockToInsert )
+ {
+ pxIterator->pxNextFreeBlock = pxBlockToInsert;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void * pvPortMalloc( size_t xWantedSize )
+{
+ BlockLink_t * pxBlock;
+ BlockLink_t * pxPreviousBlock;
+ BlockLink_t * pxNewBlockLink;
+ void * pvReturn = NULL;
+ size_t xAdditionalRequiredSize;
+ size_t xAllocatedBlockSize = 0;
+
+ /* If this is the first call to malloc then the heap will require
+ * initialisation to setup the list of free blocks. */
+ if( pxEnd == NULL )
+ {
+ prvHeapInit();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( xWantedSize > 0 )
+ {
+ /* The wanted size must be increased so it can contain a BlockLink_t
+ * structure in addition to the requested amount of bytes. */
+ if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
+ {
+ xWantedSize += xHeapStructSize;
+
+ /* Ensure that blocks are always aligned to the required number
+ * of bytes. */
+ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+ {
+ /* Byte alignment required. */
+ xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK );
+
+ if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+ {
+ xWantedSize += xAdditionalRequiredSize;
+ }
+ else
+ {
+ xWantedSize = 0;
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ xWantedSize = 0;
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Check the requested block size is not so large that the top bit is set.
+ * The top bit of the block size member of the BlockLink_t structure is used
+ * to determine who owns the block - the application or the kernel, so it
+ * must be free. */
+ if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+ {
+ if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+ {
+ /* Traverse the list from the start (lowest address) block until
+ * one of adequate size is found. */
+ pxPreviousBlock = &xStart;
+ pxBlock = xStart.pxNextFreeBlock;
+
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+ {
+ pxPreviousBlock = pxBlock;
+ pxBlock = pxBlock->pxNextFreeBlock;
+ }
+
+ /* If the end marker was reached then a block of adequate size was
+ * not found. */
+ if( pxBlock != pxEnd )
+ {
+ /* Return the memory space pointed to - jumping over the
+ * BlockLink_t structure at its start. */
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+ /* This block is being returned for use so must be taken out
+ * of the list of free blocks. */
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+ /* If the block is larger than required it can be split into
+ * two. */
+ if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+ {
+ /* This block is to be split into two. Create a new
+ * block following the number of bytes requested. The void
+ * cast is used to prevent byte alignment warnings from the
+ * compiler. */
+ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+ secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+ /* Calculate the sizes of two blocks split from the single
+ * block. */
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+ pxBlock->xBlockSize = xWantedSize;
+
+ /* Insert the new block into the list of free blocks. */
+ pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+ pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+ if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+ {
+ xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ xAllocatedBlockSize = pxBlock->xBlockSize;
+
+ /* The block is being returned - it is allocated and owned by
+ * the application and has no "next" block. */
+ secureheapALLOCATE_BLOCK( pxBlock );
+ pxBlock->pxNextFreeBlock = NULL;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+ /* Prevent compiler warnings when trace macros are not used. */
+ ( void ) xAllocatedBlockSize;
+
+ #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
+ {
+ extern void vApplicationMallocFailedHook( void );
+ vApplicationMallocFailedHook();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
+
+ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void * pv )
+{
+ uint8_t * puc = ( uint8_t * ) pv;
+ BlockLink_t * pxLink;
+
+ if( pv != NULL )
+ {
+ /* The memory being freed will have an BlockLink_t structure immediately
+ * before it. */
+ puc -= xHeapStructSize;
+
+ /* This casting is to keep the compiler from issuing warnings. */
+ pxLink = ( void * ) puc;
+
+ /* Check the block is actually allocated. */
+ secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
+ secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+ if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
+ {
+ if( pxLink->pxNextFreeBlock == NULL )
+ {
+ /* The block is being returned to the heap - it is no longer
+ * allocated. */
+ secureheapFREE_BLOCK( pxLink );
+
+ secureportDISABLE_NON_SECURE_INTERRUPTS();
+ {
+ /* Add this block to the list of free blocks. */
+ xFreeBytesRemaining += pxLink->xBlockSize;
+ traceFREE( pv, pxLink->xBlockSize );
+ prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+ }
+ secureportENABLE_NON_SECURE_INTERRUPTS();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+ return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+ return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM52/secure/secure_heap.h b/portable/IAR/ARM_CM52/secure/secure_heap.h
new file mode 100644
index 0000000..0e84a9d
--- /dev/null
+++ b/portable/IAR/ARM_CM52/secure/secure_heap.h
@@ -0,0 +1,66 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void * pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void * pv );
+
+/**
+ * @brief Get the free heap size.
+ *
+ * @return Free heap size.
+ */
+size_t xPortGetFreeHeapSize( void );
+
+/**
+ * @brief Get the minimum ever free heap size.
+ *
+ * @return Minimum ever free heap size.
+ */
+size_t xPortGetMinimumEverFreeHeapSize( void );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/portable/IAR/ARM_CM52/secure/secure_init.c b/portable/IAR/ARM_CM52/secure/secure_init.c
new file mode 100644
index 0000000..c50d376
--- /dev/null
+++ b/portable/IAR/ARM_CM52/secure/secure_init.c
@@ -0,0 +1,106 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS ( 29UL )
+#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS ( 26UL )
+#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS ( 10UL )
+#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS ( 11UL )
+#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+ ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+ ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
+ }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+ * permitted. CP11 should be programmed to the same value as CP10. */
+ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+ /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
+ * that we can enable/disable lazy stacking in port.c file. */
+ *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
+
+ /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+ * registers (S16-S31) are also pushed to stack on exception entry and
+ * restored on exception return. */
+ *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+ }
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM52/secure/secure_init.h b/portable/IAR/ARM_CM52/secure/secure_init.h
new file mode 100644
index 0000000..ebe0490
--- /dev/null
+++ b/portable/IAR/ARM_CM52/secure/secure_init.h
@@ -0,0 +1,54 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/portable/IAR/ARM_CM52/secure/secure_port_macros.h b/portable/IAR/ARM_CM52/secure/secure_port_macros.h
new file mode 100644
index 0000000..a70da2c
--- /dev/null
+++ b/portable/IAR/ARM_CM52/secure/secure_port_macros.h
@@ -0,0 +1,140 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT 8
+#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root
+#else
+ #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+ __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+ __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+ __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+ __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Read the PSPLIM value in the given variable.
+ */
+#define secureportREAD_PSPLIM( pucOutStackLimit ) \
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+ __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+ __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x ) \
+ if( ( x ) == 0 ) \
+ { \
+ secureportDISABLE_SECURE_INTERRUPTS(); \
+ secureportDISABLE_NON_SECURE_INTERRUPTS(); \
+ for( ; ; ) {; } \
+ }
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/portable/IAR/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.S
new file mode 100644
index 0000000..d2cb78e
--- /dev/null
+++ b/portable/IAR/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -0,0 +1,1242 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+ SECTION freertos_system_calls:CODE:NOROOT(2)
+ THUMB
+/*-----------------------------------------------------------*/
+
+#include "FreeRTOSConfig.h"
+#include "mpu_syscall_numbers.h"
+
+#ifndef configUSE_MPU_WRAPPERS_V1
+ #define configUSE_MPU_WRAPPERS_V1 0
+#endif
+
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ PUBLIC MPU_xTaskDelayUntil
+MPU_xTaskDelayUntil:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskDelayUntil_Unpriv
+ MPU_xTaskDelayUntil_Priv:
+ b MPU_xTaskDelayUntilImpl
+ MPU_xTaskDelayUntil_Unpriv:
+ svc #SYSTEM_CALL_xTaskDelayUntil
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTaskAbortDelay
+MPU_xTaskAbortDelay:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskAbortDelay_Unpriv
+ MPU_xTaskAbortDelay_Priv:
+ b MPU_xTaskAbortDelayImpl
+ MPU_xTaskAbortDelay_Unpriv:
+ svc #SYSTEM_CALL_xTaskAbortDelay
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vTaskDelay
+MPU_vTaskDelay:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vTaskDelay_Unpriv
+ MPU_vTaskDelay_Priv:
+ b MPU_vTaskDelayImpl
+ MPU_vTaskDelay_Unpriv:
+ svc #SYSTEM_CALL_vTaskDelay
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_uxTaskPriorityGet
+MPU_uxTaskPriorityGet:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_uxTaskPriorityGet_Unpriv
+ MPU_uxTaskPriorityGet_Priv:
+ b MPU_uxTaskPriorityGetImpl
+ MPU_uxTaskPriorityGet_Unpriv:
+ svc #SYSTEM_CALL_uxTaskPriorityGet
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_eTaskGetState
+MPU_eTaskGetState:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_eTaskGetState_Unpriv
+ MPU_eTaskGetState_Priv:
+ b MPU_eTaskGetStateImpl
+ MPU_eTaskGetState_Unpriv:
+ svc #SYSTEM_CALL_eTaskGetState
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vTaskGetInfo
+MPU_vTaskGetInfo:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vTaskGetInfo_Unpriv
+ MPU_vTaskGetInfo_Priv:
+ b MPU_vTaskGetInfoImpl
+ MPU_vTaskGetInfo_Unpriv:
+ svc #SYSTEM_CALL_vTaskGetInfo
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTaskGetIdleTaskHandle
+MPU_xTaskGetIdleTaskHandle:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskGetIdleTaskHandle_Unpriv
+ MPU_xTaskGetIdleTaskHandle_Priv:
+ b MPU_xTaskGetIdleTaskHandleImpl
+ MPU_xTaskGetIdleTaskHandle_Unpriv:
+ svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vTaskSuspend
+MPU_vTaskSuspend:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vTaskSuspend_Unpriv
+ MPU_vTaskSuspend_Priv:
+ b MPU_vTaskSuspendImpl
+ MPU_vTaskSuspend_Unpriv:
+ svc #SYSTEM_CALL_vTaskSuspend
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vTaskResume
+MPU_vTaskResume:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vTaskResume_Unpriv
+ MPU_vTaskResume_Priv:
+ b MPU_vTaskResumeImpl
+ MPU_vTaskResume_Unpriv:
+ svc #SYSTEM_CALL_vTaskResume
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTaskGetTickCount
+MPU_xTaskGetTickCount:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskGetTickCount_Unpriv
+ MPU_xTaskGetTickCount_Priv:
+ b MPU_xTaskGetTickCountImpl
+ MPU_xTaskGetTickCount_Unpriv:
+ svc #SYSTEM_CALL_xTaskGetTickCount
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_uxTaskGetNumberOfTasks
+MPU_uxTaskGetNumberOfTasks:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_uxTaskGetNumberOfTasks_Unpriv
+ MPU_uxTaskGetNumberOfTasks_Priv:
+ b MPU_uxTaskGetNumberOfTasksImpl
+ MPU_uxTaskGetNumberOfTasks_Unpriv:
+ svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_ulTaskGetRunTimeCounter
+MPU_ulTaskGetRunTimeCounter:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_ulTaskGetRunTimeCounter_Unpriv
+ MPU_ulTaskGetRunTimeCounter_Priv:
+ b MPU_ulTaskGetRunTimeCounterImpl
+ MPU_ulTaskGetRunTimeCounter_Unpriv:
+ svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_ulTaskGetRunTimePercent
+MPU_ulTaskGetRunTimePercent:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_ulTaskGetRunTimePercent_Unpriv
+ MPU_ulTaskGetRunTimePercent_Priv:
+ b MPU_ulTaskGetRunTimePercentImpl
+ MPU_ulTaskGetRunTimePercent_Unpriv:
+ svc #SYSTEM_CALL_ulTaskGetRunTimePercent
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_ulTaskGetIdleRunTimePercent
+MPU_ulTaskGetIdleRunTimePercent:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
+ MPU_ulTaskGetIdleRunTimePercent_Priv:
+ b MPU_ulTaskGetIdleRunTimePercentImpl
+ MPU_ulTaskGetIdleRunTimePercent_Unpriv:
+ svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_ulTaskGetIdleRunTimeCounter
+MPU_ulTaskGetIdleRunTimeCounter:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
+ MPU_ulTaskGetIdleRunTimeCounter_Priv:
+ b MPU_ulTaskGetIdleRunTimeCounterImpl
+ MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
+ svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vTaskSetApplicationTaskTag
+MPU_vTaskSetApplicationTaskTag:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vTaskSetApplicationTaskTag_Unpriv
+ MPU_vTaskSetApplicationTaskTag_Priv:
+ b MPU_vTaskSetApplicationTaskTagImpl
+ MPU_vTaskSetApplicationTaskTag_Unpriv:
+ svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTaskGetApplicationTaskTag
+MPU_xTaskGetApplicationTaskTag:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskGetApplicationTaskTag_Unpriv
+ MPU_xTaskGetApplicationTaskTag_Priv:
+ b MPU_xTaskGetApplicationTaskTagImpl
+ MPU_xTaskGetApplicationTaskTag_Unpriv:
+ svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vTaskSetThreadLocalStoragePointer
+MPU_vTaskSetThreadLocalStoragePointer:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
+ MPU_vTaskSetThreadLocalStoragePointer_Priv:
+ b MPU_vTaskSetThreadLocalStoragePointerImpl
+ MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
+ svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
+MPU_pvTaskGetThreadLocalStoragePointer:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
+ MPU_pvTaskGetThreadLocalStoragePointer_Priv:
+ b MPU_pvTaskGetThreadLocalStoragePointerImpl
+ MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
+ svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_uxTaskGetSystemState
+MPU_uxTaskGetSystemState:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_uxTaskGetSystemState_Unpriv
+ MPU_uxTaskGetSystemState_Priv:
+ b MPU_uxTaskGetSystemStateImpl
+ MPU_uxTaskGetSystemState_Unpriv:
+ svc #SYSTEM_CALL_uxTaskGetSystemState
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_uxTaskGetStackHighWaterMark
+MPU_uxTaskGetStackHighWaterMark:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_uxTaskGetStackHighWaterMark_Unpriv
+ MPU_uxTaskGetStackHighWaterMark_Priv:
+ b MPU_uxTaskGetStackHighWaterMarkImpl
+ MPU_uxTaskGetStackHighWaterMark_Unpriv:
+ svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_uxTaskGetStackHighWaterMark2
+MPU_uxTaskGetStackHighWaterMark2:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
+ MPU_uxTaskGetStackHighWaterMark2_Priv:
+ b MPU_uxTaskGetStackHighWaterMark2Impl
+ MPU_uxTaskGetStackHighWaterMark2_Unpriv:
+ svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTaskGetCurrentTaskHandle
+MPU_xTaskGetCurrentTaskHandle:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskGetCurrentTaskHandle_Unpriv
+ MPU_xTaskGetCurrentTaskHandle_Priv:
+ b MPU_xTaskGetCurrentTaskHandleImpl
+ MPU_xTaskGetCurrentTaskHandle_Unpriv:
+ svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTaskGetSchedulerState
+MPU_xTaskGetSchedulerState:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskGetSchedulerState_Unpriv
+ MPU_xTaskGetSchedulerState_Priv:
+ b MPU_xTaskGetSchedulerStateImpl
+ MPU_xTaskGetSchedulerState_Unpriv:
+ svc #SYSTEM_CALL_xTaskGetSchedulerState
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vTaskSetTimeOutState
+MPU_vTaskSetTimeOutState:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vTaskSetTimeOutState_Unpriv
+ MPU_vTaskSetTimeOutState_Priv:
+ b MPU_vTaskSetTimeOutStateImpl
+ MPU_vTaskSetTimeOutState_Unpriv:
+ svc #SYSTEM_CALL_vTaskSetTimeOutState
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTaskCheckForTimeOut
+MPU_xTaskCheckForTimeOut:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskCheckForTimeOut_Unpriv
+ MPU_xTaskCheckForTimeOut_Priv:
+ b MPU_xTaskCheckForTimeOutImpl
+ MPU_xTaskCheckForTimeOut_Unpriv:
+ svc #SYSTEM_CALL_xTaskCheckForTimeOut
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTaskGenericNotifyEntry
+MPU_xTaskGenericNotifyEntry:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskGenericNotify_Unpriv
+ MPU_xTaskGenericNotify_Priv:
+ b MPU_xTaskGenericNotifyImpl
+ MPU_xTaskGenericNotify_Unpriv:
+ svc #SYSTEM_CALL_xTaskGenericNotify
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTaskGenericNotifyWaitEntry
+MPU_xTaskGenericNotifyWaitEntry:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskGenericNotifyWait_Unpriv
+ MPU_xTaskGenericNotifyWait_Priv:
+ b MPU_xTaskGenericNotifyWaitImpl
+ MPU_xTaskGenericNotifyWait_Unpriv:
+ svc #SYSTEM_CALL_xTaskGenericNotifyWait
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_ulTaskGenericNotifyTake
+MPU_ulTaskGenericNotifyTake:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_ulTaskGenericNotifyTake_Unpriv
+ MPU_ulTaskGenericNotifyTake_Priv:
+ b MPU_ulTaskGenericNotifyTakeImpl
+ MPU_ulTaskGenericNotifyTake_Unpriv:
+ svc #SYSTEM_CALL_ulTaskGenericNotifyTake
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTaskGenericNotifyStateClear
+MPU_xTaskGenericNotifyStateClear:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTaskGenericNotifyStateClear_Unpriv
+ MPU_xTaskGenericNotifyStateClear_Priv:
+ b MPU_xTaskGenericNotifyStateClearImpl
+ MPU_xTaskGenericNotifyStateClear_Unpriv:
+ svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_ulTaskGenericNotifyValueClear
+MPU_ulTaskGenericNotifyValueClear:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_ulTaskGenericNotifyValueClear_Unpriv
+ MPU_ulTaskGenericNotifyValueClear_Priv:
+ b MPU_ulTaskGenericNotifyValueClearImpl
+ MPU_ulTaskGenericNotifyValueClear_Unpriv:
+ svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xQueueGenericSend
+MPU_xQueueGenericSend:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xQueueGenericSend_Unpriv
+ MPU_xQueueGenericSend_Priv:
+ b MPU_xQueueGenericSendImpl
+ MPU_xQueueGenericSend_Unpriv:
+ svc #SYSTEM_CALL_xQueueGenericSend
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_uxQueueMessagesWaiting
+MPU_uxQueueMessagesWaiting:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_uxQueueMessagesWaiting_Unpriv
+ MPU_uxQueueMessagesWaiting_Priv:
+ b MPU_uxQueueMessagesWaitingImpl
+ MPU_uxQueueMessagesWaiting_Unpriv:
+ svc #SYSTEM_CALL_uxQueueMessagesWaiting
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_uxQueueSpacesAvailable
+MPU_uxQueueSpacesAvailable:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_uxQueueSpacesAvailable_Unpriv
+ MPU_uxQueueSpacesAvailable_Priv:
+ b MPU_uxQueueSpacesAvailableImpl
+ MPU_uxQueueSpacesAvailable_Unpriv:
+ svc #SYSTEM_CALL_uxQueueSpacesAvailable
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xQueueReceive
+MPU_xQueueReceive:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xQueueReceive_Unpriv
+ MPU_xQueueReceive_Priv:
+ b MPU_xQueueReceiveImpl
+ MPU_xQueueReceive_Unpriv:
+ svc #SYSTEM_CALL_xQueueReceive
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xQueuePeek
+MPU_xQueuePeek:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xQueuePeek_Unpriv
+ MPU_xQueuePeek_Priv:
+ b MPU_xQueuePeekImpl
+ MPU_xQueuePeek_Unpriv:
+ svc #SYSTEM_CALL_xQueuePeek
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xQueueSemaphoreTake
+MPU_xQueueSemaphoreTake:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xQueueSemaphoreTake_Unpriv
+ MPU_xQueueSemaphoreTake_Priv:
+ b MPU_xQueueSemaphoreTakeImpl
+ MPU_xQueueSemaphoreTake_Unpriv:
+ svc #SYSTEM_CALL_xQueueSemaphoreTake
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xQueueGetMutexHolder
+MPU_xQueueGetMutexHolder:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xQueueGetMutexHolder_Unpriv
+ MPU_xQueueGetMutexHolder_Priv:
+ b MPU_xQueueGetMutexHolderImpl
+ MPU_xQueueGetMutexHolder_Unpriv:
+ svc #SYSTEM_CALL_xQueueGetMutexHolder
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xQueueTakeMutexRecursive
+MPU_xQueueTakeMutexRecursive:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xQueueTakeMutexRecursive_Unpriv
+ MPU_xQueueTakeMutexRecursive_Priv:
+ b MPU_xQueueTakeMutexRecursiveImpl
+ MPU_xQueueTakeMutexRecursive_Unpriv:
+ svc #SYSTEM_CALL_xQueueTakeMutexRecursive
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xQueueGiveMutexRecursive
+MPU_xQueueGiveMutexRecursive:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xQueueGiveMutexRecursive_Unpriv
+ MPU_xQueueGiveMutexRecursive_Priv:
+ b MPU_xQueueGiveMutexRecursiveImpl
+ MPU_xQueueGiveMutexRecursive_Unpriv:
+ svc #SYSTEM_CALL_xQueueGiveMutexRecursive
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xQueueSelectFromSet
+MPU_xQueueSelectFromSet:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xQueueSelectFromSet_Unpriv
+ MPU_xQueueSelectFromSet_Priv:
+ b MPU_xQueueSelectFromSetImpl
+ MPU_xQueueSelectFromSet_Unpriv:
+ svc #SYSTEM_CALL_xQueueSelectFromSet
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xQueueAddToSet
+MPU_xQueueAddToSet:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xQueueAddToSet_Unpriv
+ MPU_xQueueAddToSet_Priv:
+ b MPU_xQueueAddToSetImpl
+ MPU_xQueueAddToSet_Unpriv:
+ svc #SYSTEM_CALL_xQueueAddToSet
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vQueueAddToRegistry
+MPU_vQueueAddToRegistry:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vQueueAddToRegistry_Unpriv
+ MPU_vQueueAddToRegistry_Priv:
+ b MPU_vQueueAddToRegistryImpl
+ MPU_vQueueAddToRegistry_Unpriv:
+ svc #SYSTEM_CALL_vQueueAddToRegistry
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vQueueUnregisterQueue
+MPU_vQueueUnregisterQueue:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vQueueUnregisterQueue_Unpriv
+ MPU_vQueueUnregisterQueue_Priv:
+ b MPU_vQueueUnregisterQueueImpl
+ MPU_vQueueUnregisterQueue_Unpriv:
+ svc #SYSTEM_CALL_vQueueUnregisterQueue
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_pcQueueGetName
+MPU_pcQueueGetName:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_pcQueueGetName_Unpriv
+ MPU_pcQueueGetName_Priv:
+ b MPU_pcQueueGetNameImpl
+ MPU_pcQueueGetName_Unpriv:
+ svc #SYSTEM_CALL_pcQueueGetName
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_pvTimerGetTimerID
+MPU_pvTimerGetTimerID:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_pvTimerGetTimerID_Unpriv
+ MPU_pvTimerGetTimerID_Priv:
+ b MPU_pvTimerGetTimerIDImpl
+ MPU_pvTimerGetTimerID_Unpriv:
+ svc #SYSTEM_CALL_pvTimerGetTimerID
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vTimerSetTimerID
+MPU_vTimerSetTimerID:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vTimerSetTimerID_Unpriv
+ MPU_vTimerSetTimerID_Priv:
+ b MPU_vTimerSetTimerIDImpl
+ MPU_vTimerSetTimerID_Unpriv:
+ svc #SYSTEM_CALL_vTimerSetTimerID
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTimerIsTimerActive
+MPU_xTimerIsTimerActive:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTimerIsTimerActive_Unpriv
+ MPU_xTimerIsTimerActive_Priv:
+ b MPU_xTimerIsTimerActiveImpl
+ MPU_xTimerIsTimerActive_Unpriv:
+ svc #SYSTEM_CALL_xTimerIsTimerActive
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
+MPU_xTimerGetTimerDaemonTaskHandle:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
+ MPU_xTimerGetTimerDaemonTaskHandle_Priv:
+ b MPU_xTimerGetTimerDaemonTaskHandleImpl
+ MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
+ svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTimerGenericCommandFromTask_Unpriv
+ MPU_xTimerGenericCommandFromTask_Priv:
+ b MPU_xTimerGenericCommandFromTaskImpl
+ MPU_xTimerGenericCommandFromTask_Unpriv:
+ svc #SYSTEM_CALL_xTimerGenericCommandFromTask
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_pcTimerGetName
+MPU_pcTimerGetName:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_pcTimerGetName_Unpriv
+ MPU_pcTimerGetName_Priv:
+ b MPU_pcTimerGetNameImpl
+ MPU_pcTimerGetName_Unpriv:
+ svc #SYSTEM_CALL_pcTimerGetName
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vTimerSetReloadMode
+MPU_vTimerSetReloadMode:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vTimerSetReloadMode_Unpriv
+ MPU_vTimerSetReloadMode_Priv:
+ b MPU_vTimerSetReloadModeImpl
+ MPU_vTimerSetReloadMode_Unpriv:
+ svc #SYSTEM_CALL_vTimerSetReloadMode
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTimerGetReloadMode
+MPU_xTimerGetReloadMode:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTimerGetReloadMode_Unpriv
+ MPU_xTimerGetReloadMode_Priv:
+ b MPU_xTimerGetReloadModeImpl
+ MPU_xTimerGetReloadMode_Unpriv:
+ svc #SYSTEM_CALL_xTimerGetReloadMode
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_uxTimerGetReloadMode
+MPU_uxTimerGetReloadMode:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_uxTimerGetReloadMode_Unpriv
+ MPU_uxTimerGetReloadMode_Priv:
+ b MPU_uxTimerGetReloadModeImpl
+ MPU_uxTimerGetReloadMode_Unpriv:
+ svc #SYSTEM_CALL_uxTimerGetReloadMode
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTimerGetPeriod
+MPU_xTimerGetPeriod:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTimerGetPeriod_Unpriv
+ MPU_xTimerGetPeriod_Priv:
+ b MPU_xTimerGetPeriodImpl
+ MPU_xTimerGetPeriod_Unpriv:
+ svc #SYSTEM_CALL_xTimerGetPeriod
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xTimerGetExpiryTime
+MPU_xTimerGetExpiryTime:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xTimerGetExpiryTime_Unpriv
+ MPU_xTimerGetExpiryTime_Priv:
+ b MPU_xTimerGetExpiryTimeImpl
+ MPU_xTimerGetExpiryTime_Unpriv:
+ svc #SYSTEM_CALL_xTimerGetExpiryTime
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xEventGroupWaitBitsEntry
+MPU_xEventGroupWaitBitsEntry:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xEventGroupWaitBits_Unpriv
+ MPU_xEventGroupWaitBits_Priv:
+ b MPU_xEventGroupWaitBitsImpl
+ MPU_xEventGroupWaitBits_Unpriv:
+ svc #SYSTEM_CALL_xEventGroupWaitBits
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xEventGroupClearBits
+MPU_xEventGroupClearBits:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xEventGroupClearBits_Unpriv
+ MPU_xEventGroupClearBits_Priv:
+ b MPU_xEventGroupClearBitsImpl
+ MPU_xEventGroupClearBits_Unpriv:
+ svc #SYSTEM_CALL_xEventGroupClearBits
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xEventGroupSetBits
+MPU_xEventGroupSetBits:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xEventGroupSetBits_Unpriv
+ MPU_xEventGroupSetBits_Priv:
+ b MPU_xEventGroupSetBitsImpl
+ MPU_xEventGroupSetBits_Unpriv:
+ svc #SYSTEM_CALL_xEventGroupSetBits
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xEventGroupSync
+MPU_xEventGroupSync:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xEventGroupSync_Unpriv
+ MPU_xEventGroupSync_Priv:
+ b MPU_xEventGroupSyncImpl
+ MPU_xEventGroupSync_Unpriv:
+ svc #SYSTEM_CALL_xEventGroupSync
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_uxEventGroupGetNumber
+MPU_uxEventGroupGetNumber:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_uxEventGroupGetNumber_Unpriv
+ MPU_uxEventGroupGetNumber_Priv:
+ b MPU_uxEventGroupGetNumberImpl
+ MPU_uxEventGroupGetNumber_Unpriv:
+ svc #SYSTEM_CALL_uxEventGroupGetNumber
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_vEventGroupSetNumber
+MPU_vEventGroupSetNumber:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_vEventGroupSetNumber_Unpriv
+ MPU_vEventGroupSetNumber_Priv:
+ b MPU_vEventGroupSetNumberImpl
+ MPU_vEventGroupSetNumber_Unpriv:
+ svc #SYSTEM_CALL_vEventGroupSetNumber
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xStreamBufferSend
+MPU_xStreamBufferSend:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xStreamBufferSend_Unpriv
+ MPU_xStreamBufferSend_Priv:
+ b MPU_xStreamBufferSendImpl
+ MPU_xStreamBufferSend_Unpriv:
+ svc #SYSTEM_CALL_xStreamBufferSend
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xStreamBufferReceive
+MPU_xStreamBufferReceive:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xStreamBufferReceive_Unpriv
+ MPU_xStreamBufferReceive_Priv:
+ b MPU_xStreamBufferReceiveImpl
+ MPU_xStreamBufferReceive_Unpriv:
+ svc #SYSTEM_CALL_xStreamBufferReceive
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xStreamBufferIsFull
+MPU_xStreamBufferIsFull:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xStreamBufferIsFull_Unpriv
+ MPU_xStreamBufferIsFull_Priv:
+ b MPU_xStreamBufferIsFullImpl
+ MPU_xStreamBufferIsFull_Unpriv:
+ svc #SYSTEM_CALL_xStreamBufferIsFull
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xStreamBufferIsEmpty
+MPU_xStreamBufferIsEmpty:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xStreamBufferIsEmpty_Unpriv
+ MPU_xStreamBufferIsEmpty_Priv:
+ b MPU_xStreamBufferIsEmptyImpl
+ MPU_xStreamBufferIsEmpty_Unpriv:
+ svc #SYSTEM_CALL_xStreamBufferIsEmpty
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xStreamBufferSpacesAvailable
+MPU_xStreamBufferSpacesAvailable:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xStreamBufferSpacesAvailable_Unpriv
+ MPU_xStreamBufferSpacesAvailable_Priv:
+ b MPU_xStreamBufferSpacesAvailableImpl
+ MPU_xStreamBufferSpacesAvailable_Unpriv:
+ svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xStreamBufferBytesAvailable
+MPU_xStreamBufferBytesAvailable:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xStreamBufferBytesAvailable_Unpriv
+ MPU_xStreamBufferBytesAvailable_Priv:
+ b MPU_xStreamBufferBytesAvailableImpl
+ MPU_xStreamBufferBytesAvailable_Unpriv:
+ svc #SYSTEM_CALL_xStreamBufferBytesAvailable
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xStreamBufferSetTriggerLevel
+MPU_xStreamBufferSetTriggerLevel:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xStreamBufferSetTriggerLevel_Unpriv
+ MPU_xStreamBufferSetTriggerLevel_Priv:
+ b MPU_xStreamBufferSetTriggerLevelImpl
+ MPU_xStreamBufferSetTriggerLevel_Unpriv:
+ svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
+/*-----------------------------------------------------------*/
+
+ PUBLIC MPU_xStreamBufferNextMessageLengthBytes
+MPU_xStreamBufferNextMessageLengthBytes:
+ push {r0}
+ mrs r0, control
+ tst r0, #1
+ pop {r0}
+ bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
+ MPU_xStreamBufferNextMessageLengthBytes_Priv:
+ b MPU_xStreamBufferNextMessageLengthBytesImpl
+ MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
+ svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
+/*-----------------------------------------------------------*/
+
+/* Default weak implementations in case one is not available from
+ * mpu_wrappers because of config options. */
+
+ PUBWEAK MPU_xTaskDelayUntilImpl
+MPU_xTaskDelayUntilImpl:
+ b MPU_xTaskDelayUntilImpl
+
+ PUBWEAK MPU_xTaskAbortDelayImpl
+MPU_xTaskAbortDelayImpl:
+ b MPU_xTaskAbortDelayImpl
+
+ PUBWEAK MPU_vTaskDelayImpl
+MPU_vTaskDelayImpl:
+ b MPU_vTaskDelayImpl
+
+ PUBWEAK MPU_uxTaskPriorityGetImpl
+MPU_uxTaskPriorityGetImpl:
+ b MPU_uxTaskPriorityGetImpl
+
+ PUBWEAK MPU_eTaskGetStateImpl
+MPU_eTaskGetStateImpl:
+ b MPU_eTaskGetStateImpl
+
+ PUBWEAK MPU_vTaskGetInfoImpl
+MPU_vTaskGetInfoImpl:
+ b MPU_vTaskGetInfoImpl
+
+ PUBWEAK MPU_xTaskGetIdleTaskHandleImpl
+MPU_xTaskGetIdleTaskHandleImpl:
+ b MPU_xTaskGetIdleTaskHandleImpl
+
+ PUBWEAK MPU_vTaskSuspendImpl
+MPU_vTaskSuspendImpl:
+ b MPU_vTaskSuspendImpl
+
+ PUBWEAK MPU_vTaskResumeImpl
+MPU_vTaskResumeImpl:
+ b MPU_vTaskResumeImpl
+
+ PUBWEAK MPU_xTaskGetTickCountImpl
+MPU_xTaskGetTickCountImpl:
+ b MPU_xTaskGetTickCountImpl
+
+ PUBWEAK MPU_uxTaskGetNumberOfTasksImpl
+MPU_uxTaskGetNumberOfTasksImpl:
+ b MPU_uxTaskGetNumberOfTasksImpl
+
+ PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
+MPU_ulTaskGetRunTimeCounterImpl:
+ b MPU_ulTaskGetRunTimeCounterImpl
+
+ PUBWEAK MPU_ulTaskGetRunTimePercentImpl
+MPU_ulTaskGetRunTimePercentImpl:
+ b MPU_ulTaskGetRunTimePercentImpl
+
+ PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl
+MPU_ulTaskGetIdleRunTimePercentImpl:
+ b MPU_ulTaskGetIdleRunTimePercentImpl
+
+ PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl
+MPU_ulTaskGetIdleRunTimeCounterImpl:
+ b MPU_ulTaskGetIdleRunTimeCounterImpl
+
+ PUBWEAK MPU_vTaskSetApplicationTaskTagImpl
+MPU_vTaskSetApplicationTaskTagImpl:
+ b MPU_vTaskSetApplicationTaskTagImpl
+
+ PUBWEAK MPU_xTaskGetApplicationTaskTagImpl
+MPU_xTaskGetApplicationTaskTagImpl:
+ b MPU_xTaskGetApplicationTaskTagImpl
+
+ PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl
+MPU_vTaskSetThreadLocalStoragePointerImpl:
+ b MPU_vTaskSetThreadLocalStoragePointerImpl
+
+ PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl
+MPU_pvTaskGetThreadLocalStoragePointerImpl:
+ b MPU_pvTaskGetThreadLocalStoragePointerImpl
+
+ PUBWEAK MPU_uxTaskGetSystemStateImpl
+MPU_uxTaskGetSystemStateImpl:
+ b MPU_uxTaskGetSystemStateImpl
+
+ PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl
+MPU_uxTaskGetStackHighWaterMarkImpl:
+ b MPU_uxTaskGetStackHighWaterMarkImpl
+
+ PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl
+MPU_uxTaskGetStackHighWaterMark2Impl:
+ b MPU_uxTaskGetStackHighWaterMark2Impl
+
+ PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl
+MPU_xTaskGetCurrentTaskHandleImpl:
+ b MPU_xTaskGetCurrentTaskHandleImpl
+
+ PUBWEAK MPU_xTaskGetSchedulerStateImpl
+MPU_xTaskGetSchedulerStateImpl:
+ b MPU_xTaskGetSchedulerStateImpl
+
+ PUBWEAK MPU_vTaskSetTimeOutStateImpl
+MPU_vTaskSetTimeOutStateImpl:
+ b MPU_vTaskSetTimeOutStateImpl
+
+ PUBWEAK MPU_xTaskCheckForTimeOutImpl
+MPU_xTaskCheckForTimeOutImpl:
+ b MPU_xTaskCheckForTimeOutImpl
+
+ PUBWEAK MPU_xTaskGenericNotifyImpl
+MPU_xTaskGenericNotifyImpl:
+ b MPU_xTaskGenericNotifyImpl
+
+ PUBWEAK MPU_xTaskGenericNotifyWaitImpl
+MPU_xTaskGenericNotifyWaitImpl:
+ b MPU_xTaskGenericNotifyWaitImpl
+
+ PUBWEAK MPU_ulTaskGenericNotifyTakeImpl
+MPU_ulTaskGenericNotifyTakeImpl:
+ b MPU_ulTaskGenericNotifyTakeImpl
+
+ PUBWEAK MPU_xTaskGenericNotifyStateClearImpl
+MPU_xTaskGenericNotifyStateClearImpl:
+ b MPU_xTaskGenericNotifyStateClearImpl
+
+ PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl
+MPU_ulTaskGenericNotifyValueClearImpl:
+ b MPU_ulTaskGenericNotifyValueClearImpl
+
+ PUBWEAK MPU_xQueueGenericSendImpl
+MPU_xQueueGenericSendImpl:
+ b MPU_xQueueGenericSendImpl
+
+ PUBWEAK MPU_uxQueueMessagesWaitingImpl
+MPU_uxQueueMessagesWaitingImpl:
+ b MPU_uxQueueMessagesWaitingImpl
+
+ PUBWEAK MPU_uxQueueSpacesAvailableImpl
+MPU_uxQueueSpacesAvailableImpl:
+ b MPU_uxQueueSpacesAvailableImpl
+
+ PUBWEAK MPU_xQueueReceiveImpl
+MPU_xQueueReceiveImpl:
+ b MPU_xQueueReceiveImpl
+
+ PUBWEAK MPU_xQueuePeekImpl
+MPU_xQueuePeekImpl:
+ b MPU_xQueuePeekImpl
+
+ PUBWEAK MPU_xQueueSemaphoreTakeImpl
+MPU_xQueueSemaphoreTakeImpl:
+ b MPU_xQueueSemaphoreTakeImpl
+
+ PUBWEAK MPU_xQueueGetMutexHolderImpl
+MPU_xQueueGetMutexHolderImpl:
+ b MPU_xQueueGetMutexHolderImpl
+
+ PUBWEAK MPU_xQueueTakeMutexRecursiveImpl
+MPU_xQueueTakeMutexRecursiveImpl:
+ b MPU_xQueueTakeMutexRecursiveImpl
+
+ PUBWEAK MPU_xQueueGiveMutexRecursiveImpl
+MPU_xQueueGiveMutexRecursiveImpl:
+ b MPU_xQueueGiveMutexRecursiveImpl
+
+ PUBWEAK MPU_xQueueSelectFromSetImpl
+MPU_xQueueSelectFromSetImpl:
+ b MPU_xQueueSelectFromSetImpl
+
+ PUBWEAK MPU_xQueueAddToSetImpl
+MPU_xQueueAddToSetImpl:
+ b MPU_xQueueAddToSetImpl
+
+ PUBWEAK MPU_vQueueAddToRegistryImpl
+MPU_vQueueAddToRegistryImpl:
+ b MPU_vQueueAddToRegistryImpl
+
+ PUBWEAK MPU_vQueueUnregisterQueueImpl
+MPU_vQueueUnregisterQueueImpl:
+ b MPU_vQueueUnregisterQueueImpl
+
+ PUBWEAK MPU_pcQueueGetNameImpl
+MPU_pcQueueGetNameImpl:
+ b MPU_pcQueueGetNameImpl
+
+ PUBWEAK MPU_pvTimerGetTimerIDImpl
+MPU_pvTimerGetTimerIDImpl:
+ b MPU_pvTimerGetTimerIDImpl
+
+ PUBWEAK MPU_vTimerSetTimerIDImpl
+MPU_vTimerSetTimerIDImpl:
+ b MPU_vTimerSetTimerIDImpl
+
+ PUBWEAK MPU_xTimerIsTimerActiveImpl
+MPU_xTimerIsTimerActiveImpl:
+ b MPU_xTimerIsTimerActiveImpl
+
+ PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl
+MPU_xTimerGetTimerDaemonTaskHandleImpl:
+ b MPU_xTimerGetTimerDaemonTaskHandleImpl
+
+ PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+ b MPU_xTimerGenericCommandFromTaskImpl
+
+ PUBWEAK MPU_pcTimerGetNameImpl
+MPU_pcTimerGetNameImpl:
+ b MPU_pcTimerGetNameImpl
+
+ PUBWEAK MPU_vTimerSetReloadModeImpl
+MPU_vTimerSetReloadModeImpl:
+ b MPU_vTimerSetReloadModeImpl
+
+ PUBWEAK MPU_xTimerGetReloadModeImpl
+MPU_xTimerGetReloadModeImpl:
+ b MPU_xTimerGetReloadModeImpl
+
+ PUBWEAK MPU_uxTimerGetReloadModeImpl
+MPU_uxTimerGetReloadModeImpl:
+ b MPU_uxTimerGetReloadModeImpl
+
+ PUBWEAK MPU_xTimerGetPeriodImpl
+MPU_xTimerGetPeriodImpl:
+ b MPU_xTimerGetPeriodImpl
+
+ PUBWEAK MPU_xTimerGetExpiryTimeImpl
+MPU_xTimerGetExpiryTimeImpl:
+ b MPU_xTimerGetExpiryTimeImpl
+
+ PUBWEAK MPU_xEventGroupWaitBitsImpl
+MPU_xEventGroupWaitBitsImpl:
+ b MPU_xEventGroupWaitBitsImpl
+
+ PUBWEAK MPU_xEventGroupClearBitsImpl
+MPU_xEventGroupClearBitsImpl:
+ b MPU_xEventGroupClearBitsImpl
+
+ PUBWEAK MPU_xEventGroupSetBitsImpl
+MPU_xEventGroupSetBitsImpl:
+ b MPU_xEventGroupSetBitsImpl
+
+ PUBWEAK MPU_xEventGroupSyncImpl
+MPU_xEventGroupSyncImpl:
+ b MPU_xEventGroupSyncImpl
+
+ PUBWEAK MPU_uxEventGroupGetNumberImpl
+MPU_uxEventGroupGetNumberImpl:
+ b MPU_uxEventGroupGetNumberImpl
+
+ PUBWEAK MPU_vEventGroupSetNumberImpl
+MPU_vEventGroupSetNumberImpl:
+ b MPU_vEventGroupSetNumberImpl
+
+ PUBWEAK MPU_xStreamBufferSendImpl
+MPU_xStreamBufferSendImpl:
+ b MPU_xStreamBufferSendImpl
+
+ PUBWEAK MPU_xStreamBufferReceiveImpl
+MPU_xStreamBufferReceiveImpl:
+ b MPU_xStreamBufferReceiveImpl
+
+ PUBWEAK MPU_xStreamBufferIsFullImpl
+MPU_xStreamBufferIsFullImpl:
+ b MPU_xStreamBufferIsFullImpl
+
+ PUBWEAK MPU_xStreamBufferIsEmptyImpl
+MPU_xStreamBufferIsEmptyImpl:
+ b MPU_xStreamBufferIsEmptyImpl
+
+ PUBWEAK MPU_xStreamBufferSpacesAvailableImpl
+MPU_xStreamBufferSpacesAvailableImpl:
+ b MPU_xStreamBufferSpacesAvailableImpl
+
+ PUBWEAK MPU_xStreamBufferBytesAvailableImpl
+MPU_xStreamBufferBytesAvailableImpl:
+ b MPU_xStreamBufferBytesAvailableImpl
+
+ PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl
+MPU_xStreamBufferSetTriggerLevelImpl:
+ b MPU_xStreamBufferSetTriggerLevelImpl
+
+ PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl
+MPU_xStreamBufferNextMessageLengthBytesImpl:
+ b MPU_xStreamBufferNextMessageLengthBytesImpl
+
+/*-----------------------------------------------------------*/
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+ END
diff --git a/portable/IAR/ARM_CM52_NTZ/non_secure/port.c b/portable/IAR/ARM_CM52_NTZ/non_secure/port.c
new file mode 100644
index 0000000..76d2b24
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+++ b/portable/IAR/ARM_CM52_NTZ/non_secure/port.c
@@ -0,0 +1,2280 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU includes. */
+#include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if ( configENABLE_TRUSTZONE == 1 )
+ /* Secure components includes. */
+ #include "secure_context.h"
+ #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration settings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+ #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+ #define portUSE_PSPLIM_REGISTER 0
+#else
+ #define portUSE_PSPLIM_REGISTER 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
+#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
+#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used during system call enter and exit.
+ */
+#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE ( 3UL )
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS ( 20UL )
+#define portCPACR_CP11_POS ( 22UL )
+
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS ( 31UL )
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS ( 30UL )
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Offsets in the stack to the parameters when inside the SVC handler.
+ */
+#define portOFFSET_TO_LR ( 5 )
+#define portOFFSET_TO_PC ( 6 )
+#define portOFFSET_TO_PSR ( 7 )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
+
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+
+ /* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+ #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE_BIT ( 1UL << 0UL )
+
+/* Extract first address of the MPU region as encoded in the
+ * RBAR (Region Base Address Register) value. */
+#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
+ ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK )
+
+/* Extract last address of the MPU region as encoded in the
+ * RLAR (Region Limit Address Register) value. */
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
+ ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
+
+/* Does addr lies within [start, end] address range? */
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
+ ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
+
+/* Is the access request satisfied by the available permissions? */
+#define portIS_AUTHORIZED( accessRequest, permissions ) \
+ ( ( ( permissions ) & ( accessRequest ) ) == accessRequest )
+
+/* Max value that fits in a uint32_t type. */
+#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The maximum 24-bit number.
+ *
+ * It is needed because the systick is a 24-bit counter.
+ */
+#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
+
+/**
+ * @brief A fiddle factor to estimate the number of SysTick counts that would
+ * have occurred while the SysTick counter is stopped during tickless idle
+ * calculations.
+ */
+#define portMISSED_COUNTS_FACTOR ( 94UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR ( 0x01000000 )
+
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF FD
+ * 1111 1111 1111 1111 1111 1111 1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )
+#else
+
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF BC
+ * 1111 1111 1111 1111 1111 1111 1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ * Bit[0] = 0 ==> The task is privileged.
+ * Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
+
+/**
+ * @brief Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register.
+ */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS 1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT 0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+ #define portCONTROL_UPAC_EN ( 1UL << 7UL )
+ #define portCONTROL_PAC_EN ( 1UL << 6UL )
+ #define portCONTROL_UBTI_EN ( 1UL << 5UL )
+ #define portCONTROL_BTI_EN ( 1UL << 4UL )
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief Extract MPU region's access permissions from the Region Base Address
+ * Register (RBAR) value.
+ *
+ * @param ulRBARValue RBAR value for the MPU region.
+ *
+ * @return uint32_t Access permissions.
+ */
+ static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
+
+#if ( configENABLE_MPU == 1 )
+
+ /**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_FPU == 1 )
+
+ /**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ /**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ *
+ * The implementation in this file is weak to allow application writers to
+ * change the timer used to generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether the current execution context is interrupt.
+ *
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE
+ * otherwise.
+ */
+BaseType_t xPortIsInsideInterrupt( void );
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
+ */
+ void vSystemCallEnter( uint32_t * pulTaskStack,
+ uint32_t ulLR,
+ uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief Raise SVC for exiting from a system call.
+ */
+ void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+ void vSystemCallExit( uint32_t * pulSystemCallStack,
+ uint32_t ulLR ) PRIVILEGED_FUNCTION;
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+#if ( configENABLE_MPU == 1 )
+
+ /**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+ PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if ( configENABLE_TRUSTZONE == 1 )
+
+ /**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+ PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+ /**
+ * @brief The number of SysTick increments that make up one tick period.
+ */
+ PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
+
+ /**
+ * @brief The maximum number of tick periods that can be suppressed is
+ * limited by the 24 bit resolution of the SysTick timer.
+ */
+ PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
+
+ /**
+ * @brief Compensate for the CPU cycles that pass while the SysTick is
+ * stopped (low power functionality only).
+ */
+ PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+ __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+ {
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
+ TickType_t xModifiableIdleTime;
+
+ /* Make sure the SysTick reload value does not overflow the counter. */
+ if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+ {
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+ }
+
+ /* Enter a critical section but don't use the taskENTER_CRITICAL()
+ * method as that will mask interrupts that should exit sleep mode. */
+ __asm volatile ( "cpsid i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* If a context switch is pending or a task is waiting for the scheduler
+ * to be unsuspended then abandon the low power entry. */
+ if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+ {
+ /* Re-enable interrupts - see comments above the cpsid instruction
+ * above. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ }
+ else
+ {
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
+ /* Set the new reload value. */
+ portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+ /* Clear the SysTick count flag and set the count value back to
+ * zero. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Restart SysTick. */
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+ * set its parameter to 0 to indicate that its implementation contains
+ * its own wait for interrupt or wait for event instruction, and so wfi
+ * should not be executed again. However, the original expected idle
+ * time variable must remain unmodified, so a copy is taken. */
+ xModifiableIdleTime = xExpectedIdleTime;
+ configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+ if( xModifiableIdleTime > 0 )
+ {
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "wfi" );
+ __asm volatile ( "isb" );
+ }
+
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+ /* Re-enable interrupts to allow the interrupt that brought the MCU
+ * out of sleep mode to execute immediately. See comments above
+ * the cpsid instruction above. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* Disable interrupts again because the clock is about to be stopped
+ * and interrupts that execute while the clock is stopped will increase
+ * any slippage between the time maintained by the RTOS and calendar
+ * time. */
+ __asm volatile ( "cpsid i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* Disable the SysTick clock without reading the
+ * portNVIC_SYSTICK_CTRL_REG register to ensure the
+ * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
+ * the time the SysTick is stopped for is accounted for as best it can
+ * be, but using the tickless mode will inevitably result in some tiny
+ * drift of the time maintained by the kernel with respect to calendar
+ * time*/
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Determine whether the SysTick has already counted to zero. */
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ uint32_t ulCalculatedLoadValue;
+
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+ /* Don't allow a tiny value, or values that have somehow
+ * underflowed because the post sleep hook did something
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ {
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+ /* As the pending tick will be processed as soon as this
+ * function exits, the tick value maintained by the tick is stepped
+ * forward by one less than the time spent waiting. */
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+ }
+ else
+ {
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
+ * periods (not the ulReload value which accounted for part
+ * ticks). */
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
+
+ /* How many complete tick periods passed while the processor
+ * was waiting? */
+ ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+ /* The reload value is set to whatever fraction of a single tick
+ * period remains. */
+ portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+ }
+
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
+ vTaskStepTick( ulCompleteTickPeriods );
+
+ /* Exit with interrupts enabled. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ }
+ }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Calculate the constants required to configure the tick interrupt. */
+ #if ( configUSE_TICKLESS_IDLE == 1 )
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
+ #endif /* configUSE_TICKLESS_IDLE */
+
+ /* Stop and reset SysTick.
+ *
+ * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+ * enable SysTick without first selecting a valid clock source. We trigger
+ * the bug if we change clock sources from a clock with a zero clock period
+ * to one with a nonzero clock period and enable Systick at the same time.
+ * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+ * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+ volatile uint32_t ulDummy = 0UL;
+
+ /* A function that implements a task must not exit or attempt to return to
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()
+ * to be triggered if configASSERT() is defined, then stop here so
+ * application writers can catch the error. */
+ configASSERT( ulCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+
+ while( ulDummy == 0 )
+ {
+ /* This file calls prvTaskExitError() after the scheduler has been
+ * started to remove a compiler warning about the function being
+ * defined but never called. ulDummy is used purely to quieten other
+ * warnings about code appearing after this function is called - making
+ * ulDummy volatile makes the compiler think the function could return
+ * and therefore not output an 'unreachable code' warning for code that
+ * appears after it. */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulAccessPermissions = 0;
+
+ if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY )
+ {
+ ulAccessPermissions = tskMPU_READ_PERMISSION;
+ }
+
+ if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE )
+ {
+ ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION );
+ }
+
+ return ulAccessPermissions;
+ }
+
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_functions_start__;
+ extern uint32_t * __privileged_functions_end__;
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ extern uint32_t * __unprivileged_flash_start__;
+ extern uint32_t * __unprivileged_flash_end__;
+ extern uint32_t * __privileged_sram_start__;
+ extern uint32_t * __privileged_sram_end__;
+ #else /* if defined( __ARMCC_VERSION ) */
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_functions_start__[];
+ extern uint32_t __privileged_functions_end__[];
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ extern uint32_t __unprivileged_flash_start__[];
+ extern uint32_t __unprivileged_flash_end__[];
+ extern uint32_t __privileged_sram_start__[];
+ extern uint32_t __privileged_sram_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+
+ /* The only permitted number of regions are 8 or 16. */
+ configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
+
+ /* MAIR0 - Index 0. */
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ /* MAIR0 - Index 1. */
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* Setup privileged flash as Read Only so that privileged tasks can
+ * read it but not modify. */
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged flash as Read Only by both privileged and
+ * unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged syscalls flash as Read Only by both privileged
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup RAM containing kernel data for privileged access only. */
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Enable mem fault. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
+
+ /* Enable MPU with privileged background access i.e. unmapped
+ * regions have privileged access. */
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
+ }
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_FPU == 1 )
+
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ /* Enable non-secure access to the FPU. */
+ SecureInit_EnableNSFPUAccess();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+ * unprivileged code should be able to access FPU. CP11 should be
+ * programmed to the same value as CP10. */
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+ );
+
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+ * context on exception entry and restore on exception return.
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+ }
+
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Set a PendSV to request a context switch. */
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ portDISABLE_INTERRUPTS();
+ ulCriticalNesting++;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ configASSERT( ulCriticalNesting );
+ ulCriticalNesting--;
+
+ if( ulCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+ uint32_t ulPreviousMask;
+
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ traceISR_EXIT_TO_SCHEDULER();
+ /* Pend a context switch. */
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+ }
+ else
+ {
+ traceISR_EXIT();
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ uint32_t ulPC;
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ uint32_t ulR0, ulR1;
+ extern TaskHandle_t pxCurrentTCB;
+ #if ( configENABLE_MPU == 1 )
+ uint32_t ulControl, ulIsTaskPrivileged;
+ #endif /* configENABLE_MPU */
+ #endif /* configENABLE_TRUSTZONE */
+ uint8_t ucSVCNumber;
+
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+ * R12, LR, PC, xPSR. */
+ ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ];
+ ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+ switch( ucSVCNumber )
+ {
+ #if ( configENABLE_TRUSTZONE == 1 )
+ case portSVC_ALLOCATE_SECURE_CONTEXT:
+
+ /* R0 contains the stack size passed as parameter to the
+ * vPortAllocateSecureContext function. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+
+ #if ( configENABLE_MPU == 1 )
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+ }
+ #else /* if ( configENABLE_MPU == 1 ) */
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+ }
+ #endif /* configENABLE_MPU */
+
+ configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+ SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+ break;
+
+ case portSVC_FREE_SECURE_CONTEXT:
+
+ /* R0 contains TCB being freed and R1 contains the secure
+ * context handle to be freed. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+ ulR1 = pulCallerStackAddress[ 1 ];
+
+ /* Free the secure context. */
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+ break;
+ #endif /* configENABLE_TRUSTZONE */
+
+ case portSVC_START_SCHEDULER:
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
+
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ #if ( configENABLE_FPU == 1 )
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
+ #endif /* configENABLE_FPU */
+
+ /* Setup the context of the first task so that the first task starts
+ * executing. */
+ vRestoreContextOfFirstTask();
+ break;
+
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ case portSVC_RAISE_PRIVILEGE:
+
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ vRaisePrivilege();
+ }
+ break;
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ #if ( configENABLE_MPU == 1 )
+ case portSVC_YIELD:
+ vPortYield();
+ break;
+ #endif /* configENABLE_MPU == 1 */
+
+ default:
+ /* Incorrect SVC call. */
+ configASSERT( pdFALSE );
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ void vSystemCallEnter( uint32_t * pulTaskStack,
+ uint32_t ulLR,
+ uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
+ {
+ extern TaskHandle_t pxCurrentTCB;
+ extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
+ xMPU_SETTINGS * pxMpuSettings;
+ uint32_t * pulSystemCallStack;
+ uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
+
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ #endif /* #if defined( __ARMCC_VERSION ) */
+
+ ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+ pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+
+ /* Checks:
+ * 1. SVC is raised from the system call section (i.e. application is
+ * not raising SVC directly).
+ * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+ * it is non-NULL only during the execution of a system call (i.e.
+ * between system call enter and exit).
+ * 3. System call is not for a kernel API disabled by the configuration
+ * in FreeRTOSConfig.h.
+ * 4. We do not need to check that ucSystemCallNumber is within range
+ * because the assembly SVC handler checks that before calling
+ * this function.
+ */
+ if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+ ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+ ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
+ {
+ pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+ /* Hardware Saved Stack Frame Size upon Exception entry:
+ * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+ * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+ */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ {
+ if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+ {
+ /* Extended frame i.e. FPU in use. */
+ ulHardwareSavedExceptionFrameSize = 26;
+ __asm volatile (
+ " vpush {s0} \n" /* Trigger lazy stacking. */
+ " vpop {s0} \n" /* Nullify the affect of the above instruction. */
+ ::: "memory"
+ );
+ }
+ else
+ {
+ /* Standard frame i.e. FPU not in use. */
+ ulHardwareSavedExceptionFrameSize = 8;
+ }
+ }
+ #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ {
+ ulHardwareSavedExceptionFrameSize = 8;
+ }
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+
+ /* Make space on the system call stack for the stack frame. */
+ pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
+
+ /* Copy the stack frame. */
+ for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
+ {
+ pulSystemCallStack[ i ] = pulTaskStack[ i ];
+ }
+
+ /* Store the value of the Link Register before the SVC was raised.
+ * It contains the address of the caller of the System Call entry
+ * point (i.e. the caller of the MPU_<API>). We need to restore it
+ * when we exit from the system call. */
+ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
+ /* Store the value of the PSPLIM register before the SVC was raised.
+ * We need to restore it when we exit from the system call. */
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
+
+ /* Use the pulSystemCallStack in thread mode. */
+ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ }
+ #endif
+
+ /* Start executing the system call upon returning from this handler. */
+ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
+ /* Raise a request to exit from the system call upon finishing the
+ * system call. */
+ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
+ /* Remember the location where we should copy the stack frame when we exit from
+ * the system call. */
+ pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
+
+ /* Record if the hardware used padding to force the stack pointer
+ * to be double word aligned. */
+ if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+ {
+ pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
+ }
+ else
+ {
+ pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
+ }
+
+ /* We ensure in pxPortInitialiseStack that the system call stack is
+ * double word aligned and therefore, there is no need of padding.
+ * Clear the bit[9] of stacked xPSR. */
+ pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+ /* Raise the privilege for the duration of the system call. */
+ __asm volatile (
+ " mrs r0, control \n" /* Obtain current control value. */
+ " movs r1, #1 \n" /* r1 = 1. */
+ " bics r0, r1 \n" /* Clear nPRIV bit. */
+ " msr control, r0 \n" /* Write back new control value. */
+ ::: "r0", "r1", "memory"
+ );
+ }
+ }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
+ }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ void vSystemCallExit( uint32_t * pulSystemCallStack,
+ uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+ {
+ extern TaskHandle_t pxCurrentTCB;
+ xMPU_SETTINGS * pxMpuSettings;
+ uint32_t * pulTaskStack;
+ uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
+
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_functions_start__;
+ extern uint32_t * __privileged_functions_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_functions_start__[];
+ extern uint32_t __privileged_functions_end__[];
+ #endif /* #if defined( __ARMCC_VERSION ) */
+
+ ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+ pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+
+ /* Checks:
+ * 1. SVC is raised from the privileged code (i.e. application is not
+ * raising SVC directly). This SVC is only raised from
+ * vRequestSystemCallExit which is in the privileged code section.
+ * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+ * this means that we previously entered a system call and the
+ * application is not attempting to exit without entering a system
+ * call.
+ */
+ if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+ ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+ ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
+ {
+ pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+ /* Hardware Saved Stack Frame Size upon Exception entry:
+ * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+ * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+ */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ {
+ if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+ {
+ /* Extended frame i.e. FPU in use. */
+ ulHardwareSavedExceptionFrameSize = 26;
+ __asm volatile (
+ " vpush {s0} \n" /* Trigger lazy stacking. */
+ " vpop {s0} \n" /* Nullify the affect of the above instruction. */
+ ::: "memory"
+ );
+ }
+ else
+ {
+ /* Standard frame i.e. FPU not in use. */
+ ulHardwareSavedExceptionFrameSize = 8;
+ }
+ }
+ #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ {
+ ulHardwareSavedExceptionFrameSize = 8;
+ }
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+
+ /* Make space on the task stack for the stack frame. */
+ pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
+
+ /* Copy the stack frame. */
+ for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
+ {
+ pulTaskStack[ i ] = pulSystemCallStack[ i ];
+ }
+
+ /* Use the pulTaskStack in thread mode. */
+ __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+ /* Return to the caller of the System Call entry point (i.e. the
+ * caller of the MPU_<API>). */
+ pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+ /* Ensure that LR has a valid value.*/
+ pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+ /* Restore the PSPLIM register to what it was at the time of
+ * system call entry. */
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
+
+ /* If the hardware used padding to force the stack pointer
+ * to be double word aligned, set the stacked xPSR bit[9],
+ * otherwise clear it. */
+ if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+ {
+ pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
+ }
+ else
+ {
+ pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+ }
+
+ /* This is not NULL only for the duration of the system call. */
+ pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+ /* Drop the privilege before returning to the thread mode. */
+ __asm volatile (
+ " mrs r0, control \n" /* Obtain current control value. */
+ " movs r1, #1 \n" /* r1 = 1. */
+ " orrs r0, r1 \n" /* Set nPRIV bit. */
+ " msr control, r0 \n" /* Write back new control value. */
+ ::: "r0", "r1", "memory"
+ );
+ }
+ }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
+ {
+ BaseType_t xTaskIsPrivileged = pdFALSE;
+ const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+ if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ {
+ xTaskIsPrivileged = pdTRUE;
+ }
+
+ return xTaskIsPrivileged;
+ }
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ StackType_t * pxEndOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters,
+ BaseType_t xRunPrivileged,
+ xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulIndex = 0;
+ uint32_t ulControl = 0x0;
+
+ xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+ ulIndex++;
+
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
+ ulIndex++;
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+ ulIndex++;
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+ ulIndex++;
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
+ ulIndex++;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Check PACBTI security feature configuration before pushing the
+ * CONTROL register's value on task's TCB. */
+ ulControl = prvConfigurePACBTI( pdFALSE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
+ if( xRunPrivileged == pdTRUE )
+ {
+ xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
+ ulIndex++;
+ }
+ else
+ {
+ xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
+ ulIndex++;
+ }
+
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+ ulIndex++;
+
+ #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+ {
+ /* Ensure that the system call stack is double word aligned. */
+ xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+ xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+ ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+ xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+ xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+ ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+ ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+ /* This is not NULL only for the duration of a system call. */
+ xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+ }
+ #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+ ulIndex++;
+ }
+ }
+ #endif /* configENABLE_PAC */
+
+ return &( xMPUSettings->ulContext[ ulIndex ] );
+ }
+
+#else /* configENABLE_MPU */
+
+ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ StackType_t * pxEndOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters ) /* PRIVILEGED_FUNCTION */
+ {
+ /* Simulate the stack frame as it would be created by a context switch
+ * interrupt. */
+ #if ( portPRELOAD_REGISTERS == 0 )
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #else /* portPRELOAD_REGISTERS */
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #endif /* portPRELOAD_REGISTERS */
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = ulTaskPacKey[ i ];
+ }
+ }
+ #endif /* configENABLE_PAC */
+
+ return pxTopOfStack;
+ }
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+ * for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * SVC_Handler and PendSV_Handler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+ {
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+ {
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * First, determine the number of priority bits available. Write to all
+ * possible bits in the priority setting for SVCall. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Check that the bits not implemented in hardware are zero in
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
+
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
+ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+ portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Set the CONTROL register value based on PACBTI security feature
+ * configuration before starting the first task. */
+ ( void ) prvConfigurePACBTI( pdTRUE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
+ #if ( configENABLE_MPU == 1 )
+ {
+ /* Setup the Memory Protection Unit (MPU). */
+ prvSetupMPU();
+ }
+ #endif /* configENABLE_MPU */
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ * here already. */
+ vPortSetupTimerInterrupt();
+
+ /* Initialize the critical nesting count ready for the first task. */
+ ulCriticalNesting = 0;
+
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+ {
+ xSchedulerRunning = pdTRUE;
+ }
+ #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
+
+ /* Start the first task. */
+ vStartFirstTask();
+
+ /* Should never get here as the tasks will now be executing. Call the task
+ * exit error function to prevent compiler warnings about a static function
+ * not being called in the case that the application writer overrides this
+ * functionality by defining configTASK_RETURN_ADDRESS. Call
+ * vTaskSwitchContext() so link time optimization does not remove the
+ * symbol. */
+ vTaskSwitchContext();
+ prvTaskExitError();
+
+ /* Should not get here. */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Not implemented in ports where there is nothing to return to.
+ * Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+ const struct xMEMORY_REGION * const xRegions,
+ StackType_t * pxBottomOfStack,
+ configSTACK_DEPTH_TYPE uxStackDepth )
+ {
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+ int32_t lIndex = 0;
+
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_sram_start__;
+ extern uint32_t * __privileged_sram_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_sram_start__[];
+ extern uint32_t __privileged_sram_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+
+ /* Setup MAIR0. */
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* This function is called automatically when the task is created - in
+ * which case the stack region parameters will be valid. At all other
+ * times the stack parameters will not be valid and it is assumed that
+ * the stack region has already been configured. */
+ if( uxStackDepth > 0 )
+ {
+ ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
+
+ /* If the stack is within the privileged SRAM, do not protect it
+ * using a separate MPU region. This is needed because privileged
+ * SRAM is already protected using an MPU region and ARMv8-M does
+ * not allow overlapping MPU regions. */
+ if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+ ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
+ {
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
+ }
+ else
+ {
+ /* Define the region that allows access to the stack. */
+ ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+ }
+ }
+
+ /* User supplied configurable regions. */
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+ {
+ /* If xRegions is NULL i.e. the task has not specified any MPU
+ * region, the else part ensures that all the configurable MPU
+ * regions are invalidated. */
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+ {
+ /* Translate the generic region definition contained in xRegions
+ * into the ARMv8 specific MPU settings that are then stored in
+ * xMPUSettings. */
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ /* Start address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE );
+
+ /* RO/RW. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+ }
+ else
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+ }
+
+ /* XN. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+ }
+
+ /* End Address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* PXN. */
+ #if ( portARMV8M_MINOR_VERSION >= 1 )
+ {
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+ }
+ }
+ #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
+ /* Normal memory/ Device memory. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+ {
+ /* Attr1 in MAIR0 is configured as device memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+ }
+ else
+ {
+ /* Attr0 in MAIR0 is configured as normal memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+ }
+ }
+ else
+ {
+ /* Invalidate the region. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+ }
+
+ lIndex++;
+ }
+ }
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
+ uint32_t ulBufferLength,
+ uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
+
+ {
+ uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
+ BaseType_t xAccessGranted = pdFALSE;
+ const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ {
+ xAccessGranted = pdTRUE;
+ }
+ else
+ {
+ if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
+ {
+ ulBufferStartAddress = ( uint32_t ) pvBuffer;
+ ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
+
+ for( i = 0; i < portTOTAL_NUM_REGIONS; i++ )
+ {
+ /* Is the MPU region enabled? */
+ if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE )
+ {
+ if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
+ portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ),
+ portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) &&
+ portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
+ portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ),
+ portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) &&
+ portIS_AUTHORIZED( ulAccessRequested,
+ prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) )
+ {
+ xAccessGranted = pdTRUE;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ return xAccessGranted;
+ }
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortIsInsideInterrupt( void )
+{
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
+
+ /* Obtain the number of the currently executing interrupt. Interrupt Program
+ * Status Register (IPSR) holds the exception number of the currently-executing
+ * exception or zero for Thread mode.*/
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ if( ulCurrentInterrupt == 0 )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+ void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+ int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+ xMPU_SETTINGS * xTaskMpuSettings;
+
+ ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+ ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+ xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+ xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+ }
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+ void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+ int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+ xMPU_SETTINGS * xTaskMpuSettings;
+
+ ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+ ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+ xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+ xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+ }
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+ BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+ BaseType_t xAccessGranted = pdFALSE;
+ const xMPU_SETTINGS * xTaskMpuSettings;
+
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else
+ {
+ xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+ ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+ ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+ if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ {
+ xAccessGranted = pdTRUE;
+ }
+ else
+ {
+ if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+ {
+ xAccessGranted = pdTRUE;
+ }
+ }
+ }
+
+ return xAccessGranted;
+ }
+
+ #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+ BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+ {
+ ( void ) lInternalIndexOfKernelObject;
+
+ /* If Access Control List feature is not used, all the tasks have
+ * access to all the kernel objects. */
+ return pdTRUE;
+ }
+
+ #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+ {
+ uint32_t ulControl = 0x0;
+
+ /* Ensure that PACBTI is implemented. */
+ configASSERT( portID_ISAR5_REG != 0x0 );
+
+ /* Enable UsageFault exception. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+ }
+ #endif
+
+ #if ( configENABLE_BTI == 1 )
+ {
+ ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+ }
+ #endif
+
+ if( xWriteControlRegister == pdTRUE )
+ {
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+ }
+
+ return ulControl;
+ }
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM52_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM52_NTZ/non_secure/portasm.h
new file mode 100644
index 0000000..b7021b0
--- /dev/null
+++ b/portable/IAR/ARM_CM52_NTZ/non_secure/portasm.h
@@ -0,0 +1,114 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kernel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/portable/IAR/ARM_CM52_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM52_NTZ/non_secure/portasm.s
new file mode 100644
index 0000000..ba6e8e9
--- /dev/null
+++ b/portable/IAR/ARM_CM52_NTZ/non_secure/portasm.s
@@ -0,0 +1,456 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+/* Including FreeRTOSConfig.h here will cause build errors if the header file
+contains code not understood by the assembler - for example the 'extern' keyword.
+To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
+the code is included in C files but excluded by the preprocessor in assembly
+files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
+#include "FreeRTOSConfig.h"
+
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
+#ifndef configUSE_MPU_WRAPPERS_V1
+ #define configUSE_MPU_WRAPPERS_V1 0
+#endif
+
+ EXTERN pxCurrentTCB
+ EXTERN vTaskSwitchContext
+ EXTERN vPortSVCHandler_C
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+ EXTERN vSystemCallEnter
+ EXTERN vSystemCallExit
+#endif
+
+ PUBLIC xIsPrivileged
+ PUBLIC vResetPrivilege
+ PUBLIC vRestoreContextOfFirstTask
+ PUBLIC vRaisePrivilege
+ PUBLIC vStartFirstTask
+ PUBLIC ulSetInterruptMask
+ PUBLIC vClearInterruptMask
+ PUBLIC PendSV_Handler
+ PUBLIC SVC_Handler
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+ SECTION .text:CODE:NOROOT(2)
+ THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+ mrs r0, control /* r0 = CONTROL. */
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ ite ne
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
+ bx lr /* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+ mrs r0, control /* r0 = CONTROL. */
+ orr r0, r0, #1 /* r0 = r0 | 1. */
+ msr control, r0 /* CONTROL = r0. */
+ bx lr /* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+ SECTION privileged_functions:CODE:NOROOT(2)
+ THUMB
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+vRestoreContextOfFirstTask:
+ program_mpu_first_task:
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r0, [r2] /* r0 = pxCurrentTCB. */
+
+ dmb /* Complete outstanding transfers before disabling MPU. */
+ ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r2, [r1] /* Read the value of MPU_CTRL. */
+ bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+ str r2, [r1] /* Disable MPU. */
+
+ adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+ ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ str r1, [r2] /* Program MAIR0. */
+
+ adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+ ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
+
+ movs r3, #4 /* r3 = 4. */
+ str r3, [r1] /* Program RNR = 4. */
+ ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ movs r3, #8 /* r3 = 8. */
+ str r3, [r1] /* Program RNR = 8. */
+ ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ movs r3, #12 /* r3 = 12. */
+ str r3, [r1] /* Program RNR = 12. */
+ ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ #endif /* configTOTAL_MPU_REGIONS == 16 */
+
+ ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r2, [r1] /* Read the value of MPU_CTRL. */
+ orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+ str r2, [r1] /* Enable MPU. */
+ dsb /* Force memory writes before continuing. */
+
+ restore_context_first_task:
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r0, [r2] /* r0 = pxCurrentTCB.*/
+ ldr r1, [r0] /* r1 = Location of saved context in TCB. */
+
+ restore_special_regs_first_task:
+ #if ( configENABLE_PAC == 1 )
+ ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */
+ msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_1, r3
+ msr PAC_KEY_P_2, r4
+ msr PAC_KEY_P_3, r5
+ clrm {r2-r5} /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
+ ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
+ msr psp, r2
+ msr psplim, r3
+ msr control, r4
+
+ restore_general_regs_first_task:
+ ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */
+ stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */
+ ldmdb r1!, {r4-r11} /* r4-r11 restored. */
+
+ restore_context_done_first_task:
+ str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */
+ mov r0, #0
+ msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
+ bx lr
+
+#else /* configENABLE_MPU */
+
+vRestoreContextOfFirstTask:
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r1, [r2] /* Read pxCurrentTCB. */
+ ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_PAC == 1 )
+ ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */
+ msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_2, r2
+ msr PAC_KEY_P_1, r3
+ msr PAC_KEY_P_0, r4
+ clrm {r1-r4} /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
+ ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+ msr psplim, r1 /* Set this task's PSPLIM value. */
+ mrs r1, control /* Obtain current control register value. */
+ orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
+ msr control, r1 /* Write back the new control register value. */
+ adds r0, #32 /* Discard everything up to r0. */
+ msr psp, r0 /* This is now the new top of stack to use in the task. */
+ isb
+ mov r0, #0
+ msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
+ bx r2 /* Finally, branch to EXC_RETURN. */
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+ mrs r0, control /* Read the CONTROL register. */
+ bic r0, r0, #1 /* Clear the bit 0. */
+ msr control, r0 /* Write back the new CONTROL value. */
+ bx lr /* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+ ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
+ ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
+ ldr r0, [r0] /* The first entry in vector table is stack pointer. */
+ msr msp, r0 /* Set the MSP back to the start of the stack. */
+ cpsie i /* Globally enable interrupts. */
+ cpsie f
+ dsb
+ isb
+ svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMask:
+ mrs r0, basepri /* r0 = basepri. Return original basepri value. */
+ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+ msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ dsb
+ isb
+ bx lr /* Return. */
+/*-----------------------------------------------------------*/
+
+vClearInterruptMask:
+ msr basepri, r0 /* basepri = ulMask. */
+ dsb
+ isb
+ bx lr /* Return. */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+PendSV_Handler:
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r0, [r2] /* r0 = pxCurrentTCB. */
+ ldr r1, [r0] /* r1 = Location in TCB where the context should be saved. */
+ mrs r2, psp /* r2 = PSP. */
+
+ save_general_regs:
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ add r2, r2, #0x20 /* Move r2 to location where s0 is saved. */
+ tst lr, #0x10
+ ittt eq
+ vstmiaeq r1!, {s16-s31} /* Store s16-s31. */
+ vldmiaeq r2, {s0-s16} /* Copy hardware saved FP context into s0-s16. */
+ vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */
+ sub r2, r2, #0x20 /* Set r2 back to the location of hardware saved context. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+ stmia r1!, {r4-r11} /* Store r4-r11. */
+ ldmia r2, {r4-r11} /* Copy the hardware saved context into r4-r11. */
+ stmia r1!, {r4-r11} /* Store the hardware saved context. */
+
+ save_special_regs:
+ mrs r3, psplim /* r3 = PSPLIM. */
+ mrs r4, control /* r4 = CONTROL. */
+ stmia r1!, {r2-r4, lr} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+ #if ( configENABLE_PAC == 1 )
+ mrs r2, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */
+ mrs r3, PAC_KEY_P_1
+ mrs r4, PAC_KEY_P_2
+ mrs r5, PAC_KEY_P_3
+ stmia r1!, {r2-r5} /* Store the task's dedicated PAC key on the task's context. */
+ clrm {r2-r5} /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
+
+ str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */
+
+ select_next_task:
+ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+ msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ dsb
+ isb
+ bl vTaskSwitchContext
+ mov r0, #0 /* r0 = 0. */
+ msr basepri, r0 /* Enable interrupts. */
+
+ program_mpu:
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r0, [r2] /* r0 = pxCurrentTCB. */
+
+ dmb /* Complete outstanding transfers before disabling MPU. */
+ ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r2, [r1] /* Read the value of MPU_CTRL. */
+ bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+ str r2, [r1] /* Disable MPU. */
+
+ adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+ ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ str r1, [r2] /* Program MAIR0. */
+
+ adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+ ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
+
+ movs r3, #4 /* r3 = 4. */
+ str r3, [r1] /* Program RNR = 4. */
+ ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ movs r3, #8 /* r3 = 8. */
+ str r3, [r1] /* Program RNR = 8. */
+ ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ movs r3, #12 /* r3 = 12. */
+ str r3, [r1] /* Program RNR = 12. */
+ ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ #endif /* configTOTAL_MPU_REGIONS == 16 */
+
+ ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r2, [r1] /* Read the value of MPU_CTRL. */
+ orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+ str r2, [r1] /* Enable MPU. */
+ dsb /* Force memory writes before continuing. */
+
+ restore_context:
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r0, [r2] /* r0 = pxCurrentTCB.*/
+ ldr r1, [r0] /* r1 = Location of saved context in TCB. */
+
+ restore_special_regs:
+ #if ( configENABLE_PAC == 1 )
+ ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */
+ msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_1, r3
+ msr PAC_KEY_P_2, r4
+ msr PAC_KEY_P_3, r5
+ clrm {r2-r5} /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
+ ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
+ msr psp, r2
+ msr psplim, r3
+ msr control, r4
+
+ restore_general_regs:
+ ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */
+ stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */
+ ldmdb r1!, {r4-r11} /* r4-r11 restored. */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ tst lr, #0x10
+ ittt eq
+ vldmdbeq r1!, {s0-s16} /* s0-s16 contain hardware saved FP context. */
+ vstmiaeq r2!, {s0-s16} /* Copy hardware saved FP context on the task stack. */
+ vldmdbeq r1!, {s16-s31} /* Restore s16-s31. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+
+ restore_context_done:
+ str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */
+ bx lr
+
+#else /* configENABLE_MPU */
+
+PendSV_Handler:
+ mrs r0, psp /* Read PSP in r0. */
+#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ it eq
+ vstmdbeq r0!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */
+#endif /* configENABLE_FPU || configENABLE_MVE */
+
+ mrs r2, psplim /* r2 = PSPLIM. */
+ mov r3, lr /* r3 = LR/EXC_RETURN. */
+ stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */
+
+#if ( configENABLE_PAC == 1 )
+ mrs r1, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */
+ mrs r2, PAC_KEY_P_2
+ mrs r3, PAC_KEY_P_1
+ mrs r4, PAC_KEY_P_0
+ stmdb r0!, {r1-r4} /* Store the task's dedicated PAC key on the stack. */
+ clrm {r1-r4} /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r1, [r2] /* Read pxCurrentTCB. */
+ str r0, [r1] /* Save the new top of stack in TCB. */
+
+ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+ msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ dsb
+ isb
+ bl vTaskSwitchContext
+ mov r0, #0 /* r0 = 0. */
+ msr basepri, r0 /* Enable interrupts. */
+
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r1, [r2] /* Read pxCurrentTCB. */
+ ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+
+#if ( configENABLE_PAC == 1 )
+ ldmia r0!, {r2-r5} /* Read task's dedicated PAC key from stack. */
+ msr PAC_KEY_P_3, r2 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_2, r3
+ msr PAC_KEY_P_1, r4
+ msr PAC_KEY_P_0, r5
+ clrm {r2-r5} /* Clear r2-r5. */
+#endif /* configENABLE_PAC */
+
+ ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+
+#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ it eq
+ vldmiaeq r0!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */
+#endif /* configENABLE_FPU || configENABLE_MVE */
+
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */
+ msr psp, r0 /* Remember the new top of stack for the task. */
+ bx r3
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+SVC_Handler:
+ tst lr, #4
+ ite eq
+ mrseq r0, msp
+ mrsne r0, psp
+
+ ldr r1, [r0, #24]
+ ldrb r2, [r1, #-2]
+ cmp r2, #NUM_SYSTEM_CALLS
+ blt syscall_enter
+ cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */
+ beq syscall_exit
+ b vPortSVCHandler_C
+
+ syscall_enter:
+ mov r1, lr
+ b vSystemCallEnter
+
+ syscall_exit:
+ mov r1, lr
+ b vSystemCallExit
+
+#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+SVC_Handler:
+ tst lr, #4
+ ite eq
+ mrseq r0, msp
+ mrsne r0, psp
+ b vPortSVCHandler_C
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+ END
diff --git a/portable/IAR/ARM_CM52_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM52_NTZ/non_secure/portmacro.h
new file mode 100644
index 0000000..19de84e
--- /dev/null
+++ b/portable/IAR/ARM_CM52_NTZ/non_secure/portmacro.h
@@ -0,0 +1,87 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright (c) 2025 Arm Technology (China) Co., Ltd.All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_MVE
+ #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.
+#endif /* configENABLE_MVE */
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME "Cortex-M52"
+#define portHAS_ARMV8M_MAIN_EXTENSION 1
+#define portARMV8M_MINOR_VERSION 1
+#define portDONT_DISCARD __root
+/*-----------------------------------------------------------*/
+
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+#pragma diag_suppress=Be006
+#pragma diag_suppress=Pa082
+/*-----------------------------------------------------------*/
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
diff --git a/portable/IAR/ARM_CM52_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM52_NTZ/non_secure/portmacrocommon.h
new file mode 100644
index 0000000..f373bca
--- /dev/null
+++ b/portable/IAR/ARM_CM52_NTZ/non_secure/portmacrocommon.h
@@ -0,0 +1,582 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern BaseType_t xPortIsInsideInterrupt( void );
+
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+ /**
+ * @brief Generates 128-bit task's random PAC key.
+ *
+ * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+ * filled with a 128-bit random number.
+ */
+ void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
+
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+ /* Define to 8 for backward compatibility. */
+ #define configTOTAL_MPU_REGIONS ( 8UL )
+#endif
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ * Bit[7:4] - 0000 - Device Memory
+ * Bit[3:2] - 00 --> Device-nGnRnE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
+ * Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ /**
+ * @brief Settings to define an MPU region.
+ */
+ typedef struct MPURegionSettings
+ {
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+ } MPURegionSettings_t;
+
+ #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+ #ifndef configSYSTEM_CALL_STACK_SIZE
+ #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
+ #endif
+
+ /**
+ * @brief System call stack.
+ */
+ typedef struct SYSTEM_CALL_STACK_INFO
+ {
+ uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
+ uint32_t * pulSystemCallStack;
+ uint32_t * pulSystemCallStackLimit;
+ uint32_t * pulTaskStack;
+ uint32_t ulLinkRegisterAtSystemCallEntry;
+ uint32_t ulStackLimitRegisterAtSystemCallEntry;
+ } xSYSTEM_CALL_STACK_INFO;
+
+ #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+ /**
+ * @brief MPU settings as stored in the TCB.
+ */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+ * 16 17 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 71
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ * 16 17 8 8 5 1
+ */
+ #define MAX_CONTEXT_SIZE 55
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | | | PC, xPSR | EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+ * 16 17 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 70
+
+ #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | |
+ * | | | | PC, xPSR | EXC_RETURN | |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ * 16 17 8 8 4 1
+ */
+ #define MAX_CONTEXT_SIZE 54
+
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +----------+-----------------+------------------------------+------------+-----+
+ *
+ * <---------><----------------><------------------------------><-----------><---->
+ * 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 38
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ * 8 8 5 1
+ */
+ #define MAX_CONTEXT_SIZE 22
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+----------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | PC, xPSR | EXC_RETURN | | |
+ * +----------+-----------------+----------------------+------------+-----+
+ *
+ * <---------><----------------><----------------------><-----------><---->
+ * 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 37
+
+ #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+
+ /*
+ * +----------+-----------------+----------------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | |
+ * | | PC, xPSR | EXC_RETURN | |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ * 8 8 4 1
+ */
+ #define MAX_CONTEXT_SIZE 21
+
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+
+ /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+ #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+ #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+
+ /* Size of an Access Control List (ACL) entry in bits. */
+ #define portACL_ENTRY_SIZE_BITS ( 32U )
+
+ typedef struct MPU_SETTINGS
+ {
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+ uint32_t ulContext[ MAX_CONTEXT_SIZE ];
+ uint32_t ulTaskFlags;
+
+ #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+ xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+ #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+ uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
+ #endif
+ #endif
+ } xMPU_SETTINGS;
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#if ( configASSERT_DEFINED == 1 )
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT 100
+#define portSVC_FREE_SECURE_CONTEXT 101
+#define portSVC_START_SCHEDULER 102
+#define portSVC_RAISE_PRIVILEGE 103
+#define portSVC_SYSTEM_CALL_EXIT 104
+#define portSVC_YIELD 105
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#if ( configENABLE_MPU == 1 )
+ #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() vPortYield()
+#else
+ #define portYIELD() vPortYield()
+ #define portYIELD_WITHIN_API() vPortYield()
+#endif
+
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ extern BaseType_t xPortIsTaskPrivileged( void );
+
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #else
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+ #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+ static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint32_t ulReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ulReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+ #endif
+
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+ #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+ #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACROCOMMON_H */
diff --git a/portable/ThirdParty/GCC/ARM_TFM/README.md b/portable/ThirdParty/GCC/ARM_TFM/README.md
index bc594b1..544fb81 100644
--- a/portable/ThirdParty/GCC/ARM_TFM/README.md
+++ b/portable/ThirdParty/GCC/ARM_TFM/README.md
@@ -2,8 +2,8 @@
This port adds the support that FreeRTOS applications can call the secure
services in Trusted Firmware M(TF-M) through Platform Security Architecture
-(PSA) API based on the ARM Cortex-M23, Cortex-M33, Cortex-M55 and Cortex-M85
-platform.
+(PSA) API based on the ARM Cortex-M23, Cortex-M33, Cortex-M52, Cortex-M55
+and Cortex-M85 platform.
The Platform Security Architecture (PSA) makes it quicker, easier and cheaper
to design security into a device from the ground up. PSA is made up of four key
@@ -38,7 +38,7 @@
## Build the Non-Secure Side
-Please copy all the files in `freertos_kernel/portable/GCC/ARM_CM[23|33|55|85]_NTZ` into the `freertos_kernel/portable/ThirdParty/GCC/ARM_TFM` folder before using this port. Note that TrustZone is enabled in this port. The TF-M runs in the Secure Side.
+Please copy all the files in `freertos_kernel/portable/GCC/ARM_CM[23|33|52|55|85]_NTZ` into the `freertos_kernel/portable/ThirdParty/GCC/ARM_TFM` folder before using this port. Note that TrustZone is enabled in this port. The TF-M runs in the Secure Side.
Please call the API `tfm_ns_interface_init()` which is defined in `/interface/src/os_wrapper/tfm_ns_interface_rtos.c` by trusted-firmware-m (tag: TF-Mv2.0.0) at the very beginning of your application. Otherwise, it will always fail when calling a TF-M service in the Nonsecure Side.
@@ -57,7 +57,7 @@
* `configENABLE_MVE`
The setting of this macro is decided by the setting in Secure Side which is platform-specific.
If the Secure Side enables Non-Secure access to MVE, then this macro can be configured as 0 or 1. Otherwise, this macro can only be configured as 0.
-Please note that only Cortex-M55 and Cortex-M85 support MVE.
+Please note that only Cortex-M52, Cortex-M55 and Cortex-M85 support MVE.
Please refer to [TF-M documentation](https://trustedfirmware-m.readthedocs.io/en/latest/integration_guide/tfm_fpu_support.html) for MVE usage on the Non-Secure side.
* `configENABLE_TRUSTZONE`
